1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
5 * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
7 * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
19 model = "Microchip LAN966 family SoC";
20 compatible = "microchip,lan966";
21 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a7";
32 clock-frequency = <600000000>;
39 compatible = "fixed-clock";
41 clock-frequency = <162500000>;
45 compatible = "fixed-clock";
47 clock-frequency = <600000000>;
51 compatible = "fixed-clock";
53 clock-frequency = <300000000>;
57 compatible = "fixed-clock";
59 clock-frequency = <200000000>;
63 clks: clock-controller@e00c00a8 {
64 compatible = "microchip,lan966x-gck";
66 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
67 clock-names = "cpu", "ddr", "sys";
68 reg = <0xe00c00a8 0x38>;
72 compatible = "arm,armv7-timer";
73 interrupt-parent = <&gic>;
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <37500000>;
82 compatible = "simple-bus";
87 switch: switch@e0000000 {
88 compatible = "microchip,lan966x-switch";
89 reg = <0xe0000000 0x0100000>,
90 <0xe2000000 0x0800000>;
91 reg-names = "cpu", "gcb";
92 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-names = "xtr", "fdma", "ana", "ptp",
100 reset-names = "switch";
104 #address-cells = <1>;
149 flx0: flexcom@e0040000 {
150 compatible = "atmel,sama5d2-flexcom";
151 reg = <0xe0040000 0x100>;
152 clocks = <&clks GCK_ID_FLEXCOM0>;
153 #address-cells = <1>;
155 ranges = <0x0 0xe0040000 0x800>;
159 compatible = "atmel,at91sam9260-usart";
161 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
162 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
163 <&dma0 AT91_XDMAC_DT_PERID(2)>;
164 dma-names = "tx", "rx";
166 clock-names = "usart";
167 atmel,fifo-size = <32>;
172 compatible = "atmel,at91rm9200-spi";
174 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
175 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
176 <&dma0 AT91_XDMAC_DT_PERID(2)>;
177 dma-names = "tx", "rx";
179 clock-names = "spi_clk";
180 atmel,fifo-size = <32>;
181 #address-cells = <1>;
187 compatible = "microchip,sam9x60-i2c";
189 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
190 dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
191 <&dma0 AT91_XDMAC_DT_PERID(2)>;
192 dma-names = "tx", "rx";
194 #address-cells = <1>;
200 flx1: flexcom@e0044000 {
201 compatible = "atmel,sama5d2-flexcom";
202 reg = <0xe0044000 0x100>;
203 clocks = <&clks GCK_ID_FLEXCOM1>;
204 #address-cells = <1>;
206 ranges = <0x0 0xe0044000 0x800>;
210 compatible = "atmel,at91sam9260-usart";
212 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
213 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
214 <&dma0 AT91_XDMAC_DT_PERID(4)>;
215 dma-names = "tx", "rx";
217 clock-names = "usart";
218 atmel,fifo-size = <32>;
223 compatible = "atmel,at91rm9200-spi";
225 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
226 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
227 <&dma0 AT91_XDMAC_DT_PERID(4)>;
228 dma-names = "tx", "rx";
230 clock-names = "spi_clk";
231 atmel,fifo-size = <32>;
232 #address-cells = <1>;
238 compatible = "microchip,sam9x60-i2c";
240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
241 dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
242 <&dma0 AT91_XDMAC_DT_PERID(4)>;
243 dma-names = "tx", "rx";
245 #address-cells = <1>;
252 compatible = "atmel,at91sam9g45-trng";
253 reg = <0xe0048000 0x100>;
257 aes: crypto@e004c000 {
258 compatible = "atmel,at91sam9g46-aes";
259 reg = <0xe004c000 0x100>;
260 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
261 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
262 <&dma0 AT91_XDMAC_DT_PERID(13)>;
263 dma-names = "tx", "rx";
265 clock-names = "aes_clk";
268 flx2: flexcom@e0060000 {
269 compatible = "atmel,sama5d2-flexcom";
270 reg = <0xe0060000 0x100>;
271 clocks = <&clks GCK_ID_FLEXCOM2>;
272 #address-cells = <1>;
274 ranges = <0x0 0xe0060000 0x800>;
278 compatible = "atmel,at91sam9260-usart";
280 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
281 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
282 <&dma0 AT91_XDMAC_DT_PERID(6)>;
283 dma-names = "tx", "rx";
285 clock-names = "usart";
286 atmel,fifo-size = <32>;
291 compatible = "atmel,at91rm9200-spi";
293 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
294 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
295 <&dma0 AT91_XDMAC_DT_PERID(6)>;
296 dma-names = "tx", "rx";
298 clock-names = "spi_clk";
299 atmel,fifo-size = <32>;
300 #address-cells = <1>;
306 compatible = "microchip,sam9x60-i2c";
308 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
309 dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
310 <&dma0 AT91_XDMAC_DT_PERID(6)>;
311 dma-names = "tx", "rx";
313 #address-cells = <1>;
319 flx3: flexcom@e0064000 {
320 compatible = "atmel,sama5d2-flexcom";
321 reg = <0xe0064000 0x100>;
322 clocks = <&clks GCK_ID_FLEXCOM3>;
323 #address-cells = <1>;
325 ranges = <0x0 0xe0064000 0x800>;
329 compatible = "atmel,at91sam9260-usart";
331 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
332 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
333 <&dma0 AT91_XDMAC_DT_PERID(8)>;
334 dma-names = "tx", "rx";
336 clock-names = "usart";
337 atmel,fifo-size = <32>;
342 compatible = "atmel,at91rm9200-spi";
344 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
345 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
346 <&dma0 AT91_XDMAC_DT_PERID(8)>;
347 dma-names = "tx", "rx";
349 clock-names = "spi_clk";
350 atmel,fifo-size = <32>;
351 #address-cells = <1>;
357 compatible = "microchip,sam9x60-i2c";
359 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
360 dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
361 <&dma0 AT91_XDMAC_DT_PERID(8)>;
362 dma-names = "tx", "rx";
364 #address-cells = <1>;
370 dma0: dma-controller@e0068000 {
371 compatible = "microchip,sama7g5-dma";
372 reg = <0xe0068000 0x1000>;
373 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
376 clock-names = "dma_clk";
379 sha: crypto@e006c000 {
380 compatible = "atmel,at91sam9g46-sha";
381 reg = <0xe006c000 0xec>;
382 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
383 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
386 clock-names = "sha_clk";
389 flx4: flexcom@e0070000 {
390 compatible = "atmel,sama5d2-flexcom";
391 reg = <0xe0070000 0x100>;
392 clocks = <&clks GCK_ID_FLEXCOM4>;
393 #address-cells = <1>;
395 ranges = <0x0 0xe0070000 0x800>;
399 compatible = "atmel,at91sam9260-usart";
401 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
402 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
403 <&dma0 AT91_XDMAC_DT_PERID(10)>;
404 dma-names = "tx", "rx";
406 clock-names = "usart";
407 atmel,fifo-size = <32>;
412 compatible = "atmel,at91rm9200-spi";
414 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
415 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
416 <&dma0 AT91_XDMAC_DT_PERID(10)>;
417 dma-names = "tx", "rx";
419 clock-names = "spi_clk";
420 atmel,fifo-size = <32>;
421 #address-cells = <1>;
427 compatible = "microchip,sam9x60-i2c";
429 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
430 dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
431 <&dma0 AT91_XDMAC_DT_PERID(10)>;
432 dma-names = "tx", "rx";
434 #address-cells = <1>;
440 timer0: timer@e008c000 {
441 compatible = "snps,dw-apb-timer";
442 reg = <0xe008c000 0x400>;
444 clock-names = "timer";
445 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
448 watchdog: watchdog@e0090000 {
449 compatible = "snps,dw-wdt";
450 reg = <0xe0090000 0x1000>;
451 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
456 cpu_ctrl: syscon@e00c0000 {
457 compatible = "microchip,lan966x-cpu-syscon", "syscon";
458 reg = <0xe00c0000 0x350>;
462 compatible = "bosch,m_can";
463 reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
464 reg-names = "m_can", "message_ram";
465 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
467 interrupt-names = "int0", "int1";
468 clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
469 clock-names = "hclk", "cclk";
470 assigned-clocks = <&clks GCK_ID_MCAN0>;
471 assigned-clock-rates = <40000000>;
472 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
476 reset: reset-controller@e200400c {
477 compatible = "microchip,lan966x-switch-reset";
478 reg = <0xe200400c 0x4>;
481 cpu-syscon = <&cpu_ctrl>;
484 gpio: pinctrl@e2004064 {
485 compatible = "microchip,lan966x-pinctrl";
486 reg = <0xe2004064 0xb4>,
489 reset-names = "switch";
492 gpio-ranges = <&gpio 0 0 78>;
493 interrupt-controller;
494 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
495 #interrupt-cells = <2>;
498 mdio0: mdio@e2004118 {
499 compatible = "microchip,lan966x-miim";
500 #address-cells = <1>;
502 reg = <0xe2004118 0x24>;
507 mdio1: mdio@e200413c {
508 compatible = "microchip,lan966x-miim";
509 #address-cells = <1>;
511 reg = <0xe200413c 0x24>,
516 phy0: ethernet-phy@1 {
518 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
522 phy1: ethernet-phy@2 {
524 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
529 sgpio: gpio@e2004190 {
530 compatible = "microchip,sparx5-sgpio";
531 reg = <0xe2004190 0x118>;
534 reset-names = "switch";
535 #address-cells = <1>;
540 compatible = "microchip,sparx5-sgpio-bank";
544 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
545 interrupt-controller;
546 #interrupt-cells = <3>;
550 compatible = "microchip,sparx5-sgpio-bank";
557 hwmon: hwmon@e2010180 {
558 compatible = "microchip,lan9668-hwmon";
559 reg = <0xe2010180 0xc>,
561 reg-names = "pvt", "fan";
565 serdes: serdes@e202c000 {
566 compatible = "microchip,lan966x-serdes";
567 reg = <0xe202c000 0x9c>,
573 gic: interrupt-controller@e8c11000 {
574 compatible = "arm,gic-400", "arm,cortex-a7-gic";
575 #interrupt-cells = <3>;
576 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-controller;
578 reg = <0xe8c11000 0x1000>,