Merge tag 'for-5.9-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/kdave...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / keystone-k2g-evm.dts
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Device Tree Source for K2G EVM
4  *
5  * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
6  */
7 /dts-v1/;
8
9 #include "keystone-k2g.dtsi"
10
11 / {
12         compatible =  "ti,k2g-evm", "ti,k2g", "ti,keystone";
13         model = "Texas Instruments K2G General Purpose EVM";
14
15         memory@800000000 {
16                 device_type = "memory";
17                 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
18         };
19
20         reserved-memory {
21                 #address-cells = <2>;
22                 #size-cells = <2>;
23                 ranges;
24
25                 dsp_common_memory: dsp-common-memory@81f800000 {
26                         compatible = "shared-dma-pool";
27                         reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
28                         reusable;
29                         status = "okay";
30                 };
31         };
32
33         vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
34                 compatible = "regulator-fixed";
35                 regulator-name = "mmc0_fixed";
36                 regulator-min-microvolt = <3300000>;
37                 regulator-max-microvolt = <3300000>;
38                 regulator-always-on;
39         };
40
41         vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 {
42                 compatible = "regulator-fixed";
43                 regulator-name = "ldo1";
44                 regulator-min-microvolt = <1800000>;
45                 regulator-max-microvolt = <1800000>;
46                 regulator-always-on;
47         };
48
49         hdmi: connector {
50                 compatible = "hdmi-connector";
51                 label = "hdmi";
52
53                 type = "a";
54
55                 port {
56                         hdmi_connector_in: endpoint {
57                                 remote-endpoint = <&sii9022_out>;
58                         };
59                 };
60         };
61 };
62
63 &k2g_pinctrl {
64         uart0_pins: pinmux_uart0_pins {
65                 pinctrl-single,pins = <
66                         K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart0_rxd.uart0_rxd */
67                         K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart0_txd.uart0_txd */
68                 >;
69         };
70
71         mmc0_pins: pinmux_mmc0_pins {
72                 pinctrl-single,pins = <
73                         K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat3.mmc0_dat3 */
74                         K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat2.mmc0_dat2 */
75                         K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat1.mmc0_dat1 */
76                         K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat0.mmc0_dat0 */
77                         K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_clk.mmc0_clk */
78                         K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_cmd.mmc0_cmd */
79                         K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)        /* mmc0_sdcd.gpio1_12 */
80                 >;
81         };
82
83         mmc1_pins: pinmux_mmc1_pins {
84                 pinctrl-single,pins = <
85                         K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat7.mmc1_dat7 */
86                         K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat6.mmc1_dat6 */
87                         K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat5.mmc1_dat5 */
88                         K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat4.mmc1_dat4 */
89                         K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat3.mmc1_dat3 */
90                         K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat2.mmc1_dat2 */
91                         K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat1.mmc1_dat1 */
92                         K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat0.mmc1_dat0 */
93                         K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_clk.mmc1_clk */
94                         K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_cmd.mmc1_cmd */
95                 >;
96         };
97
98         i2c0_pins: pinmux_i2c0_pins {
99                 pinctrl-single,pins = <
100                         K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c0_scl.i2c0_scl */
101                         K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c0_sda.i2c0_sda */
102                 >;
103         };
104
105         i2c1_pins: pinmux_i2c1_pins {
106                 pinctrl-single,pins = <
107                         K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c1_scl.i2c1_scl */
108                         K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c1_sda.i2c1_sda */
109                 >;
110         };
111
112         ecap0_pins: ecap0_pins {
113                 pinctrl-single,pins = <
114                         K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4)     /* pr1_mdio_data.ecap0_in_apwm0_out */
115                 >;
116         };
117
118         spi1_pins: pinmux_spi1_pins {
119                 pinctrl-single,pins = <
120                         K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_scs0.spi1_scs0 */
121                         K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_clk.spi1_clk */
122                         K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_miso.spi1_miso */
123                         K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_mosi.spi1_mosi */
124                 >;
125         };
126
127         qspi_pins: pinmux_qspi_pins {
128                 pinctrl-single,pins = <
129                         K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
130                         K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
131                         K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
132                         K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
133                         K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
134                         K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
135                         K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
136                 >;
137         };
138
139         uart2_pins: pinmux_uart2_pins {
140                 pinctrl-single,pins = <
141                         K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart2_rxd.uart2_rxd */
142                         K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart2_txd.uart2_txd */
143                 >;
144         };
145
146         dcan0_pins: pinmux_dcan0_pins {
147                 pinctrl-single,pins = <
148                         K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE0)     /* dcan0tx.dcan0tx */
149                         K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE0)     /* dcan0rx.dcan0rx */
150                 >;
151         };
152
153         dcan1_pins: pinmux_dcan1_pins {
154                 pinctrl-single,pins = <
155                         K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE1)     /* qspicsn2.dcan1tx */
156                         K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE1)     /* qspicsn3.dcan1rx */
157                 >;
158         };
159
160         emac_pins: pinmux_emac_pins {
161                 pinctrl-single,pins = <
162                         K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD1.RGMII_RXD1 */
163                         K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD2.RGMII_RXD2 */
164                         K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD3.RGMII_RXD3 */
165                         K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD0.RGMII_RXD0 */
166                         K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD0.RGMII_TXD0 */
167                         K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD1.RGMII_TXD1 */
168                         K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD2.RGMII_TXD2 */
169                         K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD3.RGMII_TXD3 */
170                         K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXCLK.RGMII_TXC */
171                         K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXEN.RGMII_TXCTL */
172                         K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXCLK.RGMII_RXC */
173                         K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXDV.RGMII_RXCTL */
174                 >;
175         };
176
177         mdio_pins: pinmux_mdio_pins {
178                 pinctrl-single,pins = <
179                         K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_CLK.MDIO_CLK */
180                         K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_DATA.MDIO_DATA */
181                 >;
182         };
183
184         vout_pins: pinmux_vout_pins {
185                 pinctrl-single,pins = <
186                         K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */
187                         K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */
188                         K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */
189                         K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */
190                         K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */
191                         K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */
192                         K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */
193                         K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */
194                         K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */
195                         K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */
196                         K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */
197                         K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */
198                         K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */
199                         K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */
200                         K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */
201                         K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */
202                         K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */
203                         K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */
204                         K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */
205                         K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */
206                         K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */
207                         K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */
208                         K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */
209                         K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */
210                         K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */
211                         K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */
212                         K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */
213                         K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */
214                         K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */
215                 >;
216         };
217 };
218
219 &uart0 {
220         pinctrl-names = "default";
221         pinctrl-0 = <&uart0_pins>;
222         status = "okay";
223 };
224
225 &gpio1 {
226         status = "okay";
227 };
228
229 &mmc0 {
230         pinctrl-names = "default";
231         pinctrl-0 = <&mmc0_pins>;
232         vmmc-supply = <&vcc3v3_dcin_reg>;
233         vqmmc-supply = <&vcc3v3_dcin_reg>;
234         cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
235         status = "okay";
236 };
237
238 &mmc1 {
239         pinctrl-names = "default";
240         pinctrl-0 = <&mmc1_pins>;
241         vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
242         vqmmc-supply = <&vcc1v8_ldo1_reg>;
243         ti,non-removable;
244         status = "okay";
245 };
246
247 &dsp0 {
248         memory-region = <&dsp_common_memory>;
249         status = "okay";
250 };
251
252 &i2c0 {
253         pinctrl-names = "default";
254         pinctrl-0 = <&i2c0_pins>;
255         status = "okay";
256
257         eeprom@50 {
258                 compatible = "atmel,24c1024";
259                 reg = <0x50>;
260         };
261 };
262
263 &keystone_usb0 {
264         status = "okay";
265 };
266
267 &usb0_phy {
268         status = "okay";
269 };
270
271 &usb0 {
272         dr_mode = "host";
273         status = "okay";
274 };
275
276 &keystone_usb1 {
277         status = "okay";
278 };
279
280 &usb1_phy {
281         status = "okay";
282 };
283
284 &usb1 {
285         dr_mode = "peripheral";
286         status = "okay";
287 };
288
289 &ecap0 {
290         status = "okay";
291         pinctrl-names = "default";
292         pinctrl-0 = <&ecap0_pins>;
293 };
294
295 &spi1 {
296         pinctrl-names = "default";
297         pinctrl-0 = <&spi1_pins>;
298         status = "okay";
299
300         spi_nor: flash@0 {
301                 #address-cells = <1>;
302                 #size-cells = <1>;
303                 compatible = "jedec,spi-nor";
304                 spi-max-frequency = <5000000>;
305                 m25p,fast-read;
306                 reg = <0>;
307
308                 partition@0 {
309                         label = "u-boot-spl";
310                         reg = <0x0 0x100000>;
311                         read-only;
312                 };
313
314                 partition@1 {
315                         label = "misc";
316                         reg = <0x100000 0xf00000>;
317                 };
318         };
319 };
320
321 &qspi {
322         status = "okay";
323         pinctrl-names = "default";
324         pinctrl-0 = <&qspi_pins>;
325         cdns,rclk-en;
326
327         flash0: m25p80@0 {
328                 compatible = "s25fl512s", "jedec,spi-nor";
329                 reg = <0>;
330                 spi-tx-bus-width = <1>;
331                 spi-rx-bus-width = <4>;
332                 spi-max-frequency = <96000000>;
333                 #address-cells = <1>;
334                 #size-cells = <1>;
335                 cdns,read-delay = <5>;
336                 cdns,tshsl-ns = <500>;
337                 cdns,tsd2d-ns = <500>;
338                 cdns,tchsh-ns = <119>;
339                 cdns,tslch-ns = <119>;
340
341                 partition@0 {
342                         label = "QSPI.u-boot-spl-os";
343                         reg = <0x00000000 0x00100000>;
344                 };
345                 partition@1 {
346                         label = "QSPI.u-boot-env";
347                         reg = <0x00100000 0x00040000>;
348                 };
349                 partition@2 {
350                         label = "QSPI.skern";
351                         reg = <0x00140000 0x0040000>;
352                 };
353                 partition@3 {
354                         label = "QSPI.pmmc-firmware";
355                         reg = <0x00180000 0x0040000>;
356                 };
357                 partition@4 {
358                         label = "QSPI.kernel";
359                         reg = <0x001C0000 0x0800000>;
360                 };
361                 partition@5 {
362                         label = "QSPI.file-system";
363                         reg = <0x009C0000 0x3640000>;
364                 };
365         };
366 };
367
368 &uart2 {
369         pinctrl-names = "default";
370         pinctrl-0 = <&uart2_pins>;
371         status = "okay";
372 };
373
374 &dcan0 {
375         pinctrl-names = "default";
376         pinctrl-0 = <&dcan0_pins>;
377         status = "okay";
378 };
379
380 &dcan1 {
381         pinctrl-names = "default";
382         pinctrl-0 = <&dcan1_pins>;
383         status = "okay";
384 };
385
386 &qmss {
387         status = "okay";
388 };
389
390 &knav_dmas {
391         status = "okay";
392 };
393
394 &mdio {
395         pinctrl-names = "default";
396         pinctrl-0 = <&mdio_pins>;
397         status = "okay";
398         ethphy0: ethernet-phy@0 {
399                 reg = <0>;
400         };
401 };
402
403 &gbe0 {
404         phy-handle = <&ethphy0>;
405         phy-mode = "rgmii-rxid";
406         status = "okay";
407 };
408
409 &netcp {
410         pinctrl-names = "default";
411         pinctrl-0 = <&emac_pins>;
412         status = "okay";
413 };
414
415 &i2c1 {
416         pinctrl-names = "default";
417         pinctrl-0 = <&i2c1_pins>;
418         status = "okay";
419         clock-frequency = <400000>;
420
421         sii9022: sii9022@3b {
422                 #sound-dai-cells = <0>;
423                 compatible = "sil,sii9022";
424                 reg = <0x3b>;
425
426                 ports {
427                         #address-cells = <1>;
428                         #size-cells = <0>;
429
430                         port@0 {
431                                 reg = <0>;
432
433                                 sii9022_in: endpoint {
434                                         remote-endpoint = <&dpi_out>;
435                                 };
436                         };
437
438                         port@1 {
439                                 reg = <1>;
440
441                                 sii9022_out: endpoint {
442                                         remote-endpoint = <&hdmi_connector_in>;
443                                 };
444                         };
445                 };
446         };
447 };
448
449 &dss {
450         pinctrl-names = "default";
451         pinctrl-0 = <&vout_pins>;
452         status = "ok";
453
454         port {
455                 dpi_out: endpoint {
456                         remote-endpoint = <&sii9022_in>;
457                         data-lines = <24>;
458                 };
459         };
460 };