arch/arm/boot/dts/intel-ixp4xx.dtsi

   1 // SPDX-License-Identifier: ISC
   2 /*
   3  * Device Tree file for Intel XScale Network Processors
   4  * in the IXP 4xx series.
   5  */
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8
   9 / {
  10         soc {
  11                 #address-cells = <1>;
  12                 #size-cells = <1>;
  13                 ranges;
  14                 compatible = "simple-bus";
  15                 interrupt-parent = <&intcon>;
  16
  17                 qmgr: queue-manager@60000000 {
  18                         compatible = "intel,ixp4xx-ahb-queue-manager";
  19                         reg = <0x60000000 0x4000>;
  20                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
  21                 };
  22
  23                 uart0: serial@c8000000 {
  24                         compatible = "intel,xscale-uart";
  25                         reg = <0xc8000000 0x1000>;
  26                         /*
  27                          * The reg-offset and reg-shift is a side effect
  28                          * of running the platform in big endian mode.
  29                          */
  30                         reg-offset = <3>;
  31                         reg-shift = <2>;
  32                         interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
  33                         clock-frequency = <14745600>;
  34                         no-loopback-test;
  35                 };
  36
  37                 gpio0: gpio@c8004000 {
  38                         compatible = "intel,ixp4xx-gpio";
  39                         reg = <0xc8004000 0x1000>;
  40                         gpio-controller;
  41                         #gpio-cells = <2>;
  42                         interrupt-controller;
  43                         #interrupt-cells = <2>;
  44                 };
  45
  46                 intcon: interrupt-controller@c8003000 {
  47                         /*
  48                          * Note: no compatible string. The subvariant of the
  49                          * chip needs to define what version it is. The
  50                          * location of the interrupt controller is fixed in
  51                          * memory across all variants.
  52                          */
  53                         reg = <0xc8003000 0x100>;
  54                         interrupt-controller;
  55                         #interrupt-cells = <2>;
  56                 };
  57
  58                 timer@c8005000 {
  59                         compatible = "intel,ixp4xx-timer";
  60                         reg = <0xc8005000 0x100>;
  61                         interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
  62                 };
  63
  64                 npe@c8006000 {
  65                         compatible = "intel,ixp4xx-network-processing-engine";
  66                         reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
  67                 };
  68         };
  69 };