1 // SPDX-License-Identifier: ISC
3 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
8 #include "intel-ixp43x.dtsi"
11 model = "Gateworks Cambria GW2358";
12 compatible = "gateworks,gw2358", "intel,ixp43x";
18 device_type = "memory";
19 reg = <0x00000000 0x8000000>;
23 bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
24 stdout-path = "uart0:115200n8";
32 compatible = "gpio-leds";
34 label = "gw2358:green:LED";
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
37 linux,default-trigger = "heartbeat";
43 compatible = "i2c-gpio";
44 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
45 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
50 compatible = "adi,ad7418";
54 compatible = "dallas,ds1672";
58 compatible = "atmel,24c08";
65 compatible = "gateworks,pld-gpio";
70 /* This PLD just handles the LED and user button */
72 compatible = "gateworks,pld-gpio";
82 compatible = "intel,ixp4xx-flash", "cfi-flash";
84 /* Enable writes on the expansion bus */
85 intel,ixp4xx-eb-write-enable = <1>;
87 * 32 MB of Flash in 0x20000 byte blocks
88 * mapped in at CS0 and CS1
90 reg = <0 0x00000000 0x2000000>;
93 compatible = "redboot-fis";
94 /* Eraseblock at 0x1fe0000 */
95 fis-index-block = <0xff>;
99 compatible = "intel,ixp4xx-compact-flash";
101 * Set up expansion bus config to a really slow timing.
102 * The CF driver will dynamically reconfigure these timings
103 * depending on selected PIO mode (0-4).
105 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
106 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
107 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
108 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
109 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
110 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
111 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
112 intel,ixp4xx-eb-mux-address-and-data = <0>;
113 intel,ixp4xx-eb-ahb-split-transfers = <0>;
114 intel,ixp4xx-eb-write-enable = <1>;
115 intel,ixp4xx-eb-byte-access = <1>;
116 /* First register set is CMD second is CTL */
117 reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>;
118 interrupt-parent = <&gpio0>;
119 interrupts = <12 IRQ_TYPE_EDGE_RISING>;
127 * In the boardfile for the Cambria from OpenWRT the interrupts
128 * are assigned one per IDSEL, so all 4 interrupts from IDSEL
129 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
130 * connected to IRQ 10 etc. I find this highly unlikely so I
131 * have instead assumed that they are rotated (swizzled) like
132 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
136 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
137 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
138 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
139 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
141 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
142 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
143 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
144 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
146 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
147 <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
148 <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
149 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
151 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
152 <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
153 <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
154 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
156 <0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
157 <0x3000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
158 <0x3000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
159 <0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
161 <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
162 <0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
163 <0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
164 <0x7800 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
169 queue-rx = <&qmgr 4>;
170 queue-txready = <&qmgr 21>;
172 phy-handle = <&phy1>;
175 #address-cells = <1>;
178 phy1: ethernet-phy@1 {
182 phy2: ethernet-phy@2 {
190 queue-rx = <&qmgr 2>;
191 queue-txready = <&qmgr 19>;
193 phy-handle = <&phy2>;
194 intel,npe-handle = <&npe 0>;