1 // SPDX-License-Identifier: ISC
3 * Device Tree file for the Gateworks Avila GW2348 board.
4 * This machine is based on IXP425.
9 #include "intel-ixp42x.dtsi"
10 #include <dt-bindings/input/input.h>
13 model = "Gateworks Avila GW2348";
14 compatible = "gateworks,gw2348", "intel,ixp42x";
19 device_type = "memory";
20 reg = <0x00000000 0x4000000>;
24 bootargs = "console=ttyS0,115200n8";
25 stdout-path = "uart0:115200n8";
33 compatible = "gpio-leds";
35 label = "gw2348:green:user";
36 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
38 linux,default-trigger = "heartbeat";
43 compatible = "i2c-gpio";
44 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
45 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
50 compatible = "adi,ad7418";
54 compatible = "dallas,ds1672";
58 compatible = "atmel,24c08";
69 compatible = "intel,ixp4xx-flash", "cfi-flash";
71 /* Enable writes on the expansion bus */
72 intel,ixp4xx-eb-write-enable = <1>;
73 /* 16 MB of Flash mapped in at CS0 */
74 reg = <0 0x00000000 0x1000000>;
77 compatible = "redboot-fis";
78 /* Eraseblock at 0x0fe0000 */
79 fis-index-block = <0x7f>;
83 compatible = "intel,ixp4xx-compact-flash";
85 * Set up expansion bus config to a really slow timing.
86 * The CF driver will dynamically reconfigure these timings
87 * depending on selected PIO mode (0-4).
89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
94 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
95 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
96 intel,ixp4xx-eb-mux-address-and-data = <0>;
97 intel,ixp4xx-eb-ahb-split-transfers = <0>;
98 intel,ixp4xx-eb-write-enable = <1>;
99 intel,ixp4xx-eb-byte-access = <1>;
100 /* First register set is CMD second is CTL (notice it uses CS2) */
101 reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>;
102 interrupt-parent = <&gpio0>;
103 interrupts = <12 IRQ_TYPE_EDGE_RISING>;
106 * FIXME: Latch LEDs or extra UARTs at CS4
114 * Taken from Avila PCI boardfile.
116 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
120 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
121 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
122 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
123 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
125 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
126 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
127 <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
128 <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
130 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
131 <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
132 <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
133 <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
135 <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
136 <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
137 <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
138 <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
144 queue-rx = <&qmgr 3>;
145 queue-txready = <&qmgr 20>;
147 phy-handle = <&phy0>;
150 #address-cells = <1>;
153 phy0: ethernet-phy@0 {
157 phy1: ethernet-phy@1 {
166 queue-rx = <&qmgr 4>;
167 queue-txready = <&qmgr 21>;
169 phy-handle = <&phy1>;