1 // SPDX-License-Identifier: ISC
3 * Device Tree file for the Arcom/Eurotech Vulcan board.
4 * This board is a single board computer in the PC/104 form factor based on
5 * IXP425, and was released around 2005. It previously had the name "Mercury".
10 #include "intel-ixp42x.dtsi"
11 #include <dt-bindings/input/input.h>
14 model = "Arcom/Eurotech Vulcan";
15 compatible = "arcom,vulcan", "intel,ixp42x";
20 device_type = "memory";
21 reg = <0x00000000 0x4000000>;
25 /* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */
26 bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";
27 stdout-path = "uart0:115200n8";
35 compatible = "w1-gpio";
36 gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
42 compatible = "intel,ixp4xx-flash", "cfi-flash";
45 * 32 MB of Flash in 0x20000 byte blocks
46 * mapped in at CS0 and CS1.
48 * The documentation mentions the existence
49 * of a 16MB version, which we conveniently
50 * ignore. Shout if you own one!
52 reg = <0 0x00000000 0x2000000>;
54 /* Expansion bus settings */
55 intel,ixp4xx-eb-t3 = <3>;
56 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
57 intel,ixp4xx-eb-write-enable = <1>;
60 compatible = "redboot-fis";
61 fis-index-block = <0x1ff>;
65 /* 256 KB SDRAM memory at CS2 */
66 compatible = "shared-dma-pool";
67 device_type = "memory";
68 reg = <2 0x00000000 0x40000>;
70 /* Expansion bus settings */
71 intel,ixp4xx-eb-t3 = <1>;
72 intel,ixp4xx-eb-t4 = <2>;
73 intel,ixp4xx-eb-ahb-split-transfers = <1>;
74 intel,ixp4xx-eb-write-enable = <1>;
75 intel,ixp4xx-eb-byte-access = <1>;
79 * 8250-compatible Exar XR16L2551 2 x UART
81 * CHECKME: if special tweaks are needed, then fix the
82 * operating system to handle it.
84 compatible = "exar,xr16l2551", "ns8250";
85 reg = <3 0x00000000 0x10>;
86 interrupt-parent = <&gpio0>;
87 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
88 clock-frequency = <1843200>;
89 /* Expansion bus settings */
90 intel,ixp4xx-eb-t3 = <3>;
91 intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */
92 intel,ixp4xx-eb-write-enable = <1>;
93 intel,ixp4xx-eb-byte-access = <1>;
97 * MMIO GPIO in one byte
99 compatible = "arcom,vulcan-gpio";
100 reg = <4 0x00000000 0x1>;
101 /* Expansion bus settings */
102 intel,ixp4xx-eb-write-enable = <1>;
103 intel,ixp4xx-eb-byte-access = <1>;
106 compatible = "maxim,max6369";
107 reg = <5 0x00000000 0x1>;
108 /* Expansion bus settings */
109 intel,ixp4xx-eb-write-enable = <1>;
110 intel,ixp4xx-eb-byte-access = <1>;
118 * Taken from Vulcan PCI boardfile.
120 * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
121 * per slot. This interrupt is shared (OR:ed) by all four pins.
125 <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
126 <0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */
127 <0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */
128 <0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */
130 <0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */
131 <0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */
132 <0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */
133 <0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */
139 queue-rx = <&qmgr 3>;
140 queue-txready = <&qmgr 20>;
142 phy-handle = <&phy0>;
145 #address-cells = <1>;
148 phy0: ethernet-phy@0 {
152 phy1: ethernet-phy@1 {
161 queue-rx = <&qmgr 4>;
162 queue-txready = <&qmgr 21>;
164 phy-handle = <&phy1>;