arch/arm/boot/dts/imx7s.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/imx7d-clock.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include "imx7d-pinfunc.h"
  47 #include "skeleton.dtsi"
  48
  49 / {
  50         aliases {
  51                 gpio0 = &gpio1;
  52                 gpio1 = &gpio2;
  53                 gpio2 = &gpio3;
  54                 gpio3 = &gpio4;
  55                 gpio4 = &gpio5;
  56                 gpio5 = &gpio6;
  57                 gpio6 = &gpio7;
  58                 i2c0 = &i2c1;
  59                 i2c1 = &i2c2;
  60                 i2c2 = &i2c3;
  61                 i2c3 = &i2c4;
  62                 mmc0 = &usdhc1;
  63                 mmc1 = &usdhc2;
  64                 mmc2 = &usdhc3;
  65                 serial0 = &uart1;
  66                 serial1 = &uart2;
  67                 serial2 = &uart3;
  68                 serial3 = &uart4;
  69                 serial4 = &uart5;
  70                 serial5 = &uart6;
  71                 serial6 = &uart7;
  72                 spi0 = &ecspi1;
  73                 spi1 = &ecspi2;
  74                 spi2 = &ecspi3;
  75                 spi3 = &ecspi4;
  76         };
  77
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu0: cpu@0 {
  83                         compatible = "arm,cortex-a7";
  84                         device_type = "cpu";
  85                         reg = <0>;
  86                         operating-points = <
  87                                 /* KHz  uV */
  88                                 996000  1075000
  89                                 792000  975000
  90                         >;
  91                         clock-latency = <61036>; /* two CLK32 periods */
  92                         clocks = <&clks IMX7D_CLK_ARM>;
  93                 };
  94
  95                 cpu1: cpu@1 {
  96                         compatible = "arm,cortex-a7";
  97                         device_type = "cpu";
  98                         reg = <1>;
  99                 };
 100         };
 101
 102         intc: interrupt-controller@31001000 {
 103                 compatible = "arm,cortex-a7-gic";
 104                 #interrupt-cells = <3>;
 105                 interrupt-controller;
 106                 reg = <0x31001000 0x1000>,
 107                       <0x31002000 0x1000>,
 108                       <0x31004000 0x2000>,
 109                       <0x31006000 0x2000>;
 110         };
 111
 112         ckil: clock-cki {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <32768>;
 116                 clock-output-names = "ckil";
 117         };
 118
 119         osc: clock-osc {
 120                 compatible = "fixed-clock";
 121                 #clock-cells = <0>;
 122                 clock-frequency = <24000000>;
 123                 clock-output-names = "osc";
 124         };
 125
 126         timer {
 127                 compatible = "arm,armv7-timer";
 128                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 129                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 130                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 131                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 132                 interrupt-parent = <&intc>;
 133         };
 134
 135         etr@30086000 {
 136                 compatible = "arm,coresight-tmc", "arm,primecell";
 137                 reg = <0x30086000 0x1000>;
 138                 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 139                 clock-names = "apb_pclk";
 140
 141                 port {
 142                         etr_in_port: endpoint {
 143                                 slave-mode;
 144                                 remote-endpoint = <&replicator_out_port1>;
 145                         };
 146                 };
 147         };
 148
 149         tpiu@30087000 {
 150                 compatible = "arm,coresight-tpiu", "arm,primecell";
 151                 reg = <0x30087000 0x1000>;
 152                 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 153                 clock-names = "apb_pclk";
 154
 155                 port {
 156                         tpiu_in_port: endpoint {
 157                                 slave-mode;
 158                                 remote-endpoint = <&replicator_out_port1>;
 159                         };
 160                 };
 161         };
 162
 163         replicator {
 164                 /*
 165                  * non-configurable replicators don't show up on the
 166                  * AMBA bus.  As such no need to add "arm,primecell"
 167                  */
 168                 compatible = "arm,coresight-replicator";
 169
 170                 ports {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173
 174                         /* replicator output ports */
 175                         port@0 {
 176                                 reg = <0>;
 177                                 replicator_out_port0: endpoint {
 178                                         remote-endpoint = <&tpiu_in_port>;
 179                                 };
 180                         };
 181
 182                         port@1 {
 183                                 reg = <1>;
 184                                 replicator_out_port1: endpoint {
 185                                         remote-endpoint = <&etr_in_port>;
 186                                 };
 187                         };
 188
 189                         /* replicator input port */
 190                         port@2 {
 191                                 reg = <0>;
 192                                 replicator_in_port0: endpoint {
 193                                         slave-mode;
 194                                         remote-endpoint = <&etf_out_port>;
 195                                 };
 196                         };
 197                 };
 198         };
 199
 200         etf@30084000 {
 201                 compatible = "arm,coresight-tmc", "arm,primecell";
 202                 reg = <0x30084000 0x1000>;
 203                 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 204                 clock-names = "apb_pclk";
 205
 206                 ports {
 207                         #address-cells = <1>;
 208                         #size-cells = <0>;
 209
 210                         port@0 {
 211                                 reg = <0>;
 212                                 etf_in_port: endpoint {
 213                                         slave-mode;
 214                                         remote-endpoint = <&hugo_funnel_out_port0>;
 215                                 };
 216                         };
 217
 218                         port@1 {
 219                                 reg = <0>;
 220                                 etf_out_port: endpoint {
 221                                         remote-endpoint = <&replicator_in_port0>;
 222                                 };
 223                         };
 224                 };
 225         };
 226
 227         funnel@30083000 {
 228                 compatible = "arm,coresight-funnel", "arm,primecell";
 229                 reg = <0x30083000 0x1000>;
 230                 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 231                 clock-names = "apb_pclk";
 232
 233                 ports {
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236
 237                         /* funnel input ports */
 238                         port@0 {
 239                                 reg = <0>;
 240                                 hugo_funnel_in_port0: endpoint {
 241                                         slave-mode;
 242                                         remote-endpoint = <&ca_funnel_out_port0>;
 243                                 };
 244                         };
 245
 246                         port@1 {
 247                                 reg = <1>;
 248                                 hugo_funnel_in_port1: endpoint {
 249                                         slave-mode; /* M4 input */
 250                                 };
 251                         };
 252
 253                         port@2 {
 254                                 reg = <0>;
 255                                 hugo_funnel_out_port0: endpoint {
 256                                         remote-endpoint = <&etf_in_port>;
 257                                 };
 258                         };
 259
 260                         /* the other input ports are not connect to anything */
 261                 };
 262         };
 263
 264         funnel@30041000 {
 265                 compatible = "arm,coresight-funnel", "arm,primecell";
 266                 reg = <0x30041000 0x1000>;
 267                 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 268                 clock-names = "apb_pclk";
 269
 270                 ports {
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273
 274                         /* funnel input ports */
 275                         port@0 {
 276                                 reg = <0>;
 277                                 ca_funnel_in_port0: endpoint {
 278                                         slave-mode;
 279                                         remote-endpoint = <&etm0_out_port>;
 280                                 };
 281                         };
 282
 283                         port@1 {
 284                                 reg = <1>;
 285                                 ca_funnel_in_port1: endpoint {
 286                                         slave-mode;
 287                                         remote-endpoint = <&etm1_out_port>;
 288                                 };
 289                         };
 290
 291                         /* funnel output port */
 292                         port@2 {
 293                                 reg = <0>;
 294                                 ca_funnel_out_port0: endpoint {
 295                                         remote-endpoint = <&hugo_funnel_in_port0>;
 296                                 };
 297                         };
 298
 299                         /* the other input ports are not connect to anything */
 300                 };
 301         };
 302
 303         etm@3007c000 {
 304                 compatible = "arm,coresight-etm3x", "arm,primecell";
 305                 reg = <0x3007c000 0x1000>;
 306                 cpu = <&cpu0>;
 307                 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 308                 clock-names = "apb_pclk";
 309
 310                 port {
 311                         etm0_out_port: endpoint {
 312                                 remote-endpoint = <&ca_funnel_in_port0>;
 313                         };
 314                 };
 315         };
 316
 317         etm@3007d000 {
 318                 compatible = "arm,coresight-etm3x", "arm,primecell";
 319                 reg = <0x3007d000 0x1000>;
 320
 321                 /*
 322                  * System will hang if added nosmp in kernel command line
 323                  * without arm,primecell-periphid because amba bus try to
 324                  * read id and core1 power off at this time.
 325                  */
 326                 arm,primecell-periphid = <0xbb956>;
 327                 cpu = <&cpu1>;
 328                 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 329                 clock-names = "apb_pclk";
 330
 331                 port {
 332                         etm1_out_port: endpoint {
 333                                 remote-endpoint = <&ca_funnel_in_port1>;
 334                         };
 335                 };
 336         };
 337
 338         soc {
 339                 #address-cells = <1>;
 340                 #size-cells = <1>;
 341                 compatible = "simple-bus";
 342                 interrupt-parent = <&intc>;
 343                 ranges;
 344
 345                 aips1: aips-bus@30000000 {
 346                         compatible = "fsl,aips-bus", "simple-bus";
 347                         #address-cells = <1>;
 348                         #size-cells = <1>;
 349                         reg = <0x30000000 0x400000>;
 350                         ranges;
 351
 352                         gpio1: gpio@30200000 {
 353                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 354                                 reg = <0x30200000 0x10000>;
 355                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
 356                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
 357                                 gpio-controller;
 358                                 #gpio-cells = <2>;
 359                                 interrupt-controller;
 360                                 #interrupt-cells = <2>;
 361                         };
 362
 363                         gpio2: gpio@30210000 {
 364                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 365                                 reg = <0x30210000 0x10000>;
 366                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 367                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 368                                 gpio-controller;
 369                                 #gpio-cells = <2>;
 370                                 interrupt-controller;
 371                                 #interrupt-cells = <2>;
 372                         };
 373
 374                         gpio3: gpio@30220000 {
 375                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 376                                 reg = <0x30220000 0x10000>;
 377                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 378                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 379                                 gpio-controller;
 380                                 #gpio-cells = <2>;
 381                                 interrupt-controller;
 382                                 #interrupt-cells = <2>;
 383                         };
 384
 385                         gpio4: gpio@30230000 {
 386                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 387                                 reg = <0x30230000 0x10000>;
 388                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 389                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 390                                 gpio-controller;
 391                                 #gpio-cells = <2>;
 392                                 interrupt-controller;
 393                                 #interrupt-cells = <2>;
 394                         };
 395
 396                         gpio5: gpio@30240000 {
 397                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 398                                 reg = <0x30240000 0x10000>;
 399                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 400                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 401                                 gpio-controller;
 402                                 #gpio-cells = <2>;
 403                                 interrupt-controller;
 404                                 #interrupt-cells = <2>;
 405                         };
 406
 407                         gpio6: gpio@30250000 {
 408                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 409                                 reg = <0x30250000 0x10000>;
 410                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 411                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 412                                 gpio-controller;
 413                                 #gpio-cells = <2>;
 414                                 interrupt-controller;
 415                                 #interrupt-cells = <2>;
 416                         };
 417
 418                         gpio7: gpio@30260000 {
 419                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
 420                                 reg = <0x30260000 0x10000>;
 421                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 422                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 423                                 gpio-controller;
 424                                 #gpio-cells = <2>;
 425                                 interrupt-controller;
 426                                 #interrupt-cells = <2>;
 427                         };
 428
 429                         wdog1: wdog@30280000 {
 430                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 431                                 reg = <0x30280000 0x10000>;
 432                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 433                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
 434                         };
 435
 436                         wdog2: wdog@30290000 {
 437                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 438                                 reg = <0x30290000 0x10000>;
 439                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 440                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
 441                                 status = "disabled";
 442                         };
 443
 444                         wdog3: wdog@302a0000 {
 445                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 446                                 reg = <0x302a0000 0x10000>;
 447                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 448                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
 449                                 status = "disabled";
 450                         };
 451
 452                         wdog4: wdog@302b0000 {
 453                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
 454                                 reg = <0x302b0000 0x10000>;
 455                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 456                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
 457                                 status = "disabled";
 458                         };
 459
 460                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
 461                                 compatible = "fsl,imx7d-iomuxc-lpsr";
 462                                 reg = <0x302c0000 0x10000>;
 463                                 fsl,input-sel = <&iomuxc>;
 464                         };
 465
 466                         gpt1: gpt@302d0000 {
 467                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 468                                 reg = <0x302d0000 0x10000>;
 469                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 470                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 471                                          <&clks IMX7D_GPT1_ROOT_CLK>;
 472                                 clock-names = "ipg", "per";
 473                         };
 474
 475                         gpt2: gpt@302e0000 {
 476                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 477                                 reg = <0x302e0000 0x10000>;
 478                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 479                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 480                                          <&clks IMX7D_GPT2_ROOT_CLK>;
 481                                 clock-names = "ipg", "per";
 482                                 status = "disabled";
 483                         };
 484
 485                         gpt3: gpt@302f0000 {
 486                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 487                                 reg = <0x302f0000 0x10000>;
 488                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 489                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 490                                          <&clks IMX7D_GPT3_ROOT_CLK>;
 491                                 clock-names = "ipg", "per";
 492                                 status = "disabled";
 493                         };
 494
 495                         gpt4: gpt@30300000 {
 496                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 497                                 reg = <0x30300000 0x10000>;
 498                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 499                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 500                                          <&clks IMX7D_GPT4_ROOT_CLK>;
 501                                 clock-names = "ipg", "per";
 502                                 status = "disabled";
 503                         };
 504
 505                         iomuxc: iomuxc@30330000 {
 506                                 compatible = "fsl,imx7d-iomuxc";
 507                                 reg = <0x30330000 0x10000>;
 508                         };
 509
 510                         gpr: iomuxc-gpr@30340000 {
 511                                 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
 512                                 reg = <0x30340000 0x10000>;
 513                         };
 514
 515                         ocotp: ocotp-ctrl@30350000 {
 516                                 compatible = "syscon";
 517                                 reg = <0x30350000 0x10000>;
 518                                 clocks = <&clks IMX7D_CLK_DUMMY>;
 519                                 status = "disabled";
 520                         };
 521
 522                         anatop: anatop@30360000 {
 523                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
 524                                         "syscon", "simple-bus";
 525                                 reg = <0x30360000 0x10000>;
 526                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 527                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 528
 529                                 reg_1p0d: regulator-vdd1p0d {
 530                                         compatible = "fsl,anatop-regulator";
 531                                         regulator-name = "vdd1p0d";
 532                                         regulator-min-microvolt = <800000>;
 533                                         regulator-max-microvolt = <1200000>;
 534                                         anatop-reg-offset = <0x210>;
 535                                         anatop-vol-bit-shift = <8>;
 536                                         anatop-vol-bit-width = <5>;
 537                                         anatop-min-bit-val = <8>;
 538                                         anatop-min-voltage = <800000>;
 539                                         anatop-max-voltage = <1200000>;
 540                                         anatop-enable-bit = <31>;
 541                                 };
 542                         };
 543
 544                         snvs: snvs@30370000 {
 545                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 546                                 reg = <0x30370000 0x10000>;
 547
 548                                 snvs_rtc: snvs-rtc-lp {
 549                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 550                                         regmap = <&snvs>;
 551                                         offset = <0x34>;
 552                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 553                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 554                                 };
 555
 556                                 snvs_poweroff: snvs-poweroff {
 557                                         compatible = "syscon-poweroff";
 558                                         regmap = <&snvs>;
 559                                         offset = <0x38>;
 560                                         mask = <0x60>;
 561                                 };
 562
 563                                 snvs_pwrkey: snvs-powerkey {
 564                                         compatible = "fsl,sec-v4.0-pwrkey";
 565                                         regmap = <&snvs>;
 566                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 567                                         linux,keycode = <KEY_POWER>;
 568                                         wakeup-source;
 569                                 };
 570                         };
 571
 572                         clks: ccm@30380000 {
 573                                 compatible = "fsl,imx7d-ccm";
 574                                 reg = <0x30380000 0x10000>;
 575                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 576                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 577                                 #clock-cells = <1>;
 578                                 clocks = <&ckil>, <&osc>;
 579                                 clock-names = "ckil", "osc";
 580                         };
 581
 582                         src: src@30390000 {
 583                                 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
 584                                 reg = <0x30390000 0x10000>;
 585                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 586                                 #reset-cells = <1>;
 587                         };
 588                 };
 589
 590                 aips2: aips-bus@30400000 {
 591                         compatible = "fsl,aips-bus", "simple-bus";
 592                         #address-cells = <1>;
 593                         #size-cells = <1>;
 594                         reg = <0x30400000 0x400000>;
 595                         ranges;
 596
 597                         adc1: adc@30610000 {
 598                                 compatible = "fsl,imx7d-adc";
 599                                 reg = <0x30610000 0x10000>;
 600                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 601                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 602                                 clock-names = "adc";
 603                                 status = "disabled";
 604                         };
 605
 606                         adc2: adc@30620000 {
 607                                 compatible = "fsl,imx7d-adc";
 608                                 reg = <0x30620000 0x10000>;
 609                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 610                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 611                                 clock-names = "adc";
 612                                 status = "disabled";
 613                         };
 614
 615                         ecspi4: ecspi@30630000 {
 616                                 #address-cells = <1>;
 617                                 #size-cells = <0>;
 618                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 619                                 reg = <0x30630000 0x10000>;
 620                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 621                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
 622                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
 623                                 clock-names = "ipg", "per";
 624                                 status = "disabled";
 625                         };
 626
 627                         pwm1: pwm@30660000 {
 628                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 629                                 reg = <0x30660000 0x10000>;
 630                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 631                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
 632                                          <&clks IMX7D_PWM1_ROOT_CLK>;
 633                                 clock-names = "ipg", "per";
 634                                 #pwm-cells = <2>;
 635                                 status = "disabled";
 636                         };
 637
 638                         pwm2: pwm@30670000 {
 639                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 640                                 reg = <0x30670000 0x10000>;
 641                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 642                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
 643                                          <&clks IMX7D_PWM2_ROOT_CLK>;
 644                                 clock-names = "ipg", "per";
 645                                 #pwm-cells = <2>;
 646                                 status = "disabled";
 647                         };
 648
 649                         pwm3: pwm@30680000 {
 650                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 651                                 reg = <0x30680000 0x10000>;
 652                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 653                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
 654                                          <&clks IMX7D_PWM3_ROOT_CLK>;
 655                                 clock-names = "ipg", "per";
 656                                 #pwm-cells = <2>;
 657                                 status = "disabled";
 658                         };
 659
 660                         pwm4: pwm@30690000 {
 661                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
 662                                 reg = <0x30690000 0x10000>;
 663                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 664                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
 665                                          <&clks IMX7D_PWM4_ROOT_CLK>;
 666                                 clock-names = "ipg", "per";
 667                                 #pwm-cells = <2>;
 668                                 status = "disabled";
 669                         };
 670
 671                         lcdif: lcdif@30730000 {
 672                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
 673                                 reg = <0x30730000 0x10000>;
 674                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 675                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
 676                                         <&clks IMX7D_CLK_DUMMY>,
 677                                         <&clks IMX7D_CLK_DUMMY>;
 678                                 clock-names = "pix", "axi", "disp_axi";
 679                                 status = "disabled";
 680                         };
 681                 };
 682
 683                 aips3: aips-bus@30800000 {
 684                         compatible = "fsl,aips-bus", "simple-bus";
 685                         #address-cells = <1>;
 686                         #size-cells = <1>;
 687                         reg = <0x30800000 0x400000>;
 688                         ranges;
 689
 690                         ecspi1: ecspi@30820000 {
 691                                 #address-cells = <1>;
 692                                 #size-cells = <0>;
 693                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 694                                 reg = <0x30820000 0x10000>;
 695                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 696                                 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 697                                         <&clks IMX7D_ECSPI1_ROOT_CLK>;
 698                                 clock-names = "ipg", "per";
 699                                 status = "disabled";
 700                         };
 701
 702                         ecspi2: ecspi@30830000 {
 703                                 #address-cells = <1>;
 704                                 #size-cells = <0>;
 705                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 706                                 reg = <0x30830000 0x10000>;
 707                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 708                                 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 709                                         <&clks IMX7D_ECSPI2_ROOT_CLK>;
 710                                 clock-names = "ipg", "per";
 711                                 status = "disabled";
 712                         };
 713
 714                         ecspi3: ecspi@30840000 {
 715                                 #address-cells = <1>;
 716                                 #size-cells = <0>;
 717                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
 718                                 reg = <0x30840000 0x10000>;
 719                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 720                                 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 721                                         <&clks IMX7D_ECSPI3_ROOT_CLK>;
 722                                 clock-names = "ipg", "per";
 723                                 status = "disabled";
 724                         };
 725
 726                         uart1: serial@30860000 {
 727                                 compatible = "fsl,imx7d-uart",
 728                                              "fsl,imx6q-uart";
 729                                 reg = <0x30860000 0x10000>;
 730                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 731                                 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
 732                                         <&clks IMX7D_UART1_ROOT_CLK>;
 733                                 clock-names = "ipg", "per";
 734                                 status = "disabled";
 735                         };
 736
 737                         uart2: serial@30890000 {
 738                                 compatible = "fsl,imx7d-uart",
 739                                              "fsl,imx6q-uart";
 740                                 reg = <0x30890000 0x10000>;
 741                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 742                                 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 743                                         <&clks IMX7D_UART2_ROOT_CLK>;
 744                                 clock-names = "ipg", "per";
 745                                 status = "disabled";
 746                         };
 747
 748                         uart3: serial@30880000 {
 749                                 compatible = "fsl,imx7d-uart",
 750                                              "fsl,imx6q-uart";
 751                                 reg = <0x30880000 0x10000>;
 752                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 753                                 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 754                                         <&clks IMX7D_UART3_ROOT_CLK>;
 755                                 clock-names = "ipg", "per";
 756                                 status = "disabled";
 757                         };
 758
 759                         flexcan1: can@30a00000 {
 760                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 761                                 reg = <0x30a00000 0x10000>;
 762                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 763                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 764                                         <&clks IMX7D_CAN1_ROOT_CLK>;
 765                                 clock-names = "ipg", "per";
 766                                 status = "disabled";
 767                         };
 768
 769                         flexcan2: can@30a10000 {
 770                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
 771                                 reg = <0x30a10000 0x10000>;
 772                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 773                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 774                                         <&clks IMX7D_CAN2_ROOT_CLK>;
 775                                 clock-names = "ipg", "per";
 776                                 status = "disabled";
 777                         };
 778
 779                         i2c1: i2c@30a20000 {
 780                                 #address-cells = <1>;
 781                                 #size-cells = <0>;
 782                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 783                                 reg = <0x30a20000 0x10000>;
 784                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 785                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
 786                                 status = "disabled";
 787                         };
 788
 789                         i2c2: i2c@30a30000 {
 790                                 #address-cells = <1>;
 791                                 #size-cells = <0>;
 792                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 793                                 reg = <0x30a30000 0x10000>;
 794                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 795                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
 796                                 status = "disabled";
 797                         };
 798
 799                         i2c3: i2c@30a40000 {
 800                                 #address-cells = <1>;
 801                                 #size-cells = <0>;
 802                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 803                                 reg = <0x30a40000 0x10000>;
 804                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 805                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
 806                                 status = "disabled";
 807                         };
 808
 809                         i2c4: i2c@30a50000 {
 810                                 #address-cells = <1>;
 811                                 #size-cells = <0>;
 812                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
 813                                 reg = <0x30a50000 0x10000>;
 814                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
 816                                 status = "disabled";
 817                         };
 818
 819                         uart4: serial@30a60000 {
 820                                 compatible = "fsl,imx7d-uart",
 821                                              "fsl,imx6q-uart";
 822                                 reg = <0x30a60000 0x10000>;
 823                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 824                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
 825                                         <&clks IMX7D_UART4_ROOT_CLK>;
 826                                 clock-names = "ipg", "per";
 827                                 status = "disabled";
 828                         };
 829
 830                         uart5: serial@30a70000 {
 831                                 compatible = "fsl,imx7d-uart",
 832                                              "fsl,imx6q-uart";
 833                                 reg = <0x30a70000 0x10000>;
 834                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 835                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
 836                                         <&clks IMX7D_UART5_ROOT_CLK>;
 837                                 clock-names = "ipg", "per";
 838                                 status = "disabled";
 839                         };
 840
 841                         uart6: serial@30a80000 {
 842                                 compatible = "fsl,imx7d-uart",
 843                                              "fsl,imx6q-uart";
 844                                 reg = <0x30a80000 0x10000>;
 845                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 846                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
 847                                         <&clks IMX7D_UART6_ROOT_CLK>;
 848                                 clock-names = "ipg", "per";
 849                                 status = "disabled";
 850                         };
 851
 852                         uart7: serial@30a90000 {
 853                                 compatible = "fsl,imx7d-uart",
 854                                              "fsl,imx6q-uart";
 855                                 reg = <0x30a90000 0x10000>;
 856                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 857                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
 858                                         <&clks IMX7D_UART7_ROOT_CLK>;
 859                                 clock-names = "ipg", "per";
 860                                 status = "disabled";
 861                         };
 862
 863                         usbotg1: usb@30b10000 {
 864                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 865                                 reg = <0x30b10000 0x200>;
 866                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 867                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 868                                 fsl,usbphy = <&usbphynop1>;
 869                                 fsl,usbmisc = <&usbmisc1 0>;
 870                                 phy-clkgate-delay-us = <400>;
 871                                 status = "disabled";
 872                         };
 873
 874                         usbotg2: usb@30b20000 {
 875                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 876                                 reg = <0x30b20000 0x200>;
 877                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 878                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 879                                 fsl,usbphy = <&usbphynop2>;
 880                                 fsl,usbmisc = <&usbmisc2 0>;
 881                                 phy-clkgate-delay-us = <400>;
 882                                 status = "disabled";
 883                         };
 884
 885                         usbh: usb@30b30000 {
 886                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 887                                 reg = <0x30b30000 0x200>;
 888                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 889                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
 890                                 fsl,usbphy = <&usbphynop3>;
 891                                 fsl,usbmisc = <&usbmisc3 0>;
 892                                 phy_type = "hsic";
 893                                 dr_mode = "host";
 894                                 phy-clkgate-delay-us = <400>;
 895                                 status = "disabled";
 896                         };
 897
 898                         usbmisc1: usbmisc@30b10200 {
 899                                 #index-cells = <1>;
 900                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 901                                 reg = <0x30b10200 0x200>;
 902                         };
 903
 904                         usbmisc2: usbmisc@30b20200 {
 905                                 #index-cells = <1>;
 906                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 907                                 reg = <0x30b20200 0x200>;
 908                         };
 909
 910                         usbmisc3: usbmisc@30b30200 {
 911                                 #index-cells = <1>;
 912                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
 913                                 reg = <0x30b30200 0x200>;
 914                         };
 915
 916                         usbphynop1: usbphynop1 {
 917                                 compatible = "usb-nop-xceiv";
 918                                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
 919                                 clock-names = "main_clk";
 920                         };
 921
 922                         usbphynop2: usbphynop2 {
 923                                 compatible = "usb-nop-xceiv";
 924                                 clocks = <&clks IMX7D_USB_PHY2_CLK>;
 925                                 clock-names = "main_clk";
 926                         };
 927
 928                         usbphynop3: usbphynop3 {
 929                                 compatible = "usb-nop-xceiv";
 930                                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
 931                                 clock-names = "main_clk";
 932                         };
 933
 934                         usdhc1: usdhc@30b40000 {
 935                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 936                                 reg = <0x30b40000 0x10000>;
 937                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 938                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 939                                         <&clks IMX7D_CLK_DUMMY>,
 940                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
 941                                 clock-names = "ipg", "ahb", "per";
 942                                 bus-width = <4>;
 943                                 status = "disabled";
 944                         };
 945
 946                         usdhc2: usdhc@30b50000 {
 947                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 948                                 reg = <0x30b50000 0x10000>;
 949                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 950                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 951                                         <&clks IMX7D_CLK_DUMMY>,
 952                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
 953                                 clock-names = "ipg", "ahb", "per";
 954                                 bus-width = <4>;
 955                                 status = "disabled";
 956                         };
 957
 958                         usdhc3: usdhc@30b60000 {
 959                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
 960                                 reg = <0x30b60000 0x10000>;
 961                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 962                                 clocks = <&clks IMX7D_CLK_DUMMY>,
 963                                         <&clks IMX7D_CLK_DUMMY>,
 964                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
 965                                 clock-names = "ipg", "ahb", "per";
 966                                 bus-width = <4>;
 967                                 status = "disabled";
 968                         };
 969
 970                         fec1: ethernet@30be0000 {
 971                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
 972                                 reg = <0x30be0000 0x10000>;
 973                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 974                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 975                                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 976                                 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 977                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 978                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
 979                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
 980                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
 981                                 clock-names = "ipg", "ahb", "ptp",
 982                                         "enet_clk_ref", "enet_out";
 983                                 fsl,num-tx-queues=<3>;
 984                                 fsl,num-rx-queues=<3>;
 985                                 status = "disabled";
 986                         };
 987
 988                         fec2: ethernet@30bf0000 {
 989                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
 990                                 reg = <0x30bf0000 0x10000>;
 991                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 992                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 993                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 994                                 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 995                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 996                                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
 997                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
 998                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
 999                                 clock-names = "ipg", "ahb", "ptp",
1000                                         "enet_clk_ref", "enet_out";
1001                                 fsl,num-tx-queues=<3>;
1002                                 fsl,num-rx-queues=<3>;
1003                                 status = "disabled";
1004                         };
1005                 };
1006         };
1007 };