Merge tag 'iio-fixes-for-5.6a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / imx7s.dtsi
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
5
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
13
14 / {
15         #address-cells = <1>;
16         #size-cells = <1>;
17         /*
18          * The decompressor and also some bootloaders rely on a
19          * pre-existing /chosen node to be available to insert the
20          * command line and merge other ATAGS info.
21          */
22         chosen {};
23
24         aliases {
25                 gpio0 = &gpio1;
26                 gpio1 = &gpio2;
27                 gpio2 = &gpio3;
28                 gpio3 = &gpio4;
29                 gpio4 = &gpio5;
30                 gpio5 = &gpio6;
31                 gpio6 = &gpio7;
32                 i2c0 = &i2c1;
33                 i2c1 = &i2c2;
34                 i2c2 = &i2c3;
35                 i2c3 = &i2c4;
36                 mmc0 = &usdhc1;
37                 mmc1 = &usdhc2;
38                 mmc2 = &usdhc3;
39                 serial0 = &uart1;
40                 serial1 = &uart2;
41                 serial2 = &uart3;
42                 serial3 = &uart4;
43                 serial4 = &uart5;
44                 serial5 = &uart6;
45                 serial6 = &uart7;
46                 spi0 = &ecspi1;
47                 spi1 = &ecspi2;
48                 spi2 = &ecspi3;
49                 spi3 = &ecspi4;
50         };
51
52         cpus {
53                 #address-cells = <1>;
54                 #size-cells = <0>;
55
56                 idle-states {
57                         entry-method = "psci";
58
59                         cpu_sleep_wait: cpu-sleep-wait {
60                                 compatible = "arm,idle-state";
61                                 arm,psci-suspend-param = <0x0010000>;
62                                 local-timer-stop;
63                                 entry-latency-us = <100>;
64                                 exit-latency-us = <50>;
65                                 min-residency-us = <1000>;
66                         };
67                 };
68
69                 cpu0: cpu@0 {
70                         compatible = "arm,cortex-a7";
71                         device_type = "cpu";
72                         reg = <0>;
73                         clock-frequency = <792000000>;
74                         clock-latency = <61036>; /* two CLK32 periods */
75                         clocks = <&clks IMX7D_CLK_ARM>;
76                         cpu-idle-states = <&cpu_sleep_wait>;
77                 };
78         };
79
80         ckil: clock-cki {
81                 compatible = "fixed-clock";
82                 #clock-cells = <0>;
83                 clock-frequency = <32768>;
84                 clock-output-names = "ckil";
85         };
86
87         osc: clock-osc {
88                 compatible = "fixed-clock";
89                 #clock-cells = <0>;
90                 clock-frequency = <24000000>;
91                 clock-output-names = "osc";
92         };
93
94         usbphynop1: usbphynop1 {
95                 compatible = "usb-nop-xceiv";
96                 clocks = <&clks IMX7D_USB_PHY1_CLK>;
97                 clock-names = "main_clk";
98                 #phy-cells = <0>;
99         };
100
101         usbphynop3: usbphynop3 {
102                 compatible = "usb-nop-xceiv";
103                 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
104                 clock-names = "main_clk";
105                 #phy-cells = <0>;
106         };
107
108         pmu {
109                 compatible = "arm,cortex-a7-pmu";
110                 interrupt-parent = <&gpc>;
111                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
112                 interrupt-affinity = <&cpu0>;
113         };
114
115         replicator {
116                 /*
117                  * non-configurable replicators don't show up on the
118                  * AMBA bus.  As such no need to add "arm,primecell"
119                  */
120                 compatible = "arm,coresight-static-replicator";
121
122                 out-ports {
123                         #address-cells = <1>;
124                         #size-cells = <0>;
125                                 /* replicator output ports */
126                         port@0 {
127                                 reg = <0>;
128                                 replicator_out_port0: endpoint {
129                                         remote-endpoint = <&tpiu_in_port>;
130                                 };
131                         };
132
133                         port@1 {
134                                 reg = <1>;
135                                 replicator_out_port1: endpoint {
136                                         remote-endpoint = <&etr_in_port>;
137                                 };
138                         };
139                 };
140
141                 in-ports {
142                         port {
143                                 replicator_in_port0: endpoint {
144                                         remote-endpoint = <&etf_out_port>;
145                                 };
146                         };
147                 };
148         };
149
150         tempmon: tempmon {
151                 compatible = "fsl,imx7d-tempmon";
152                 interrupt-parent = <&gpc>;
153                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
154                 fsl,tempmon = <&anatop>;
155                 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
156                 nvmem-cell-names = "calib", "temp_grade";
157                 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
158         };
159
160         timer {
161                 compatible = "arm,armv7-timer";
162                 interrupt-parent = <&intc>;
163                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
164                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
165                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
166                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
167         };
168
169         soc {
170                 #address-cells = <1>;
171                 #size-cells = <1>;
172                 compatible = "simple-bus";
173                 interrupt-parent = <&gpc>;
174                 ranges;
175
176                 funnel@30041000 {
177                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
178                         reg = <0x30041000 0x1000>;
179                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
180                         clock-names = "apb_pclk";
181
182                         ca_funnel_in_ports: in-ports {
183                                 port {
184                                         ca_funnel_in_port0: endpoint {
185                                                 remote-endpoint = <&etm0_out_port>;
186                                         };
187                                 };
188
189                                 /* the other input ports are not connect to anything */
190                         };
191
192                         out-ports {
193                                 port {
194                                         ca_funnel_out_port0: endpoint {
195                                                 remote-endpoint = <&hugo_funnel_in_port0>;
196                                         };
197                                 };
198
199                         };
200                 };
201
202                 etm@3007c000 {
203                         compatible = "arm,coresight-etm3x", "arm,primecell";
204                         reg = <0x3007c000 0x1000>;
205                         cpu = <&cpu0>;
206                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
207                         clock-names = "apb_pclk";
208
209                         out-ports {
210                                 port {
211                                         etm0_out_port: endpoint {
212                                                 remote-endpoint = <&ca_funnel_in_port0>;
213                                         };
214                                 };
215                         };
216                 };
217
218                 funnel@30083000 {
219                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
220                         reg = <0x30083000 0x1000>;
221                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
222                         clock-names = "apb_pclk";
223
224                         in-ports {
225                                 #address-cells = <1>;
226                                 #size-cells = <0>;
227
228                                 port@0 {
229                                         reg = <0>;
230                                         hugo_funnel_in_port0: endpoint {
231                                                 remote-endpoint = <&ca_funnel_out_port0>;
232                                         };
233                                 };
234
235                                 port@1 {
236                                         reg = <1>;
237                                         hugo_funnel_in_port1: endpoint {
238                                                 /* M4 input */
239                                         };
240                                 };
241                                 /* the other input ports are not connect to anything */
242                         };
243
244                         out-ports {
245                                 port {
246                                         hugo_funnel_out_port0: endpoint {
247                                                 remote-endpoint = <&etf_in_port>;
248                                         };
249                                 };
250                         };
251                 };
252
253                 etf@30084000 {
254                         compatible = "arm,coresight-tmc", "arm,primecell";
255                         reg = <0x30084000 0x1000>;
256                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
257                         clock-names = "apb_pclk";
258
259                         in-ports {
260                                 port {
261                                         etf_in_port: endpoint {
262                                                 remote-endpoint = <&hugo_funnel_out_port0>;
263                                         };
264                                 };
265                         };
266
267                         out-ports {
268                                 port {
269                                         etf_out_port: endpoint {
270                                                 remote-endpoint = <&replicator_in_port0>;
271                                         };
272                                 };
273                         };
274                 };
275
276                 etr@30086000 {
277                         compatible = "arm,coresight-tmc", "arm,primecell";
278                         reg = <0x30086000 0x1000>;
279                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
280                         clock-names = "apb_pclk";
281
282                         in-ports {
283                                 port {
284                                         etr_in_port: endpoint {
285                                                 remote-endpoint = <&replicator_out_port1>;
286                                         };
287                                 };
288                         };
289                 };
290
291                 tpiu@30087000 {
292                         compatible = "arm,coresight-tpiu", "arm,primecell";
293                         reg = <0x30087000 0x1000>;
294                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
295                         clock-names = "apb_pclk";
296
297                         in-ports {
298                                 port {
299                                         tpiu_in_port: endpoint {
300                                                 remote-endpoint = <&replicator_out_port0>;
301                                         };
302                                 };
303                         };
304                 };
305
306                 intc: interrupt-controller@31001000 {
307                         compatible = "arm,cortex-a7-gic";
308                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
309                         #interrupt-cells = <3>;
310                         interrupt-controller;
311                         interrupt-parent = <&intc>;
312                         reg = <0x31001000 0x1000>,
313                               <0x31002000 0x2000>,
314                               <0x31004000 0x2000>,
315                               <0x31006000 0x2000>;
316                 };
317
318                 aips1: aips-bus@30000000 {
319                         compatible = "fsl,aips-bus", "simple-bus";
320                         #address-cells = <1>;
321                         #size-cells = <1>;
322                         reg = <0x30000000 0x400000>;
323                         ranges;
324
325                         gpio1: gpio@30200000 {
326                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
327                                 reg = <0x30200000 0x10000>;
328                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
329                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
330                                 gpio-controller;
331                                 #gpio-cells = <2>;
332                                 interrupt-controller;
333                                 #interrupt-cells = <2>;
334                                 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
335                         };
336
337                         gpio2: gpio@30210000 {
338                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
339                                 reg = <0x30210000 0x10000>;
340                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
341                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
342                                 gpio-controller;
343                                 #gpio-cells = <2>;
344                                 interrupt-controller;
345                                 #interrupt-cells = <2>;
346                                 gpio-ranges = <&iomuxc 0 13 32>;
347                         };
348
349                         gpio3: gpio@30220000 {
350                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
351                                 reg = <0x30220000 0x10000>;
352                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
353                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
354                                 gpio-controller;
355                                 #gpio-cells = <2>;
356                                 interrupt-controller;
357                                 #interrupt-cells = <2>;
358                                 gpio-ranges = <&iomuxc 0 45 29>;
359                         };
360
361                         gpio4: gpio@30230000 {
362                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
363                                 reg = <0x30230000 0x10000>;
364                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
365                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
366                                 gpio-controller;
367                                 #gpio-cells = <2>;
368                                 interrupt-controller;
369                                 #interrupt-cells = <2>;
370                                 gpio-ranges = <&iomuxc 0 74 24>;
371                         };
372
373                         gpio5: gpio@30240000 {
374                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
375                                 reg = <0x30240000 0x10000>;
376                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
377                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
378                                 gpio-controller;
379                                 #gpio-cells = <2>;
380                                 interrupt-controller;
381                                 #interrupt-cells = <2>;
382                                 gpio-ranges = <&iomuxc 0 98 18>;
383                         };
384
385                         gpio6: gpio@30250000 {
386                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
387                                 reg = <0x30250000 0x10000>;
388                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
389                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
390                                 gpio-controller;
391                                 #gpio-cells = <2>;
392                                 interrupt-controller;
393                                 #interrupt-cells = <2>;
394                                 gpio-ranges = <&iomuxc 0 116 23>;
395                         };
396
397                         gpio7: gpio@30260000 {
398                                 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
399                                 reg = <0x30260000 0x10000>;
400                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
401                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
402                                 gpio-controller;
403                                 #gpio-cells = <2>;
404                                 interrupt-controller;
405                                 #interrupt-cells = <2>;
406                                 gpio-ranges = <&iomuxc 0 139 16>;
407                         };
408
409                         wdog1: wdog@30280000 {
410                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
411                                 reg = <0x30280000 0x10000>;
412                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
413                                 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
414                         };
415
416                         wdog2: wdog@30290000 {
417                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
418                                 reg = <0x30290000 0x10000>;
419                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
420                                 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
421                                 status = "disabled";
422                         };
423
424                         wdog3: wdog@302a0000 {
425                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
426                                 reg = <0x302a0000 0x10000>;
427                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
428                                 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
429                                 status = "disabled";
430                         };
431
432                         wdog4: wdog@302b0000 {
433                                 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
434                                 reg = <0x302b0000 0x10000>;
435                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
436                                 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
437                                 status = "disabled";
438                         };
439
440                         iomuxc_lpsr: iomuxc-lpsr@302c0000 {
441                                 compatible = "fsl,imx7d-iomuxc-lpsr";
442                                 reg = <0x302c0000 0x10000>;
443                                 fsl,input-sel = <&iomuxc>;
444                         };
445
446                         gpt1: gpt@302d0000 {
447                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
448                                 reg = <0x302d0000 0x10000>;
449                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
450                                 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
451                                          <&clks IMX7D_GPT1_ROOT_CLK>;
452                                 clock-names = "ipg", "per";
453                         };
454
455                         gpt2: gpt@302e0000 {
456                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
457                                 reg = <0x302e0000 0x10000>;
458                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
459                                 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
460                                          <&clks IMX7D_GPT2_ROOT_CLK>;
461                                 clock-names = "ipg", "per";
462                                 status = "disabled";
463                         };
464
465                         gpt3: gpt@302f0000 {
466                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
467                                 reg = <0x302f0000 0x10000>;
468                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
469                                 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
470                                          <&clks IMX7D_GPT3_ROOT_CLK>;
471                                 clock-names = "ipg", "per";
472                                 status = "disabled";
473                         };
474
475                         gpt4: gpt@30300000 {
476                                 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
477                                 reg = <0x30300000 0x10000>;
478                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
479                                 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
480                                          <&clks IMX7D_GPT4_ROOT_CLK>;
481                                 clock-names = "ipg", "per";
482                                 status = "disabled";
483                         };
484
485                         kpp: kpp@30320000 {
486                                 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
487                                 reg = <0x30320000 0x10000>;
488                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
489                                 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
490                                 status = "disabled";
491                         };
492
493                         iomuxc: iomuxc@30330000 {
494                                 compatible = "fsl,imx7d-iomuxc";
495                                 reg = <0x30330000 0x10000>;
496                         };
497
498                         gpr: iomuxc-gpr@30340000 {
499                                 compatible = "fsl,imx7d-iomuxc-gpr",
500                                         "fsl,imx6q-iomuxc-gpr", "syscon",
501                                         "simple-mfd";
502                                 reg = <0x30340000 0x10000>;
503
504                                 mux: mux-controller {
505                                         compatible = "mmio-mux";
506                                         #mux-control-cells = <0>;
507                                         mux-reg-masks = <0x14 0x00000010>;
508                                 };
509
510                                 video_mux: csi-mux {
511                                         compatible = "video-mux";
512                                         mux-controls = <&mux 0>;
513                                         #address-cells = <1>;
514                                         #size-cells = <0>;
515                                         status = "disabled";
516
517                                         port@0 {
518                                                 reg = <0>;
519                                         };
520
521                                         port@1 {
522                                                 reg = <1>;
523
524                                                 csi_mux_from_mipi_vc0: endpoint {
525                                                         remote-endpoint = <&mipi_vc0_to_csi_mux>;
526                                                 };
527                                         };
528
529                                         port@2 {
530                                                 reg = <2>;
531
532                                                 csi_mux_to_csi: endpoint {
533                                                         remote-endpoint = <&csi_from_csi_mux>;
534                                                 };
535                                         };
536                                 };
537                         };
538
539                         ocotp: ocotp-ctrl@30350000 {
540                                 #address-cells = <1>;
541                                 #size-cells = <1>;
542                                 compatible = "fsl,imx7d-ocotp", "syscon";
543                                 reg = <0x30350000 0x10000>;
544                                 clocks = <&clks IMX7D_OCOTP_CLK>;
545
546                                 tempmon_calib: calib@3c {
547                                         reg = <0x3c 0x4>;
548                                 };
549
550                                 fuse_grade: fuse-grade@10 {
551                                         reg = <0x10 0x4>;
552                                 };
553                         };
554
555                         anatop: anatop@30360000 {
556                                 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
557                                         "syscon", "simple-mfd";
558                                 reg = <0x30360000 0x10000>;
559                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
560                                         <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
561
562                                 reg_1p0d: regulator-vdd1p0d {
563                                         compatible = "fsl,anatop-regulator";
564                                         regulator-name = "vdd1p0d";
565                                         regulator-min-microvolt = <800000>;
566                                         regulator-max-microvolt = <1200000>;
567                                         anatop-reg-offset = <0x210>;
568                                         anatop-vol-bit-shift = <8>;
569                                         anatop-vol-bit-width = <5>;
570                                         anatop-min-bit-val = <8>;
571                                         anatop-min-voltage = <800000>;
572                                         anatop-max-voltage = <1200000>;
573                                         anatop-enable-bit = <0>;
574                                 };
575
576                                 reg_1p2: regulator-vdd1p2 {
577                                         compatible = "fsl,anatop-regulator";
578                                         regulator-name = "vdd1p2";
579                                         regulator-min-microvolt = <1100000>;
580                                         regulator-max-microvolt = <1300000>;
581                                         anatop-reg-offset = <0x220>;
582                                         anatop-vol-bit-shift = <8>;
583                                         anatop-vol-bit-width = <5>;
584                                         anatop-min-bit-val = <0x14>;
585                                         anatop-min-voltage = <1100000>;
586                                         anatop-max-voltage = <1300000>;
587                                         anatop-enable-bit = <0>;
588                                 };
589                         };
590
591                         snvs: snvs@30370000 {
592                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
593                                 reg = <0x30370000 0x10000>;
594
595                                 snvs_rtc: snvs-rtc-lp {
596                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
597                                         regmap = <&snvs>;
598                                         offset = <0x34>;
599                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
600                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
601                                         clocks = <&clks IMX7D_SNVS_CLK>;
602                                         clock-names = "snvs-rtc";
603                                 };
604
605                                 snvs_pwrkey: snvs-powerkey {
606                                         compatible = "fsl,sec-v4.0-pwrkey";
607                                         regmap = <&snvs>;
608                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
609                                         linux,keycode = <KEY_POWER>;
610                                         wakeup-source;
611                                         status = "disabled";
612                                 };
613                         };
614
615                         clks: ccm@30380000 {
616                                 compatible = "fsl,imx7d-ccm";
617                                 reg = <0x30380000 0x10000>;
618                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
619                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
620                                 #clock-cells = <1>;
621                                 clocks = <&ckil>, <&osc>;
622                                 clock-names = "ckil", "osc";
623                         };
624
625                         src: src@30390000 {
626                                 compatible = "fsl,imx7d-src", "syscon";
627                                 reg = <0x30390000 0x10000>;
628                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
629                                 #reset-cells = <1>;
630                         };
631
632                         gpc: gpc@303a0000 {
633                                 compatible = "fsl,imx7d-gpc";
634                                 reg = <0x303a0000 0x10000>;
635                                 interrupt-controller;
636                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
637                                 #interrupt-cells = <3>;
638                                 interrupt-parent = <&intc>;
639                                 #power-domain-cells = <1>;
640
641                                 pgc {
642                                         #address-cells = <1>;
643                                         #size-cells = <0>;
644
645                                         pgc_mipi_phy: power-domain@0 {
646                                                 #power-domain-cells = <0>;
647                                                 reg = <0>;
648                                                 power-supply = <&reg_1p0d>;
649                                         };
650
651                                         pgc_pcie_phy: power-domain@1 {
652                                                 #power-domain-cells = <0>;
653                                                 reg = <1>;
654                                                 power-supply = <&reg_1p0d>;
655                                         };
656
657                                         pgc_hsic_phy: power-domain@2 {
658                                                 #power-domain-cells = <0>;
659                                                 reg = <2>;
660                                                 power-supply = <&reg_1p2>;
661                                         };
662                                 };
663                         };
664                 };
665
666                 aips2: aips-bus@30400000 {
667                         compatible = "fsl,aips-bus", "simple-bus";
668                         #address-cells = <1>;
669                         #size-cells = <1>;
670                         reg = <0x30400000 0x400000>;
671                         ranges;
672
673                         adc1: adc@30610000 {
674                                 compatible = "fsl,imx7d-adc";
675                                 reg = <0x30610000 0x10000>;
676                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
677                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
678                                 clock-names = "adc";
679                                 #io-channel-cells = <1>;
680                                 status = "disabled";
681                         };
682
683                         adc2: adc@30620000 {
684                                 compatible = "fsl,imx7d-adc";
685                                 reg = <0x30620000 0x10000>;
686                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
687                                 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
688                                 clock-names = "adc";
689                                 #io-channel-cells = <1>;
690                                 status = "disabled";
691                         };
692
693                         ecspi4: spi@30630000 {
694                                 #address-cells = <1>;
695                                 #size-cells = <0>;
696                                 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
697                                 reg = <0x30630000 0x10000>;
698                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
699                                 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
700                                         <&clks IMX7D_ECSPI4_ROOT_CLK>;
701                                 clock-names = "ipg", "per";
702                                 status = "disabled";
703                         };
704
705                         pwm1: pwm@30660000 {
706                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
707                                 reg = <0x30660000 0x10000>;
708                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
709                                 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
710                                          <&clks IMX7D_PWM1_ROOT_CLK>;
711                                 clock-names = "ipg", "per";
712                                 #pwm-cells = <3>;
713                                 status = "disabled";
714                         };
715
716                         pwm2: pwm@30670000 {
717                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
718                                 reg = <0x30670000 0x10000>;
719                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
720                                 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
721                                          <&clks IMX7D_PWM2_ROOT_CLK>;
722                                 clock-names = "ipg", "per";
723                                 #pwm-cells = <3>;
724                                 status = "disabled";
725                         };
726
727                         pwm3: pwm@30680000 {
728                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
729                                 reg = <0x30680000 0x10000>;
730                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
731                                 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
732                                          <&clks IMX7D_PWM3_ROOT_CLK>;
733                                 clock-names = "ipg", "per";
734                                 #pwm-cells = <3>;
735                                 status = "disabled";
736                         };
737
738                         pwm4: pwm@30690000 {
739                                 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
740                                 reg = <0x30690000 0x10000>;
741                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
742                                 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
743                                          <&clks IMX7D_PWM4_ROOT_CLK>;
744                                 clock-names = "ipg", "per";
745                                 #pwm-cells = <3>;
746                                 status = "disabled";
747                         };
748
749                         csi: csi@30710000 {
750                                 compatible = "fsl,imx7-csi";
751                                 reg = <0x30710000 0x10000>;
752                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
753                                 clocks = <&clks IMX7D_CLK_DUMMY>,
754                                          <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
755                                          <&clks IMX7D_CLK_DUMMY>;
756                                 clock-names = "axi", "mclk", "dcic";
757                                 status = "disabled";
758
759                                 port {
760                                         csi_from_csi_mux: endpoint {
761                                                 remote-endpoint = <&csi_mux_to_csi>;
762                                         };
763                                 };
764                         };
765
766                         lcdif: lcdif@30730000 {
767                                 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
768                                 reg = <0x30730000 0x10000>;
769                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
770                                 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
771                                         <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
772                                 clock-names = "pix", "axi";
773                                 status = "disabled";
774                         };
775
776                         mipi_csi: mipi-csi@30750000 {
777                                 compatible = "fsl,imx7-mipi-csi2";
778                                 reg = <0x30750000 0x10000>;
779                                 #address-cells = <1>;
780                                 #size-cells = <0>;
781                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
782                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
783                                          <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
784                                          <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
785                                 clock-names = "pclk", "wrap", "phy";
786                                 power-domains = <&pgc_mipi_phy>;
787                                 phy-supply = <&reg_1p0d>;
788                                 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
789                                 reset-names = "mrst";
790                                 status = "disabled";
791
792                                 port@0 {
793                                         reg = <0>;
794                                 };
795
796                                 port@1 {
797                                         reg = <1>;
798
799                                         mipi_vc0_to_csi_mux: endpoint {
800                                                 remote-endpoint = <&csi_mux_from_mipi_vc0>;
801                                         };
802                                 };
803                         };
804                 };
805
806                 aips3: aips-bus@30800000 {
807                         compatible = "fsl,aips-bus", "simple-bus";
808                         #address-cells = <1>;
809                         #size-cells = <1>;
810                         reg = <0x30800000 0x400000>;
811                         ranges;
812
813                         spba-bus@30800000 {
814                                 compatible = "fsl,spba-bus", "simple-bus";
815                                 #address-cells = <1>;
816                                 #size-cells = <1>;
817                                 reg = <0x30800000 0x100000>;
818                                 ranges;
819
820                                 ecspi1: spi@30820000 {
821                                         #address-cells = <1>;
822                                         #size-cells = <0>;
823                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
824                                         reg = <0x30820000 0x10000>;
825                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
826                                         clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
827                                                 <&clks IMX7D_ECSPI1_ROOT_CLK>;
828                                         clock-names = "ipg", "per";
829                                         status = "disabled";
830                                 };
831
832                                 ecspi2: spi@30830000 {
833                                         #address-cells = <1>;
834                                         #size-cells = <0>;
835                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
836                                         reg = <0x30830000 0x10000>;
837                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
838                                         clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
839                                                 <&clks IMX7D_ECSPI2_ROOT_CLK>;
840                                         clock-names = "ipg", "per";
841                                         status = "disabled";
842                                 };
843
844                                 ecspi3: spi@30840000 {
845                                         #address-cells = <1>;
846                                         #size-cells = <0>;
847                                         compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
848                                         reg = <0x30840000 0x10000>;
849                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
850                                         clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
851                                                 <&clks IMX7D_ECSPI3_ROOT_CLK>;
852                                         clock-names = "ipg", "per";
853                                         status = "disabled";
854                                 };
855
856                                 uart1: serial@30860000 {
857                                         compatible = "fsl,imx7d-uart",
858                                                      "fsl,imx6q-uart";
859                                         reg = <0x30860000 0x10000>;
860                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
861                                         clocks = <&clks IMX7D_UART1_ROOT_CLK>,
862                                                 <&clks IMX7D_UART1_ROOT_CLK>;
863                                         clock-names = "ipg", "per";
864                                         status = "disabled";
865                                 };
866
867                                 uart2: serial@30890000 {
868                                         compatible = "fsl,imx7d-uart",
869                                                      "fsl,imx6q-uart";
870                                         reg = <0x30890000 0x10000>;
871                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
872                                         clocks = <&clks IMX7D_UART2_ROOT_CLK>,
873                                                 <&clks IMX7D_UART2_ROOT_CLK>;
874                                         clock-names = "ipg", "per";
875                                         status = "disabled";
876                                 };
877
878                                 uart3: serial@30880000 {
879                                         compatible = "fsl,imx7d-uart",
880                                                      "fsl,imx6q-uart";
881                                         reg = <0x30880000 0x10000>;
882                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
883                                         clocks = <&clks IMX7D_UART3_ROOT_CLK>,
884                                                 <&clks IMX7D_UART3_ROOT_CLK>;
885                                         clock-names = "ipg", "per";
886                                         status = "disabled";
887                                 };
888
889                                 sai1: sai@308a0000 {
890                                         #sound-dai-cells = <0>;
891                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
892                                         reg = <0x308a0000 0x10000>;
893                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
894                                         clocks = <&clks IMX7D_SAI1_IPG_CLK>,
895                                                  <&clks IMX7D_SAI1_ROOT_CLK>,
896                                                  <&clks IMX7D_CLK_DUMMY>,
897                                                  <&clks IMX7D_CLK_DUMMY>;
898                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
899                                         dma-names = "rx", "tx";
900                                         dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
901                                         status = "disabled";
902                                 };
903
904                                 sai2: sai@308b0000 {
905                                         #sound-dai-cells = <0>;
906                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
907                                         reg = <0x308b0000 0x10000>;
908                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
909                                         clocks = <&clks IMX7D_SAI2_IPG_CLK>,
910                                                  <&clks IMX7D_SAI2_ROOT_CLK>,
911                                                  <&clks IMX7D_CLK_DUMMY>,
912                                                  <&clks IMX7D_CLK_DUMMY>;
913                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
914                                         dma-names = "rx", "tx";
915                                         dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
916                                         status = "disabled";
917                                 };
918
919                                 sai3: sai@308c0000 {
920                                         #sound-dai-cells = <0>;
921                                         compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
922                                         reg = <0x308c0000 0x10000>;
923                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
924                                         clocks = <&clks IMX7D_SAI3_IPG_CLK>,
925                                                  <&clks IMX7D_SAI3_ROOT_CLK>,
926                                                  <&clks IMX7D_CLK_DUMMY>,
927                                                  <&clks IMX7D_CLK_DUMMY>;
928                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
929                                         dma-names = "rx", "tx";
930                                         dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
931                                         status = "disabled";
932                                 };
933                         };
934
935                         crypto: caam@30900000 {
936                                 compatible = "fsl,sec-v4.0";
937                                 #address-cells = <1>;
938                                 #size-cells = <1>;
939                                 reg = <0x30900000 0x40000>;
940                                 ranges = <0 0x30900000 0x40000>;
941                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
942                                 clocks = <&clks IMX7D_CAAM_CLK>,
943                                          <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
944                                 clock-names = "ipg", "aclk";
945
946                                 sec_jr0: jr0@1000 {
947                                         compatible = "fsl,sec-v4.0-job-ring";
948                                         reg = <0x1000 0x1000>;
949                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
950                                 };
951
952                                 sec_jr1: jr1@2000 {
953                                         compatible = "fsl,sec-v4.0-job-ring";
954                                         reg = <0x2000 0x1000>;
955                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
956                                 };
957
958                                 sec_jr2: jr1@3000 {
959                                         compatible = "fsl,sec-v4.0-job-ring";
960                                         reg = <0x3000 0x1000>;
961                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
962                                 };
963                         };
964
965                         flexcan1: can@30a00000 {
966                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
967                                 reg = <0x30a00000 0x10000>;
968                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
969                                 clocks = <&clks IMX7D_CLK_DUMMY>,
970                                         <&clks IMX7D_CAN1_ROOT_CLK>;
971                                 clock-names = "ipg", "per";
972                                 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
973                                 status = "disabled";
974                         };
975
976                         flexcan2: can@30a10000 {
977                                 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
978                                 reg = <0x30a10000 0x10000>;
979                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
980                                 clocks = <&clks IMX7D_CLK_DUMMY>,
981                                         <&clks IMX7D_CAN2_ROOT_CLK>;
982                                 clock-names = "ipg", "per";
983                                 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
984                                 status = "disabled";
985                         };
986
987                         i2c1: i2c@30a20000 {
988                                 #address-cells = <1>;
989                                 #size-cells = <0>;
990                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
991                                 reg = <0x30a20000 0x10000>;
992                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
993                                 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
994                                 status = "disabled";
995                         };
996
997                         i2c2: i2c@30a30000 {
998                                 #address-cells = <1>;
999                                 #size-cells = <0>;
1000                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1001                                 reg = <0x30a30000 0x10000>;
1002                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1003                                 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1004                                 status = "disabled";
1005                         };
1006
1007                         i2c3: i2c@30a40000 {
1008                                 #address-cells = <1>;
1009                                 #size-cells = <0>;
1010                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1011                                 reg = <0x30a40000 0x10000>;
1012                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1013                                 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1014                                 status = "disabled";
1015                         };
1016
1017                         i2c4: i2c@30a50000 {
1018                                 #address-cells = <1>;
1019                                 #size-cells = <0>;
1020                                 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1021                                 reg = <0x30a50000 0x10000>;
1022                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1023                                 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1024                                 status = "disabled";
1025                         };
1026
1027                         uart4: serial@30a60000 {
1028                                 compatible = "fsl,imx7d-uart",
1029                                              "fsl,imx6q-uart";
1030                                 reg = <0x30a60000 0x10000>;
1031                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1032                                 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1033                                         <&clks IMX7D_UART4_ROOT_CLK>;
1034                                 clock-names = "ipg", "per";
1035                                 status = "disabled";
1036                         };
1037
1038                         uart5: serial@30a70000 {
1039                                 compatible = "fsl,imx7d-uart",
1040                                              "fsl,imx6q-uart";
1041                                 reg = <0x30a70000 0x10000>;
1042                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1043                                 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1044                                         <&clks IMX7D_UART5_ROOT_CLK>;
1045                                 clock-names = "ipg", "per";
1046                                 status = "disabled";
1047                         };
1048
1049                         uart6: serial@30a80000 {
1050                                 compatible = "fsl,imx7d-uart",
1051                                              "fsl,imx6q-uart";
1052                                 reg = <0x30a80000 0x10000>;
1053                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1054                                 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1055                                         <&clks IMX7D_UART6_ROOT_CLK>;
1056                                 clock-names = "ipg", "per";
1057                                 status = "disabled";
1058                         };
1059
1060                         uart7: serial@30a90000 {
1061                                 compatible = "fsl,imx7d-uart",
1062                                              "fsl,imx6q-uart";
1063                                 reg = <0x30a90000 0x10000>;
1064                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1065                                 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1066                                         <&clks IMX7D_UART7_ROOT_CLK>;
1067                                 clock-names = "ipg", "per";
1068                                 status = "disabled";
1069                         };
1070
1071                         mu0a: mailbox@30aa0000 {
1072                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1073                                 reg = <0x30aa0000 0x10000>;
1074                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1075                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1076                                 #mbox-cells = <2>;
1077                                 status = "disabled";
1078                         };
1079
1080                         mu0b: mailbox@30ab0000 {
1081                                 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1082                                 reg = <0x30ab0000 0x10000>;
1083                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1084                                 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1085                                 #mbox-cells = <2>;
1086                                 fsl,mu-side-b;
1087                                 status = "disabled";
1088                         };
1089
1090                         usbotg1: usb@30b10000 {
1091                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1092                                 reg = <0x30b10000 0x200>;
1093                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1094                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1095                                 fsl,usbphy = <&usbphynop1>;
1096                                 fsl,usbmisc = <&usbmisc1 0>;
1097                                 phy-clkgate-delay-us = <400>;
1098                                 status = "disabled";
1099                         };
1100
1101                         usbh: usb@30b30000 {
1102                                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1103                                 reg = <0x30b30000 0x200>;
1104                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1105                                 power-domains = <&pgc_hsic_phy>;
1106                                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1107                                 fsl,usbphy = <&usbphynop3>;
1108                                 fsl,usbmisc = <&usbmisc3 0>;
1109                                 phy_type = "hsic";
1110                                 dr_mode = "host";
1111                                 phy-clkgate-delay-us = <400>;
1112                                 status = "disabled";
1113                         };
1114
1115                         usbmisc1: usbmisc@30b10200 {
1116                                 #index-cells = <1>;
1117                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1118                                 reg = <0x30b10200 0x200>;
1119                         };
1120
1121                         usbmisc3: usbmisc@30b30200 {
1122                                 #index-cells = <1>;
1123                                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1124                                 reg = <0x30b30200 0x200>;
1125                         };
1126
1127                         usdhc1: usdhc@30b40000 {
1128                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1129                                 reg = <0x30b40000 0x10000>;
1130                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1131                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1132                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1133                                         <&clks IMX7D_USDHC1_ROOT_CLK>;
1134                                 clock-names = "ipg", "ahb", "per";
1135                                 bus-width = <4>;
1136                                 status = "disabled";
1137                         };
1138
1139                         usdhc2: usdhc@30b50000 {
1140                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1141                                 reg = <0x30b50000 0x10000>;
1142                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1143                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1144                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1145                                         <&clks IMX7D_USDHC2_ROOT_CLK>;
1146                                 clock-names = "ipg", "ahb", "per";
1147                                 bus-width = <4>;
1148                                 status = "disabled";
1149                         };
1150
1151                         usdhc3: usdhc@30b60000 {
1152                                 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1153                                 reg = <0x30b60000 0x10000>;
1154                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1155                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1156                                         <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1157                                         <&clks IMX7D_USDHC3_ROOT_CLK>;
1158                                 clock-names = "ipg", "ahb", "per";
1159                                 bus-width = <4>;
1160                                 status = "disabled";
1161                         };
1162
1163                         sdma: sdma@30bd0000 {
1164                                 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1165                                 reg = <0x30bd0000 0x10000>;
1166                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1167                                 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1168                                          <&clks IMX7D_SDMA_CORE_CLK>;
1169                                 clock-names = "ipg", "ahb";
1170                                 #dma-cells = <3>;
1171                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1172                         };
1173
1174                         fec1: ethernet@30be0000 {
1175                                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1176                                 reg = <0x30be0000 0x10000>;
1177                                 interrupt-names = "int0", "int1", "int2", "pps";
1178                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1179                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1180                                         <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1181                                         <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1182                                 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1183                                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1184                                         <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1185                                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1186                                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1187                                 clock-names = "ipg", "ahb", "ptp",
1188                                         "enet_clk_ref", "enet_out";
1189                                 fsl,num-tx-queues = <3>;
1190                                 fsl,num-rx-queues = <3>;
1191                                 status = "disabled";
1192                         };
1193                 };
1194
1195                 dma_apbh: dma-apbh@33000000 {
1196                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1197                         reg = <0x33000000 0x2000>;
1198                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1202                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1203                         #dma-cells = <1>;
1204                         dma-channels = <4>;
1205                         clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1206                 };
1207
1208                 gpmi: gpmi-nand@33002000{
1209                         compatible = "fsl,imx7d-gpmi-nand";
1210                         #address-cells = <1>;
1211                         #size-cells = <1>;
1212                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1213                         reg-names = "gpmi-nand", "bch";
1214                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1215                         interrupt-names = "bch";
1216                         clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1217                                 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1218                         clock-names = "gpmi_io", "gpmi_bch_apb";
1219                         dmas = <&dma_apbh 0>;
1220                         dma-names = "rx-tx";
1221                         status = "disabled";
1222                         assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1223                         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1224                 };
1225         };
1226 };