1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
7 #include <dt-bindings/reset/imx7-reset.h>
12 clock-frequency = <996000000>;
13 operating-points-v2 = <&cpu0_opp_table>;
18 compatible = "arm,cortex-a7";
21 clock-frequency = <996000000>;
22 operating-points-v2 = <&cpu0_opp_table>;
23 cpu-idle-states = <&cpu_sleep_wait>;
28 compatible = "arm,armv7-timer";
29 interrupt-parent = <&intc>;
30 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
31 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
32 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
33 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
36 cpu0_opp_table: opp-table {
37 compatible = "operating-points-v2";
41 opp-hz = /bits/ 64 <792000000>;
42 opp-microvolt = <975000>;
43 clock-latency-ns = <150000>;
47 opp-hz = /bits/ 64 <996000000>;
48 opp-microvolt = <1075000>;
49 clock-latency-ns = <150000>;
54 usbphynop2: usbphynop2 {
55 compatible = "usb-nop-xceiv";
56 clocks = <&clks IMX7D_USB_PHY2_CLK>;
57 clock-names = "main_clk";
63 compatible = "arm,coresight-etm3x", "arm,primecell";
64 reg = <0x3007d000 0x1000>;
67 * System will hang if added nosmp in kernel command line
68 * without arm,primecell-periphid because amba bus try to
69 * read id and core1 power off at this time.
71 arm,primecell-periphid = <0xbb956>;
73 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
74 clock-names = "apb_pclk";
78 etm1_out_port: endpoint {
79 remote-endpoint = <&ca_funnel_in_port1>;
85 intc: interrupt-controller@31001000 {
86 compatible = "arm,cortex-a7-gic";
87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
88 #interrupt-cells = <3>;
90 interrupt-parent = <&intc>;
91 reg = <0x31001000 0x1000>,
100 pcie_phy: pcie-phy@306d0000 {
101 compatible = "fsl,imx7d-pcie-phy";
102 reg = <0x306d0000 0x10000>;
108 usbotg2: usb@30b20000 {
109 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
110 reg = <0x30b20000 0x200>;
111 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks IMX7D_USB_CTRL_CLK>;
113 fsl,usbphy = <&usbphynop2>;
114 fsl,usbmisc = <&usbmisc2 0>;
115 phy-clkgate-delay-us = <400>;
119 usbmisc2: usbmisc@30b20200 {
121 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
122 reg = <0x30b20200 0x200>;
125 fec2: ethernet@30bf0000 {
126 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
127 reg = <0x30bf0000 0x10000>;
128 interrupt-names = "int0", "int1", "int2", "pps";
129 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
134 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
135 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
136 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
137 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
138 clock-names = "ipg", "ahb", "ptp",
139 "enet_clk_ref", "enet_out";
140 fsl,num-tx-queues=<3>;
141 fsl,num-rx-queues=<3>;
145 pcie: pcie@33800000 {
146 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
147 reg = <0x33800000 0x4000>,
148 <0x4ff00000 0x80000>;
149 reg-names = "dbi", "config";
150 #address-cells = <3>;
153 bus-range = <0x00 0xff>;
154 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
155 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
158 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-names = "msi";
160 #interrupt-cells = <1>;
161 interrupt-map-mask = <0 0 0 0x7>;
163 * Reference manual lists pci irqs incorrectly
164 * Real hardware ordering is same as imx6: D+MSI, C, B, A
166 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
167 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
168 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
169 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
171 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
172 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
173 clock-names = "pcie", "pcie_bus", "pcie_phy";
174 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
175 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
176 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
177 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
179 fsl,max-link-speed = <2>;
180 power-domains = <&pgc_pcie_phy>;
181 resets = <&src IMX7_RESET_PCIEPHY>,
182 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
183 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
184 reset-names = "pciephy", "apps", "turnoff";
185 fsl,imx7d-pcie-phy = <&pcie_phy>;
190 &ca_funnel_in_ports {
191 #address-cells = <1>;
196 ca_funnel_in_port1: endpoint {
197 remote-endpoint = <&etm1_out_port>;