2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Copyright 2016 Toradex AG
5 * This file is dual-licensed: you can use it either under the terms
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7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
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17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
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45 #include <dt-bindings/reset/imx7-reset.h>
55 clock-frequency = <996000000>;
59 compatible = "arm,cortex-a7";
62 clock-frequency = <996000000>;
68 compatible = "arm,coresight-etm3x", "arm,primecell";
69 reg = <0x3007d000 0x1000>;
72 * System will hang if added nosmp in kernel command line
73 * without arm,primecell-periphid because amba bus try to
74 * read id and core1 power off at this time.
76 arm,primecell-periphid = <0xbb956>;
78 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
79 clock-names = "apb_pclk";
82 etm1_out_port: endpoint {
83 remote-endpoint = <&ca_funnel_in_port1>;
91 usbotg2: usb@30b20000 {
92 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
93 reg = <0x30b20000 0x200>;
94 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&clks IMX7D_USB_CTRL_CLK>;
96 fsl,usbphy = <&usbphynop2>;
97 fsl,usbmisc = <&usbmisc2 0>;
98 phy-clkgate-delay-us = <400>;
102 usbmisc2: usbmisc@30b20200 {
104 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
105 reg = <0x30b20200 0x200>;
108 usbphynop2: usbphynop2 {
109 compatible = "usb-nop-xceiv";
110 clocks = <&clks IMX7D_USB_PHY2_CLK>;
111 clock-names = "main_clk";
114 fec2: ethernet@30bf0000 {
115 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
116 reg = <0x30bf0000 0x10000>;
117 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
121 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
122 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
123 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
124 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
125 clock-names = "ipg", "ahb", "ptp",
126 "enet_clk_ref", "enet_out";
127 fsl,num-tx-queues=<3>;
128 fsl,num-rx-queues=<3>;
132 pcie: pcie@0x33800000 {
133 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
134 reg = <0x33800000 0x4000>,
135 <0x4ff00000 0x80000>;
136 reg-names = "dbi", "config";
137 #address-cells = <3>;
140 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
141 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
143 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
144 interrupt-names = "msi";
145 #interrupt-cells = <1>;
146 interrupt-map-mask = <0 0 0 0x7>;
147 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
148 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
149 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
152 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
153 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
154 clock-names = "pcie", "pcie_bus", "pcie_phy";
155 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
156 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
157 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
158 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
160 fsl,max-link-speed = <2>;
161 power-domains = <&pgc_pcie_phy>;
162 resets = <&src IMX7_RESET_PCIEPHY>,
163 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
164 reset-names = "pciephy", "apps";
172 ca_funnel_in_port1: endpoint {
174 remote-endpoint = <&etm1_out_port>;