arch/arm/boot/dts/imx7d.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2015 Freescale Semiconductor, Inc.
   4 // Copyright 2016 Toradex AG
   5
   6 #include "imx7s.dtsi"
   7 #include <dt-bindings/reset/imx7-reset.h>
   8
   9 / {
  10         cpus {
  11                 cpu0: cpu@0 {
  12                         operating-points = <
  13                                 /* KHz  uV */
  14                                 996000  1075000
  15                                 792000  975000
  16                         >;
  17                         clock-frequency = <996000000>;
  18                 };
  19
  20                 cpu1: cpu@1 {
  21                         compatible = "arm,cortex-a7";
  22                         device_type = "cpu";
  23                         reg = <1>;
  24                         clock-frequency = <996000000>;
  25                 };
  26         };
  27
  28         usbphynop2: usbphynop2 {
  29                 compatible = "usb-nop-xceiv";
  30                 clocks = <&clks IMX7D_USB_PHY2_CLK>;
  31                 clock-names = "main_clk";
  32                 #phy-cells = <0>;
  33         };
  34
  35         soc {
  36                 etm@3007d000 {
  37                         compatible = "arm,coresight-etm3x", "arm,primecell";
  38                         reg = <0x3007d000 0x1000>;
  39
  40                         /*
  41                          * System will hang if added nosmp in kernel command line
  42                          * without arm,primecell-periphid because amba bus try to
  43                          * read id and core1 power off at this time.
  44                          */
  45                         arm,primecell-periphid = <0xbb956>;
  46                         cpu = <&cpu1>;
  47                         clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
  48                         clock-names = "apb_pclk";
  49
  50                         port {
  51                                 etm1_out_port: endpoint {
  52                                         remote-endpoint = <&ca_funnel_in_port1>;
  53                                 };
  54                         };
  55                 };
  56         };
  57 };
  58
  59 &aips3 {
  60         usbotg2: usb@30b20000 {
  61                 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
  62                 reg = <0x30b20000 0x200>;
  63                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  64                 clocks = <&clks IMX7D_USB_CTRL_CLK>;
  65                 fsl,usbphy = <&usbphynop2>;
  66                 fsl,usbmisc = <&usbmisc2 0>;
  67                 phy-clkgate-delay-us = <400>;
  68                 status = "disabled";
  69         };
  70
  71         usbmisc2: usbmisc@30b20200 {
  72                 #index-cells = <1>;
  73                 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
  74                 reg = <0x30b20200 0x200>;
  75         };
  76
  77         fec2: ethernet@30bf0000 {
  78                 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
  79                 reg = <0x30bf0000 0x10000>;
  80                 interrupt-names = "int0", "int1", "int2", "pps";
  81                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  82                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  83                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  84                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
  85                 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
  86                         <&clks IMX7D_ENET_AXI_ROOT_CLK>,
  87                         <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
  88                         <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
  89                         <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
  90                 clock-names = "ipg", "ahb", "ptp",
  91                         "enet_clk_ref", "enet_out";
  92                 fsl,num-tx-queues=<3>;
  93                 fsl,num-rx-queues=<3>;
  94                 status = "disabled";
  95         };
  96
  97         pcie: pcie@33800000 {
  98                 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
  99                 reg = <0x33800000 0x4000>,
 100                       <0x4ff00000 0x80000>;
 101                 reg-names = "dbi", "config";
 102                 #address-cells = <3>;
 103                 #size-cells = <2>;
 104                 device_type = "pci";
 105                 bus-range = <0x00 0xff>;
 106                 ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
 107                           0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
 108                 num-lanes = <1>;
 109                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 110                 interrupt-names = "msi";
 111                 #interrupt-cells = <1>;
 112                 interrupt-map-mask = <0 0 0 0x7>;
 113                 interrupt-map = <0 0 0 1 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 114                                 <0 0 0 2 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 115                                 <0 0 0 3 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 116                                 <0 0 0 4 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 117                 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
 118                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
 119                          <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
 120                 clock-names = "pcie", "pcie_bus", "pcie_phy";
 121                 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
 122                                   <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
 123                 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
 124                                          <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 125
 126                 fsl,max-link-speed = <2>;
 127                 power-domains = <&pgc_pcie_phy>;
 128                 resets = <&src IMX7_RESET_PCIEPHY>,
 129                          <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
 130                 reset-names = "pciephy", "apps";
 131                 status = "disabled";
 132         };
 133 };
 134
 135 &ca_funnel_ports {
 136         port@1 {
 137                 reg = <1>;
 138                 ca_funnel_in_port1: endpoint {
 139                         slave-mode;
 140                         remote-endpoint = <&etm1_out_port>;
 141                 };
 142         };
 143 };