1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
7 #include <dt-bindings/reset/imx7-reset.h>
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
26 compatible = "arm,cortex-a7";
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
32 cpu-idle-states = <&cpu_sleep_wait>;
37 compatible = "arm,armv7-timer";
38 interrupt-parent = <&intc>;
39 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
40 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
41 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
45 cpu0_opp_table: opp-table {
46 compatible = "operating-points-v2";
50 opp-hz = /bits/ 64 <792000000>;
51 opp-microvolt = <1000000>;
52 clock-latency-ns = <150000>;
53 opp-supported-hw = <0xd>, <0x7>;
58 opp-hz = /bits/ 64 <996000000>;
59 opp-microvolt = <1100000>;
60 clock-latency-ns = <150000>;
61 opp-supported-hw = <0xc>, <0x7>;
66 opp-hz = /bits/ 64 <1200000000>;
67 opp-microvolt = <1225000>;
68 clock-latency-ns = <150000>;
69 opp-supported-hw = <0x8>, <0x3>;
74 usbphynop2: usbphynop2 {
75 compatible = "usb-nop-xceiv";
76 clocks = <&clks IMX7D_USB_PHY2_CLK>;
77 clock-names = "main_clk";
83 compatible = "arm,coresight-etm3x", "arm,primecell";
84 reg = <0x3007d000 0x1000>;
87 * System will hang if added nosmp in kernel command line
88 * without arm,primecell-periphid because amba bus try to
89 * read id and core1 power off at this time.
91 arm,primecell-periphid = <0xbb956>;
93 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
94 clock-names = "apb_pclk";
98 etm1_out_port: endpoint {
99 remote-endpoint = <&ca_funnel_in_port1>;
105 intc: interrupt-controller@31001000 {
106 compatible = "arm,cortex-a7-gic";
107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108 #interrupt-cells = <3>;
109 interrupt-controller;
110 interrupt-parent = <&intc>;
111 reg = <0x31001000 0x1000>,
120 pcie_phy: pcie-phy@306d0000 {
121 compatible = "fsl,imx7d-pcie-phy";
122 reg = <0x306d0000 0x10000>;
128 usbotg2: usb@30b20000 {
129 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
130 reg = <0x30b20000 0x200>;
131 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&clks IMX7D_USB_CTRL_CLK>;
133 fsl,usbphy = <&usbphynop2>;
134 fsl,usbmisc = <&usbmisc2 0>;
135 phy-clkgate-delay-us = <400>;
139 usbmisc2: usbmisc@30b20200 {
141 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
142 reg = <0x30b20200 0x200>;
145 fec2: ethernet@30bf0000 {
146 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
147 reg = <0x30bf0000 0x10000>;
148 interrupt-names = "int0", "int1", "int2", "pps";
149 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
154 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
155 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
156 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
157 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
158 clock-names = "ipg", "ahb", "ptp",
159 "enet_clk_ref", "enet_out";
160 fsl,num-tx-queues = <3>;
161 fsl,num-rx-queues = <3>;
162 fsl,stop-mode = <&gpr 0x10 4>;
166 pcie: pcie@33800000 {
167 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
168 reg = <0x33800000 0x4000>,
169 <0x4ff00000 0x80000>;
170 reg-names = "dbi", "config";
171 #address-cells = <3>;
174 bus-range = <0x00 0xff>;
175 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
176 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
179 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "msi";
181 #interrupt-cells = <1>;
182 interrupt-map-mask = <0 0 0 0x7>;
184 * Reference manual lists pci irqs incorrectly
185 * Real hardware ordering is same as imx6: D+MSI, C, B, A
187 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
188 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
189 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
190 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
192 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
193 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
194 clock-names = "pcie", "pcie_bus", "pcie_phy";
195 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
196 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
197 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
198 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
200 fsl,max-link-speed = <2>;
201 power-domains = <&pgc_pcie_phy>;
202 resets = <&src IMX7_RESET_PCIEPHY>,
203 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
204 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
205 reset-names = "pciephy", "apps", "turnoff";
206 fsl,imx7d-pcie-phy = <&pcie_phy>;
211 &ca_funnel_in_ports {
212 #address-cells = <1>;
217 ca_funnel_in_port1: endpoint {
218 remote-endpoint = <&etm1_out_port>;