arch/arm/boot/dts/imx7d-smegw01.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 //
   3 // Copyright (C) 2020 PHYTEC Messtechnik GmbH
   4 // Author: Jens Lang  <J.Lang@phytec.de>
   5 // Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
   6
   7 /dts-v1/;
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "imx7d.dtsi"
  10
  11 / {
  12         model = "Storopack SMEGW01 board";
  13         compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
  14
  15         aliases {
  16                 mmc0 = &usdhc1;
  17                 mmc1 = &usdhc3;
  18                 mmc2 = &usdhc2;
  19                 rtc0 = &i2c_rtc;
  20                 rtc1 = &snvs_rtc;
  21         };
  22
  23         chosen {
  24                 stdout-path = &uart1;
  25         };
  26
  27         memory@80000000 {
  28                 device_type = "memory";
  29                 reg = <0x80000000 0x20000000>;
  30         };
  31
  32         reg_lte_on: regulator-lte-on {
  33                 compatible = "regulator-fixed";
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&pinctrl_lte_on>;
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 regulator-name = "lte_on";
  39                 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
  40                 enable-active-high;
  41                 regulator-always-on;
  42         };
  43
  44         reg_lte_nreset: regulator-lte-nreset {
  45                 compatible = "regulator-fixed";
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_lte_nreset>;
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50                 regulator-name = "LTE_nReset";
  51                 gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
  52                 enable-active-high;
  53                 regulator-always-on;
  54         };
  55
  56         reg_wifi: regulator-wifi {
  57                 compatible = "regulator-fixed";
  58                 gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
  59                 enable-active-high;
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pinctrl_wifi>;
  62                 regulator-name = "wifi_reg";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65         };
  66
  67         reg_wlan_rfkill: regulator-wlan-rfkill {
  68                 compatible = "regulator-fixed";
  69                 pinctrl-names = "default";
  70                 pinctrl-2 = <&pinctrl_rfkill>;
  71                 regulator-min-microvolt = <3300000>;
  72                 regulator-max-microvolt = <3300000>;
  73                 regulator-name = "wlan_rfkill";
  74                 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
  75                 enable-active-high;
  76                 regulator-always-on;
  77         };
  78
  79         reg_usbotg_vbus: regulator-usbotg-vbus {
  80                 compatible = "regulator-fixed";
  81                 pinctrl-names = "default";
  82                 pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
  83                 regulator-name = "usb_otg_vbus";
  84                 regulator-min-microvolt = <5000000>;
  85                 regulator-max-microvolt = <5000000>;
  86                 gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
  87                 enable-active-high;
  88         };
  89 };
  90
  91 &ecspi1 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_ecspi1>;
  94         cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
  95         status = "okay";
  96
  97         sram@0 {
  98                 compatible = "microchip,48l640";
  99                 reg = <0>;
 100                 spi-max-frequency = <16000000>;
 101         };
 102 };
 103
 104 &fec1 {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_enet1>;
 107         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 108                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 109         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 110         assigned-clock-rates = <0>, <100000000>;
 111         phy-mode = "rgmii-id";
 112         phy-handle = <&ethphy0>;
 113         fsl,magic-packet;
 114         status = "okay";
 115
 116         mdio: mdio {
 117                 #address-cells = <1>;
 118                 #size-cells = <0>;
 119
 120                 ethphy0: ethernet-phy@1 {
 121                         compatible = "ethernet-phy-id0022.1622",
 122                                      "ethernet-phy-ieee802.3-c22";
 123                         reg = <1>;
 124                         reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
 125                 };
 126
 127                 ethphy1: ethernet-phy@2 {
 128                         compatible = "ethernet-phy-id0022.1622",
 129                                      "ethernet-phy-ieee802.3-c22";
 130                         reg = <2>;
 131                 };
 132         };
 133 };
 134
 135 &fec2 {
 136         pinctrl-names = "default";
 137         pinctrl-0 = <&pinctrl_enet2>;
 138         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 139                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 140         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 141         assigned-clock-rates = <0>, <100000000>;
 142         phy-mode = "rgmii-id";
 143         phy-handle = <&ethphy1>;
 144         fsl,magic-packet;
 145         status = "okay";
 146 };
 147
 148 &i2c2 {
 149         pinctrl-names = "default";
 150         pinctrl-0 =<&pinctrl_i2c2>;
 151         clock-frequency = <100000>;
 152         status = "okay";
 153
 154         i2c_rtc: rtc@52 {
 155                 compatible = "microcrystal,rv3028";
 156                 pinctrl-names = "default";
 157                 pinctrl-0 = <&pinctrl_rtc_int>;
 158                 reg = <0x52>;
 159                 interrupt-parent = <&gpio2>;
 160                 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 161         };
 162 };
 163
 164 &flexcan1 {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&pinctrl_flexcan1>;
 167         status = "okay";
 168 };
 169
 170 &flexcan2 {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_flexcan2>;
 173         status = "okay";
 174 };
 175
 176 &uart1 {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_uart1>;
 179         status = "okay";
 180 };
 181
 182 &uart3 {
 183         pinctrl-names = "default";
 184         pinctrl-0 = <&pinctrl_uart3>;
 185         status = "okay";
 186 };
 187
 188 &usbotg1 {
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
 191         dr_mode = "otg";
 192         vbus-supply = <&reg_usbotg_vbus>;
 193         status = "okay";
 194 };
 195
 196 &usbotg2 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_usbotg2>;
 199         over-current-active-low;
 200         dr_mode = "host";
 201         status = "okay";
 202 };
 203
 204 &usdhc1 {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_usdhc1>;
 207         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 208         no-1-8-v;
 209         wakeup-source;
 210         keep-power-in-suspend;
 211         status = "okay";
 212 };
 213
 214 &usdhc2 {
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_usdhc2>;
 217         bus-width = <4>;
 218         no-1-8-v;
 219         non-removable;
 220         vmmc-supply = <&reg_wifi>;
 221         wakeup-source;
 222         status = "okay";
 223 };
 224
 225 &usdhc3 {
 226         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 227         pinctrl-0 = <&pinctrl_usdhc3>;
 228         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 229         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 230         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 231         assigned-clock-rates = <400000000>;
 232         max-frequency = <200000000>;
 233         bus-width = <8>;
 234         fsl,tuning-step = <1>;
 235         non-removable;
 236         cap-mmc-highspeed;
 237         cap-mmc-hw-reset;
 238         mmc-hs200-1_8v;
 239         mmc-ddr-1_8v;
 240         status = "okay";
 241 };
 242
 243 &wdog1 {
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_wdog>;
 246         fsl,ext-reset-output;
 247         status = "okay";
 248 };
 249
 250 &iomuxc {
 251         pinctrl_ecspi1: ecspi1grp {
 252                 fsl,pins = <
 253                         MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
 254                         MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK       0x04
 255                         MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI       0x04
 256                         MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO       0x04
 257                 >;
 258         };
 259
 260         pinctrl_enet1: enet1grp {
 261                 fsl,pins = <
 262                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
 263                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x5
 264                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x5
 265                         MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x5
 266                         MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x5
 267                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x5
 268                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
 269                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x5
 270                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x5
 271                         MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x5
 272                         MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x5
 273                         MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x5
 274                         MX7D_PAD_GPIO1_IO10__ENET1_MDIO         0x7
 275                         MX7D_PAD_GPIO1_IO11__ENET1_MDC          0x7
 276                 >;
 277         };
 278
 279         pinctrl_enet2: enet2grp {
 280                 fsl,pins = <
 281                         MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
 282                         MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC    0x5
 283                         MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0    0x5
 284                         MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1     0x5
 285                         MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2     0x5
 286                         MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3    0x5
 287                         MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0    0x5
 288                         MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1    0x5
 289                         MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2    0x5
 290                         MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3     0x5
 291                         MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
 292                         MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC     0x5
 293                         MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x08
 294                 >;
 295         };
 296
 297         pinctrl_i2c2: i2c2grp {
 298                 fsl,pins = <
 299                         MX7D_PAD_I2C2_SCL__I2C2_SCL             0x40000004
 300                         MX7D_PAD_I2C2_SDA__I2C2_SDA             0x40000004
 301                 >;
 302         };
 303
 304         pinctrl_flexcan1: flexcan1grp {
 305                 fsl,pins = <
 306                         MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX        0x0b0b0
 307                         MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX        0x0b0b0
 308                 >;
 309         };
 310
 311         pinctrl_flexcan2: flexcan2grp {
 312                 fsl,pins = <
 313                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x0b0b0
 314                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x0b0b0
 315                 >;
 316         };
 317
 318         pinctrl_lte_on: lteongrp {
 319                 fsl,pins = <
 320                         MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12       0x17059
 321                 >;
 322         };
 323
 324         pinctrl_lte_nreset: ltenresetgrp {
 325                 fsl,pins = <
 326                         MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21       0x17059
 327                 >;
 328         };
 329
 330         pinctrl_rfkill: rfkillgrp {
 331                 fsl,pins = <
 332                         MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x17059
 333                 >;
 334         };
 335
 336         pinctrl_rtc_int: rtcintgrp {
 337                 fsl,pins = <
 338                         MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x17059
 339                 >;
 340         };
 341
 342         pinctrl_uart1: uart1grp {
 343                 fsl,pins = <
 344                         MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x74
 345                         MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x7c
 346                 >;
 347         };
 348
 349         pinctrl_uart3: uart3grp {
 350                 fsl,pins = <
 351                         MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x7c
 352                         MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x74
 353                 >;
 354         };
 355
 356         pinctrl_usbotg1_lpsr: usbotg1grp {
 357                 fsl,pins = <
 358                         MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC   0x04
 359                 >;
 360         };
 361
 362         pinctrl_usbotg1_pwr: usbotg1-pwrgrp {
 363                 fsl,pins = <
 364                         MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR  0x04
 365                 >;
 366         };
 367
 368         pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpiogrp {
 369                 fsl,pins = <
 370                         MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5     0x04
 371                 >;
 372         };
 373
 374         pinctrl_usbotg2: usbotg2grp {
 375                 fsl,pins = <
 376                         MX7D_PAD_UART3_RTS_B__USB_OTG2_OC       0x5c
 377                 >;
 378         };
 379
 380         pinctrl_usdhc1: usdhc1grp {
 381                 fsl,pins = <
 382                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59
 383                         MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 384                         MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 385                         MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 386                         MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 387                         MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 388                         MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 389                 >;
 390         };
 391
 392         pinctrl_usdhc2: usdhc2grp {
 393                 fsl,pins = <
 394                         MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 395                         MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 396                         MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 397                         MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 398                         MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 399                         MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 400                         MX7D_PAD_SD2_CD_B__SD2_CD_B             0x08
 401                 >;
 402         };
 403
 404         pinctrl_usdhc3: usdhc3grp {
 405                 fsl,pins = <
 406                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5d
 407                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1d
 408                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5d
 409                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5d
 410                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5d
 411                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5d
 412                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5d
 413                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5d
 414                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5d
 415                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5d
 416                         MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
 417                 >;
 418         };
 419
 420         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 421                 fsl,pins = <
 422                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5e
 423                         MX7D_PAD_SD3_CLK__SD3_CLK               0x1e
 424                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5e
 425                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5e
 426                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5e
 427                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5e
 428                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5e
 429                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5e
 430                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5e
 431                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5e
 432                         MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
 433                 >;
 434         };
 435
 436         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 437                 fsl,pins = <
 438                         MX7D_PAD_SD3_CMD__SD3_CMD               0x5f
 439                         MX7D_PAD_SD3_CLK__SD3_CLK               0x0f
 440                         MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5f
 441                         MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5f
 442                         MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5f
 443                         MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5f
 444                         MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5f
 445                         MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5f
 446                         MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5f
 447                         MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5f
 448                         MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
 449                 >;
 450         };
 451
 452         pinctrl_wifi: wifigrp {
 453                 fsl,pins = <
 454                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x04
 455                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x04
 456                 >;
 457         };
 458 };
 459
 460 &iomuxc_lpsr {
 461         pinctrl_wdog: wdoggrp {
 462                 fsl,pins = <
 463                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
 464                 >;
 465         };
 466 };