2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
48 model = "Freescale i.MX7 SabreSD Board";
49 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
52 reg = <0x80000000 0x80000000>;
56 compatible = "spi-gpio";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_spi4>;
59 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
60 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
61 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
62 num-chipselects = <1>;
66 extended_io: gpio-expander@0 {
67 compatible = "fairchild,74hc595";
71 registers-number = <1>;
72 spi-max-frequency = <100000>;
76 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
77 compatible = "regulator-fixed";
78 regulator-name = "usb_otg1_vbus";
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5000000>;
81 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
85 reg_usb_otg2_vbus: regulator-usb-otg1-vbus {
86 compatible = "regulator-fixed";
87 regulator-name = "usb_otg2_vbus";
88 regulator-min-microvolt = <5000000>;
89 regulator-max-microvolt = <5000000>;
90 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
94 reg_can2_3v3: regulator-can2-3v3 {
95 compatible = "regulator-fixed";
96 regulator-name = "can2-3v3";
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
99 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
102 reg_vref_1v8: regulator-vref-1v8 {
103 compatible = "regulator-fixed";
104 regulator-name = "vref-1v8";
105 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <1800000>;
109 reg_brcm: regulator-brcm {
110 compatible = "regulator-fixed";
111 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
113 regulator-name = "brcm_reg";
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_brcm_reg>;
116 regulator-min-microvolt = <3300000>;
117 regulator-max-microvolt = <3300000>;
118 startup-delay-us = <200000>;
123 vref-supply = <®_vref_1v8>;
128 vref-supply = <®_vref_1v8>;
133 arm-supply = <&sw1a_reg>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_ecspi3>;
139 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
143 compatible = "ti,tsc2046";
145 spi-max-frequency = <1000000>;
146 pinctrl-names ="default";
147 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
148 interrupt-parent = <&gpio2>;
150 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
151 ti,x-min = /bits/ 16 <0>;
152 ti,x-max = /bits/ 16 <0>;
153 ti,y-min = /bits/ 16 <0>;
154 ti,y-max = /bits/ 16 <0>;
155 ti,pressure-max = /bits/ 16 <0>;
156 ti,x-plate-ohms = /bits/ 16 <400>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_enet1>;
164 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
165 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
166 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
167 assigned-clock-rates = <0>, <100000000>;
169 phy-handle = <ðphy0>;
174 #address-cells = <1>;
177 ethphy0: ethernet-phy@0 {
181 ethphy1: ethernet-phy@1 {
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_enet2>;
190 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
191 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
192 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
193 assigned-clock-rates = <0>, <100000000>;
195 phy-handle = <ðphy1>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_i2c1>;
206 compatible = "fsl,pfuze3000";
211 regulator-min-microvolt = <700000>;
212 regulator-max-microvolt = <1475000>;
215 regulator-ramp-delay = <6250>;
218 /* use sw1c_reg to align with pfuze100/pfuze200 */
220 regulator-min-microvolt = <700000>;
221 regulator-max-microvolt = <1475000>;
224 regulator-ramp-delay = <6250>;
228 regulator-min-microvolt = <1500000>;
229 regulator-max-microvolt = <1850000>;
235 regulator-min-microvolt = <900000>;
236 regulator-max-microvolt = <1650000>;
242 regulator-min-microvolt = <5000000>;
243 regulator-max-microvolt = <5150000>;
247 regulator-min-microvolt = <1000000>;
248 regulator-max-microvolt = <3000000>;
259 regulator-min-microvolt = <1800000>;
260 regulator-max-microvolt = <3300000>;
265 regulator-min-microvolt = <800000>;
266 regulator-max-microvolt = <1550000>;
270 regulator-min-microvolt = <2850000>;
271 regulator-max-microvolt = <3300000>;
276 regulator-min-microvolt = <2850000>;
277 regulator-max-microvolt = <3300000>;
282 regulator-min-microvolt = <1800000>;
283 regulator-max-microvolt = <3300000>;
288 regulator-min-microvolt = <1800000>;
289 regulator-max-microvolt = <3300000>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&pinctrl_i2c2>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_i2c3>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_i2c4>;
314 compatible = "wlf,wm8960";
316 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
317 clock-names = "mclk";
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_lcdif>;
325 display = <&display0>;
329 bits-per-pixel = <16>;
333 native-mode = <&timing0>;
336 clock-frequency = <9200000>;
348 pixelclk-active = <0>;
355 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_pwm1>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pinctrl_uart1>;
368 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
369 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_uart6>;
376 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
377 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
383 vbus-supply = <®_usb_otg1_vbus>;
388 vbus-supply = <®_usb_otg2_vbus>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_usdhc1>;
396 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
397 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
399 keep-power-in-suspend;
404 pinctrl-names = "default", "state_100mhz", "state_200mhz";
405 pinctrl-0 = <&pinctrl_usdhc2>;
406 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
407 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
409 keep-power-in-suspend;
411 vmmc-supply = <®_brcm>;
412 fsl,tuning-step = <2>;
417 pinctrl-names = "default", "state_100mhz", "state_200mhz";
418 pinctrl-0 = <&pinctrl_usdhc3>;
419 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
420 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
421 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
422 assigned-clock-rates = <400000000>;
424 fsl,tuning-step = <2>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_wdog>;
432 fsl,ext-reset-output;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_hog>;
440 pinctrl_brcm_reg: brcmreggrp {
442 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
446 pinctrl_ecspi3: ecspi3grp {
448 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
449 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
450 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
451 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
455 pinctrl_enet1: enet1grp {
457 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
458 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
459 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
460 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
461 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
462 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
463 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
464 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
465 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
466 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
467 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
468 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
469 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
470 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
474 pinctrl_enet2: enet2grp {
476 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
477 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
478 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
479 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
480 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
481 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
482 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
483 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
484 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
485 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
486 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
487 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
491 pinctrl_hog: hoggrp {
493 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
494 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
498 pinctrl_i2c1: i2c1grp {
500 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
501 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
505 pinctrl_i2c2: i2c2grp {
507 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
508 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
512 pinctrl_i2c3: i2c3grp {
514 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
515 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
519 pinctrl_i2c4: i2c4grp {
521 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
522 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
526 pinctrl_lcdif: lcdifgrp {
528 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
529 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
530 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
531 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
532 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
533 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
534 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
535 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
536 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
537 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
538 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
539 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
540 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
541 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
542 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
543 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
544 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
545 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
546 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
547 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
548 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
549 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
550 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
551 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
552 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
553 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
554 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
555 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
556 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
560 pinctrl_spi4: spi4grp {
562 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
563 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
564 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
568 pinctrl_tsc2046_pendown: tsc2046_pendown {
570 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
574 pinctrl_uart1: uart1grp {
576 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
577 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
581 pinctrl_uart5: uart5grp {
583 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
584 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
585 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
586 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
590 pinctrl_uart6: uart6grp {
592 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
593 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
594 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
595 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
599 pinctrl_usdhc1: usdhc1grp {
601 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
602 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
603 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
604 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
605 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
606 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
607 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
608 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
609 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
613 pinctrl_usdhc2: usdhc2grp {
615 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
616 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
617 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
618 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
619 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
620 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
624 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
626 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
627 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
628 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
629 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
630 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
631 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
635 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
637 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
638 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
639 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
640 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
641 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
642 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
647 pinctrl_usdhc3: usdhc3grp {
649 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
650 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
651 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
652 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
653 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
654 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
655 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
656 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
657 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
658 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
659 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
663 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
665 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
666 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
667 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
668 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
669 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
670 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
671 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
672 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
673 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
674 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
675 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
679 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
681 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
682 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
683 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
684 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
685 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
686 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
687 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
688 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
689 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
690 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
691 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
698 pinctrl_wdog: wdoggrp {
700 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
704 pinctrl_pwm1: pwm1grp {
706 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0