1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
10 model = "Freescale i.MX7 SabreSD Board";
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
18 device_type = "memory";
19 reg = <0x80000000 0x80000000>;
23 compatible = "gpio-keys";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_keys>;
29 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_VOLUMEUP>;
35 label = "Volume Down";
36 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
37 linux,code = <KEY_VOLUMEDOWN>;
43 compatible = "spi-gpio";
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_spi4>;
46 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
47 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
48 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
49 num-chipselects = <1>;
53 extended_io: gpio-expander@0 {
54 compatible = "fairchild,74hc595";
58 registers-number = <1>;
59 spi-max-frequency = <100000>;
63 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
64 compatible = "regulator-fixed";
65 regulator-name = "usb_otg1_vbus";
66 regulator-min-microvolt = <5000000>;
67 regulator-max-microvolt = <5000000>;
68 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
72 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
73 compatible = "regulator-fixed";
74 regulator-name = "usb_otg2_vbus";
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
79 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
83 reg_vref_1v8: regulator-vref-1v8 {
84 compatible = "regulator-fixed";
85 regulator-name = "vref-1v8";
86 regulator-min-microvolt = <1800000>;
87 regulator-max-microvolt = <1800000>;
90 reg_brcm: regulator-brcm {
91 compatible = "regulator-fixed";
92 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
94 regulator-name = "brcm_reg";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_brcm_reg>;
97 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>;
99 startup-delay-us = <200000>;
102 reg_lcd_3v3: regulator-lcd-3v3 {
103 compatible = "regulator-fixed";
104 regulator-name = "lcd-3v3";
105 regulator-min-microvolt = <3300000>;
106 regulator-max-microvolt = <3300000>;
107 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
110 reg_can2_3v3: regulator-can2-3v3 {
111 compatible = "regulator-fixed";
112 regulator-name = "can2-3v3";
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_flexcan2_reg>;
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
120 reg_fec2_3v3: regulator-fec2-3v3 {
121 compatible = "regulator-fixed";
122 regulator-name = "fec2-3v3";
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_enet2_reg>;
125 regulator-min-microvolt = <3300000>;
126 regulator-max-microvolt = <3300000>;
127 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
130 backlight: backlight {
131 compatible = "pwm-backlight";
132 pwms = <&pwm1 0 5000000 0>;
133 brightness-levels = <0 4 8 16 32 64 128 255>;
134 default-brightness-level = <6>;
139 compatible = "innolux,at043tn24";
140 backlight = <&backlight>;
141 power-supply = <®_lcd_3v3>;
145 remote-endpoint = <&display_out>;
151 compatible = "fsl,imx7d-evk-wm8960",
152 "fsl,imx-audio-wm8960";
153 model = "wm8960-audio";
155 audio-codec = <&codec>;
156 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
158 "Headphone Jack", "HP_L",
159 "Headphone Jack", "HP_R",
169 compatible = "fsl,imx-audio-sii902x";
170 model = "sii902x-audio";
177 vref-supply = <®_vref_1v8>;
182 vref-supply = <®_vref_1v8>;
187 cpu-supply = <&sw1a_reg>;
191 cpu-supply = <&sw1a_reg>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_ecspi3>;
197 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
201 compatible = "ti,tsc2046";
203 spi-max-frequency = <1000000>;
204 pinctrl-names ="default";
205 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
206 interrupt-parent = <&gpio2>;
208 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
209 ti,x-min = /bits/ 16 <0>;
210 ti,x-max = /bits/ 16 <0>;
211 ti,y-min = /bits/ 16 <0>;
212 ti,y-max = /bits/ 16 <0>;
213 ti,pressure-max = /bits/ 16 <0>;
214 ti,x-plate-ohms = /bits/ 16 <400>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_enet1>;
222 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
223 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
224 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
225 assigned-clock-rates = <0>, <100000000>;
227 phy-handle = <ðphy0>;
229 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
233 #address-cells = <1>;
236 ethphy0: ethernet-phy@0 {
240 ethphy1: ethernet-phy@1 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_enet2>;
249 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
250 <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
251 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
252 assigned-clock-rates = <0>, <100000000>;
254 phy-handle = <ðphy1>;
255 phy-supply = <®_fec2_3v3>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_flexcan2>;
263 xceiver-supply = <®_can2_3v3>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_i2c1>;
273 compatible = "fsl,pfuze3000";
278 regulator-min-microvolt = <700000>;
279 regulator-max-microvolt = <1475000>;
282 regulator-ramp-delay = <6250>;
285 /* use sw1c_reg to align with pfuze100/pfuze200 */
287 regulator-min-microvolt = <700000>;
288 regulator-max-microvolt = <1475000>;
291 regulator-ramp-delay = <6250>;
295 regulator-min-microvolt = <1800000>;
296 regulator-max-microvolt = <1800000>;
302 regulator-min-microvolt = <900000>;
303 regulator-max-microvolt = <1650000>;
309 regulator-min-microvolt = <5000000>;
310 regulator-max-microvolt = <5150000>;
314 regulator-min-microvolt = <1000000>;
315 regulator-max-microvolt = <3000000>;
326 regulator-min-microvolt = <1800000>;
327 regulator-max-microvolt = <3300000>;
332 regulator-min-microvolt = <800000>;
333 regulator-max-microvolt = <1550000>;
337 regulator-min-microvolt = <2850000>;
338 regulator-max-microvolt = <3300000>;
343 regulator-min-microvolt = <2850000>;
344 regulator-max-microvolt = <3300000>;
349 regulator-min-microvolt = <1800000>;
350 regulator-max-microvolt = <3300000>;
355 regulator-min-microvolt = <2800000>;
356 regulator-max-microvolt = <2800000>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_i2c2>;
369 compatible = "fsl,mpl3115";
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_i2c3>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_i2c4>;
386 compatible = "wlf,wm8960";
388 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
389 clock-names = "mclk";
391 wlf,hp-cfg = <2 2 3>;
392 wlf,gpio-cfg = <1 3>;
393 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
394 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
395 <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
396 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
397 assigned-clock-rates = <0>, <884736000>, <12288000>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_lcdif>;
407 display_out: endpoint {
408 remote-endpoint = <&panel_in>;
414 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
419 vin-supply = <&sw2_reg>;
423 vin-supply = <&sw2_reg>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_sai1>;
429 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
430 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
431 <&clks IMX7D_SAI1_ROOT_CLK>;
432 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
433 assigned-clock-rates = <0>, <884736000>, <36864000>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
440 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
441 <&clks IMX7D_PLL_AUDIO_POST_DIV>,
442 <&clks IMX7D_SAI3_ROOT_CLK>;
443 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
444 assigned-clock-rates = <0>, <884736000>, <36864000>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_uart1>;
455 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
456 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&pinctrl_uart6>;
463 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
464 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
470 vbus-supply = <®_usb_otg1_vbus>;
475 vbus-supply = <®_usb_otg2_vbus>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&pinctrl_usdhc1>;
483 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
484 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
486 keep-power-in-suspend;
491 pinctrl-names = "default", "state_100mhz", "state_200mhz";
492 pinctrl-0 = <&pinctrl_usdhc2>;
493 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
494 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
496 keep-power-in-suspend;
498 vmmc-supply = <®_brcm>;
499 fsl,tuning-step = <2>;
504 pinctrl-names = "default", "state_100mhz", "state_200mhz";
505 pinctrl-0 = <&pinctrl_usdhc3>;
506 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
507 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
508 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
509 assigned-clock-rates = <400000000>;
511 fsl,tuning-step = <2>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_wdog>;
519 fsl,ext-reset-output;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_hog>;
527 pinctrl_brcm_reg: brcmreggrp {
529 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
533 pinctrl_ecspi3: ecspi3grp {
535 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
536 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
537 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
538 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
542 pinctrl_enet1: enet1grp {
544 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
545 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
546 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
547 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
548 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
549 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
550 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
551 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
552 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
553 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
554 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
555 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
556 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
557 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
561 pinctrl_enet2: enet2grp {
563 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
564 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
565 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
566 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
567 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
568 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
569 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
570 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
571 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
572 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
573 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
574 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
578 pinctrl_enet2_reg: enet2reggrp {
580 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14
584 pinctrl_flexcan2: flexcan2grp {
586 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
587 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
591 pinctrl_flexcan2_reg: flexcan2reggrp {
593 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
597 pinctrl_gpio_keys: gpio_keysgrp {
599 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
600 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
604 pinctrl_hog: hoggrp {
606 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
607 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */
611 pinctrl_i2c1: i2c1grp {
613 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
614 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
618 pinctrl_i2c2: i2c2grp {
620 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
621 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
625 pinctrl_i2c3: i2c3grp {
627 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
628 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
632 pinctrl_i2c4: i2c4grp {
634 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
635 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
639 pinctrl_lcdif: lcdifgrp {
641 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
642 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
643 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
644 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
645 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
646 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
647 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
648 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
649 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
650 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
651 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
652 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
653 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
654 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
655 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
656 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
657 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
658 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
659 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
660 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
661 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
662 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
663 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
664 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
665 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
666 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
667 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
668 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
669 MX7D_PAD_LCD_RESET__LCD_RESET 0x79
673 pinctrl_sai1: sai1grp {
675 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
676 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
677 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
678 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
679 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
683 pinctrl_sai2: sai2grp {
685 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
686 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
687 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
688 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f
692 pinctrl_sai3: sai3grp {
694 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
695 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
696 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
700 pinctrl_spi4: spi4grp {
702 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
703 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
704 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
708 pinctrl_tsc2046_pendown: tsc2046_pendown {
710 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
714 pinctrl_uart1: uart1grp {
716 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
717 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
721 pinctrl_uart5: uart5grp {
723 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
724 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
725 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
726 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
730 pinctrl_uart6: uart6grp {
732 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
733 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
734 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
735 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
739 pinctrl_usdhc1: usdhc1grp {
741 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
742 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
743 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
744 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
745 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
746 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
747 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
748 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
749 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
753 pinctrl_usdhc2: usdhc2grp {
755 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
756 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
757 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
758 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
759 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
760 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
764 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
766 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
767 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
768 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
769 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
770 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
771 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
775 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
777 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
778 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
779 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
780 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
781 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
782 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
787 pinctrl_usdhc3: usdhc3grp {
789 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
790 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
791 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
792 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
793 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
794 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
795 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
796 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
797 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
798 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
799 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
803 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
805 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
806 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
807 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
808 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
809 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
810 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
811 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
812 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
813 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
814 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
815 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
819 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
821 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
822 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
823 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
824 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
825 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
826 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
827 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
828 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
829 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
830 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
831 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
838 pinctrl-names = "default";
839 pinctrl-0 = <&pinctrl_pwm1>;
844 pinctrl_wdog: wdoggrp {
846 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
850 pinctrl_pwm1: pwm1grp {
852 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
856 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
858 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
862 pinctrl_sai3_mclk: sai3grp_mclk {
864 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f