2 * Copyright 2016 Toradex AG
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 compatible = "pwm-backlight";
46 pinctrl-names = "default";
47 pinctrl-0 = <&pinctrl_gpio_bl_on>;
48 pwms = <&pwm1 0 5000000 0>;
49 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
52 reg_module_3v3: regulator-module-3v3 {
53 compatible = "regulator-fixed";
54 regulator-name = "+V3.3";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
59 reg_module_3v3_avdd: regulator-module-3v3-avdd {
60 compatible = "regulator-fixed";
61 regulator-name = "+V3.3_AVDD_AUDIO";
62 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <3300000>;
67 compatible = "simple-audio-card";
68 simple-audio-card,name = "imx7-sgtl5000";
69 simple-audio-card,format = "i2s";
70 simple-audio-card,bitclock-master = <&dailink_master>;
71 simple-audio-card,frame-master = <&dailink_master>;
72 simple-audio-card,cpu {
76 dailink_master: simple-audio-card,codec {
78 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
84 vref-supply = <®_DCDC3>;
88 vref-supply = <®_DCDC3>;
92 cpu-supply = <®_DCDC2>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
98 cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_enet1>;
104 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
105 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
106 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
107 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
108 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
109 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
110 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
111 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
112 assigned-clock-rates = <0>, <100000000>;
114 phy-supply = <®_LDO1>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_gpmi_nand>;
123 nand-ecc-mode = "hw";
127 clock-frequency = <100000>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
133 compatible = "fsl,sgtl5000";
134 #sound-dai-cells = <0>;
136 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_sai1_mclk>;
139 VDDA-supply = <®_module_3v3_avdd>;
140 VDDIO-supply = <®_module_3v3>;
141 VDDD-supply = <®_DCDC3>;
145 compatible = "adi,ad7879-1";
147 interrupt-parent = <&gpio1>;
148 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
149 touchscreen-max-pressure = <4096>;
150 adi,resistance-plate-x = <120>;
151 adi,first-conversion-delay = /bits/ 8 <3>;
152 adi,acquisition-time = /bits/ 8 <1>;
153 adi,median-filter-size = /bits/ 8 <2>;
154 adi,averaging = /bits/ 8 <1>;
155 adi,conversion-interval = /bits/ 8 <255>;
159 compatible = "ricoh,rn5t567";
163 reg_DCDC1: DCDC1 { /* V1.0_SOC */
164 regulator-min-microvolt = <1000000>;
165 regulator-max-microvolt = <1100000>;
170 reg_DCDC2: DCDC2 { /* V1.1_ARM */
171 regulator-min-microvolt = <975000>;
172 regulator-max-microvolt = <1100000>;
177 reg_DCDC3: DCDC3 { /* V1.8 */
178 regulator-min-microvolt = <1800000>;
179 regulator-max-microvolt = <1800000>;
184 reg_DCDC4: DCDC4 { /* V1.35_DRAM */
185 regulator-min-microvolt = <1350000>;
186 regulator-max-microvolt = <1350000>;
191 reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
192 regulator-min-microvolt = <1800000>;
193 regulator-max-microvolt = <3300000>;
197 reg_LDO2: LDO2 { /* +V1.8_SD */
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <3300000>;
204 reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
205 regulator-min-microvolt = <3300000>;
206 regulator-max-microvolt = <3300000>;
211 reg_LDO4: LDO4 { /* V1.8_LPSR */
212 regulator-min-microvolt = <1800000>;
213 regulator-max-microvolt = <1800000>;
218 reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
219 regulator-min-microvolt = <3300000>;
220 regulator-max-microvolt = <3300000>;
229 clock-frequency = <100000>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_i2c4>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_lcdif_dat
237 &pinctrl_lcdif_ctrl>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pwm1>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_pwm2>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_pwm3>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_pwm4>;
261 vin-supply = <®_DCDC3>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_sai1>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
273 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
274 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_uart2>;
282 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
283 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart3>;
291 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
292 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
304 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
306 vqmmc-supply = <®_LDO2>;
310 pinctrl-names = "default", "state_100mhz", "state_200mhz";
311 pinctrl-0 = <&pinctrl_usdhc3>;
312 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
313 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
314 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
315 assigned-clock-rates = <400000000>;
317 fsl,tuning-step = <2>;
318 max-frequency = <100000000>;
319 vmmc-supply = <®_module_3v3>;
320 vqmmc-supply = <®_DCDC3>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
328 pinctrl_gpio1: gpio1-grp {
330 MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
331 MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 63 */
332 MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
333 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
334 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
335 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
336 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
337 MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
338 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
339 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */
340 MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
341 MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
342 MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
343 MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14 /* SODIMM 117 */
344 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* SODIMM 119 */
345 MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14 /* SODIMM 121 */
346 MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14 /* SODIMM 123 */
347 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14 /* SODIMM 125 */
348 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
349 MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
350 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
351 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
352 MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
353 MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
354 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
355 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
356 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */
357 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
358 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
359 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
360 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x14 /* SODIMM 116 */
361 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x14 /* SODIMM 118 */
362 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x14 /* SODIMM 120 */
363 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x14 /* SODIMM 122 */
364 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x14 /* SODIMM 124 */
365 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x14 /* SODIMM 126 */
366 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* SODIMM 128 */
367 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x14 /* SODIMM 130 */
368 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x14 /* SODIMM 132 */
369 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x14 /* SODIMM 134 */
370 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14 /* SODIMM 150 */
371 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x14 /* SODIMM 152 */
372 MX7D_PAD_SD2_CLK__GPIO5_IO12 0x14 /* SODIMM 184 */
373 MX7D_PAD_SD2_CMD__GPIO5_IO13 0x14 /* SODIMM 186 */
377 pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
379 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
380 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
381 MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
382 MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
383 MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
384 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x14 /* SODIMM 85 */
385 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x14 /* SODIMM 97 */
386 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x14 /* SODIMM 101 */
387 MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 /* SODIMM 103 */
388 MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x14 /* SODIMM 94 */
389 MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x14 /* SODIMM 96 */
390 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* SODIMM 98 */
394 pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
396 MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x14 /* SODIMM 136 */
397 MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
398 MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
399 MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
400 MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
401 MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
405 pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
407 MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 /* SODIMM 178 */
408 MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 /* SODIMM 188 */
412 pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
414 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
418 pinctrl_can_int: can-int-grp {
420 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
424 pinctrl_enet1: enet1grp {
426 MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
427 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
428 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
429 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
430 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
432 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
433 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
434 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
435 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x73
436 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
437 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
441 pinctrl_ecspi3_cs: ecspi3-cs-grp {
443 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
447 pinctrl_ecspi3: ecspi3-grp {
449 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
450 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
451 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
455 pinctrl_flexcan2: flexcan2-grp {
457 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
458 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
462 pinctrl_gpio_bl_on: gpio-bl-on {
464 MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
468 pinctrl_gpmi_nand: gpmi-nand-grp {
470 MX7D_PAD_SD3_CLK__NAND_CLE 0x71
471 MX7D_PAD_SD3_CMD__NAND_ALE 0x71
472 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
473 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
474 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
475 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
476 MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71
477 MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71
478 MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71
479 MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71
480 MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71
481 MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71
482 MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71
483 MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71
487 pinctrl_i2c4: i2c4-grp {
489 MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
490 MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
494 pinctrl_lcdif_dat: lcdif-dat-grp {
496 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
497 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
498 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
499 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
500 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
501 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
502 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
503 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
504 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
505 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
506 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
507 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
508 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
509 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
510 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
511 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
512 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
513 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
517 pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
519 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
520 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
521 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
522 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
523 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
524 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
528 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
530 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
531 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
532 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
533 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
537 pinctrl_pwm1: pwm1-grp {
539 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79
540 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4
544 pinctrl_pwm2: pwm2-grp {
546 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x79
550 pinctrl_pwm3: pwm3-grp {
552 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x79
556 pinctrl_pwm4: pwm4-grp {
558 MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79
559 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4
563 pinctrl_uart1: uart1-grp {
565 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79
566 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79
567 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79
568 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79
572 pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
574 MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */
575 MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */
579 pinctrl_uart2: uart2-grp {
581 MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
582 MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
583 MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
584 MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
587 pinctrl_uart3: uart3-grp {
589 MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
590 MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
594 pinctrl_usbh_reg: gpio-usbh-vbus {
596 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
600 pinctrl_usdhc1: usdhc1-grp {
602 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
603 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
604 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
605 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
606 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
607 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
611 pinctrl_usdhc3: usdhc3grp {
613 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
614 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
615 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
616 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
617 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
618 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
619 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
620 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
621 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
622 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
623 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
627 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
629 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
630 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
631 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
632 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
633 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
634 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
635 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
636 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
637 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
638 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
639 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
643 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
645 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
646 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
647 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
648 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
649 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
650 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
651 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
652 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
653 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
654 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
655 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
659 pinctrl_sai1: sai1-grp {
661 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
662 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
663 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
664 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
668 pinctrl_sai1_mclk: sai1grp_mclk {
670 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
676 pinctrl-names = "default";
677 pinctrl-0 = <&pinctrl_gpio_lpsr>;
679 pinctrl_gpio_lpsr: gpio1-grp {
681 MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59
682 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59
683 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59
687 pinctrl_i2c1: i2c1-grp {
689 MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f
690 MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f
694 pinctrl_cd_usdhc1: usdhc1-cd-grp {
696 MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */
700 pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
702 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 /* DSR */
703 MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x14 /* RI */