arch/arm/boot/dts/imx6ull-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * Copyright 2018-2021 Toradex
   4  */
   5
   6 #include "imx6ull.dtsi"
   7
   8 / {
   9         aliases {
  10                 ethernet0 = &fec2;
  11                 ethernet1 = &fec1;
  12         };
  13
  14         bl: backlight {
  15                 compatible = "pwm-backlight";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  18                 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
  19                 status = "disabled";
  20         };
  21
  22         reg_module_3v3: regulator-module-3v3 {
  23                 compatible = "regulator-fixed";
  24                 regulator-always-on;
  25                 regulator-name = "+V3.3";
  26                 regulator-min-microvolt = <3300000>;
  27                 regulator-max-microvolt = <3300000>;
  28         };
  29
  30         reg_module_3v3_avdd: regulator-module-3v3-avdd {
  31                 compatible = "regulator-fixed";
  32                 regulator-always-on;
  33                 regulator-name = "+V3.3_AVDD_AUDIO";
  34                 regulator-min-microvolt = <3300000>;
  35                 regulator-max-microvolt = <3300000>;
  36         };
  37
  38         reg_sd1_vmmc: regulator-sd1-vmmc {
  39                 compatible = "regulator-gpio";
  40                 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
  43                 regulator-always-on;
  44                 regulator-name = "+V3.3_1.8_SD";
  45                 regulator-min-microvolt = <1800000>;
  46                 regulator-max-microvolt = <3300000>;
  47                 states = <1800000 0x1 3300000 0x0>;
  48                 vin-supply = <&reg_module_3v3>;
  49         };
  50 };
  51
  52 &adc1 {
  53         num-channels = <10>;
  54         vref-supply = <&reg_module_3v3_avdd>;
  55 };
  56
  57 &can1 {
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_flexcan1>;
  60         status = "disabled";
  61 };
  62
  63 &can2 {
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_flexcan2>;
  66         status = "disabled";
  67 };
  68
  69 /* Colibri SPI */
  70 &ecspi1 {
  71         cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
  74 };
  75
  76 &fec2 {
  77         pinctrl-names = "default", "sleep";
  78         pinctrl-0 = <&pinctrl_enet2>;
  79         pinctrl-1 = <&pinctrl_enet2_sleep>;
  80         phy-mode = "rmii";
  81         phy-handle = <&ethphy1>;
  82         status = "okay";
  83
  84         mdio {
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87
  88                 ethphy1: ethernet-phy@2 {
  89                         compatible = "ethernet-phy-ieee802.3-c22";
  90                         max-speed = <100>;
  91                         reg = <2>;
  92                 };
  93         };
  94 };
  95
  96 &gpmi {
  97         pinctrl-names = "default";
  98         pinctrl-0 = <&pinctrl_gpmi_nand>;
  99         nand-on-flash-bbt;
 100         nand-ecc-mode = "hw";
 101         nand-ecc-strength = <8>;
 102         nand-ecc-step-size = <512>;
 103         status = "okay";
 104 };
 105
 106 &i2c1 {
 107         pinctrl-names = "default", "gpio";
 108         pinctrl-0 = <&pinctrl_i2c1>;
 109         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 110         sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 111         scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 112 };
 113
 114 &i2c2 {
 115         pinctrl-names = "default", "gpio";
 116         pinctrl-0 = <&pinctrl_i2c2>;
 117         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 118         sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 119         scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 120         status = "okay";
 121
 122         ad7879@2c {
 123                 compatible = "adi,ad7879-1";
 124                 pinctrl-names = "default";
 125                 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
 126                 reg = <0x2c>;
 127                 interrupt-parent = <&gpio5>;
 128                 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
 129                 touchscreen-max-pressure = <4096>;
 130                 adi,resistance-plate-x = <120>;
 131                 adi,first-conversion-delay = /bits/ 8 <3>;
 132                 adi,acquisition-time = /bits/ 8 <1>;
 133                 adi,median-filter-size = /bits/ 8 <2>;
 134                 adi,averaging = /bits/ 8 <1>;
 135                 adi,conversion-interval = /bits/ 8 <255>;
 136         };
 137 };
 138
 139 &lcdif {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_lcdif_dat
 142                      &pinctrl_lcdif_ctrl>;
 143 };
 144
 145 &pwm4 {
 146         pinctrl-names = "default";
 147         pinctrl-0 = <&pinctrl_pwm4>;
 148 };
 149
 150 &pwm5 {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_pwm5>;
 153 };
 154
 155 &pwm6 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_pwm6>;
 158 };
 159
 160 &pwm7 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_pwm7>;
 163 };
 164
 165 &sdma {
 166         status = "okay";
 167 };
 168
 169 &snvs_pwrkey {
 170         status = "disabled";
 171 };
 172
 173 &uart1 {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
 176         uart-has-rtscts;
 177         fsl,dte-mode;
 178 };
 179
 180 &uart2 {
 181         pinctrl-names = "default";
 182         pinctrl-0 = <&pinctrl_uart2>;
 183         uart-has-rtscts;
 184         fsl,dte-mode;
 185 };
 186
 187 &uart5 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_uart5>;
 190         fsl,dte-mode;
 191 };
 192
 193 &usbotg1 {
 194         dr_mode = "otg";
 195         srp-disable;
 196         hnp-disable;
 197         adp-disable;
 198 };
 199
 200 &usbotg2 {
 201         dr_mode = "host";
 202 };
 203
 204 &usdhc1 {
 205         assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
 206         assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
 207         assigned-clock-rates = <0>, <198000000>;
 208 };
 209
 210 &wdog1 {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_wdog>;
 213         fsl,ext-reset-output;
 214 };
 215
 216 &iomuxc {
 217         pinctrl_can_int: canint-grp {
 218                 fsl,pins = <
 219                         MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04    0x13010 /* SODIMM 73 */
 220                 >;
 221         };
 222
 223         pinctrl_enet2: enet2-grp {
 224                 fsl,pins = <
 225                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 226                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 227                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 228                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 229                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 230                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 231                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 232                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 233                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 234                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 235                 >;
 236         };
 237
 238         pinctrl_enet2_sleep: enet2sleepgrp {
 239                 fsl,pins = <
 240                         MX6UL_PAD_GPIO1_IO06__GPIO1_IO06        0x0
 241                         MX6UL_PAD_GPIO1_IO07__GPIO1_IO07        0x0
 242                         MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08    0x0
 243                         MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09    0x0
 244                         MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10       0x0
 245                         MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15       0x0
 246                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 247                         MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11    0x0
 248                         MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12    0x0
 249                         MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13       0x0
 250                 >;
 251         };
 252
 253         pinctrl_ecspi1_cs: ecspi1-cs-grp {
 254                 fsl,pins = <
 255                         MX6UL_PAD_LCD_DATA21__GPIO3_IO26        0x70a0  /* SODIMM 86 */
 256                 >;
 257         };
 258
 259         pinctrl_ecspi1: ecspi1-grp {
 260                 fsl,pins = <
 261                         MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x000a0 /* SODIMM 88 */
 262                         MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI       0x000a0 /* SODIMM 92 */
 263                         MX6UL_PAD_LCD_DATA23__ECSPI1_MISO       0x100a0 /* SODIMM 90 */
 264                 >;
 265         };
 266
 267         pinctrl_flexcan1: flexcan1-grp {
 268                 fsl,pins = <
 269                         MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX   0x1b020
 270                         MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX   0x1b020
 271                 >;
 272         };
 273
 274         pinctrl_flexcan2: flexcan2-grp {
 275                 fsl,pins = <
 276                         MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
 277                         MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
 278                 >;
 279         };
 280
 281         pinctrl_gpio_bl_on: gpio-bl-on-grp {
 282                 fsl,pins = <
 283                         MX6UL_PAD_JTAG_TMS__GPIO1_IO11          0x30a0  /* SODIMM 71 */
 284                 >;
 285         };
 286
 287         pinctrl_gpio1: gpio1-grp {
 288                 fsl,pins = <
 289                         MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25     0x10b0 /* SODIMM 77 */
 290                         MX6UL_PAD_JTAG_TCK__GPIO1_IO14          0x70a0 /* SODIMM 99 */
 291                         MX6UL_PAD_NAND_CE1_B__GPIO4_IO14        0x10b0 /* SODIMM 133 */
 292                         MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24     0x10b0 /* SODIMM 135 */
 293                         MX6UL_PAD_UART3_CTS_B__GPIO1_IO26       0x10b0 /* SODIMM 100 */
 294                         MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15       0x70a0 /* SODIMM 102 */
 295                         MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07       0x10b0 /* SODIMM 104 */
 296                         MX6UL_PAD_UART3_RTS_B__GPIO1_IO27       0x10b0 /* SODIMM 186 */
 297                 >;
 298         };
 299
 300         pinctrl_gpio2: gpio2-grp { /* Camera */
 301                 fsl,pins = <
 302                         MX6UL_PAD_CSI_DATA04__GPIO4_IO25        0x10b0 /* SODIMM 69 */
 303                         MX6UL_PAD_CSI_MCLK__GPIO4_IO17          0x10b0 /* SODIMM 75 */
 304                         MX6UL_PAD_CSI_DATA06__GPIO4_IO27        0x10b0 /* SODIMM 85 */
 305                         MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18        0x10b0 /* SODIMM 96 */
 306                         MX6UL_PAD_CSI_DATA05__GPIO4_IO26        0x10b0 /* SODIMM 98 */
 307                 >;
 308         };
 309
 310         pinctrl_gpio3: gpio3-grp { /* CAN2 */
 311                 fsl,pins = <
 312                         MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02       0x10b0 /* SODIMM 178 */
 313                         MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03    0x10b0 /* SODIMM 188 */
 314                 >;
 315         };
 316
 317         pinctrl_gpio4: gpio4-grp {
 318                 fsl,pins = <
 319                         MX6UL_PAD_CSI_DATA07__GPIO4_IO28        0x10b0 /* SODIMM 65 */
 320                 >;
 321         };
 322
 323         pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
 324                 fsl,pins = <
 325                         MX6UL_PAD_JTAG_MOD__GPIO1_IO10          0xb0a0 /* SODIMM 106 */
 326                 >;
 327         };
 328
 329         pinctrl_gpio6: gpio6-grp { /* Wifi pins */
 330                 fsl,pins = <
 331                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03        0x10b0 /* SODIMM 89 */
 332                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23        0x10b0 /* SODIMM 79 */
 333                         MX6UL_PAD_CSI_VSYNC__GPIO4_IO19         0x10b0 /* SODIMM 81 */
 334                         MX6UL_PAD_CSI_DATA03__GPIO4_IO24        0x10b0 /* SODIMM 97 */
 335                         MX6UL_PAD_CSI_DATA00__GPIO4_IO21        0x10b0 /* SODIMM 101 */
 336                         MX6UL_PAD_CSI_DATA01__GPIO4_IO22        0x10b0 /* SODIMM 103 */
 337                         MX6UL_PAD_CSI_HSYNC__GPIO4_IO20         0x10b0 /* SODIMM 94 */
 338                 >;
 339         };
 340
 341         pinctrl_gpio7: gpio7-grp { /* CAN1 */
 342                 fsl,pins = <
 343                         MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00    0xb0b0/* SODIMM 55 */
 344                         MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01    0xb0b0 /* SODIMM 63 */
 345                 >;
 346         };
 347
 348         /*
 349          * With an eMMC instead of a raw NAND device the following pins
 350          * are available at SODIMM pins
 351          */
 352         pinctrl_gpmi_gpio: gpmi-gpio-grp {
 353                 fsl,pins = <
 354                         MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x10b0 /* SODIMM 140 */
 355                         MX6UL_PAD_NAND_CE0_B__GPIO4_IO13        0x10b0 /* SODIMM 144 */
 356                         MX6UL_PAD_NAND_CLE__GPIO4_IO15          0x10b0 /* SODIMM 146 */
 357                         MX6UL_PAD_NAND_READY_B__GPIO4_IO12      0x10b0 /* SODIMM 142 */
 358                 >;
 359         };
 360
 361         pinctrl_gpmi_nand: gpmi-nand-grp {
 362                 fsl,pins = <
 363                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x100a9
 364                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x100a9
 365                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x100a9
 366                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x100a9
 367                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x100a9
 368                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x100a9
 369                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x100a9
 370                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x100a9
 371                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x100a9
 372                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x100a9
 373                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x100a9
 374                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x100a9
 375                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x100a9
 376                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
 377                 >;
 378         };
 379
 380         pinctrl_i2c1: i2c1-grp {
 381                 fsl,pins = <
 382                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0    /* SODIMM 196 */
 383                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0    /* SODIMM 194 */
 384                 >;
 385         };
 386
 387         pinctrl_i2c1_gpio: i2c1-gpio-grp {
 388                 fsl,pins = <
 389                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0  /* SODIMM 196 */
 390                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0  /* SODIMM 194 */
 391                 >;
 392         };
 393
 394         pinctrl_i2c2: i2c2-grp {
 395                 fsl,pins = <
 396                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 397                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 398                 >;
 399         };
 400
 401         pinctrl_i2c2_gpio: i2c2-gpio-grp {
 402                 fsl,pins = <
 403                         MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
 404                         MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
 405                 >;
 406         };
 407
 408         pinctrl_lcdif_dat: lcdif-dat-grp {
 409                 fsl,pins = <
 410                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079      /* SODIMM 76 */
 411                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079      /* SODIMM 70 */
 412                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079      /* SODIMM 60 */
 413                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079      /* SODIMM 58 */
 414                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079      /* SODIMM 78 */
 415                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079      /* SODIMM 72 */
 416                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079      /* SODIMM 80 */
 417                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079      /* SODIMM 46 */
 418                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079      /* SODIMM 62 */
 419                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079      /* SODIMM 48 */
 420                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079      /* SODIMM 74 */
 421                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079      /* SODIMM 50 */
 422                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079      /* SODIMM 52 */
 423                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079      /* SODIMM 54 */
 424                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079      /* SODIMM 66 */
 425                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079      /* SODIMM 64 */
 426                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079      /* SODIMM 57 */
 427                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079      /* SODIMM 61 */
 428                 >;
 429         };
 430
 431         pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
 432                 fsl,pins = <
 433                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x00079     /* SODIMM 56 */
 434                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x00079     /* SODIMM 44 */
 435                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x00079     /* SODIMM 68 */
 436                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x00079     /* SODIMM 82 */
 437                 >;
 438         };
 439
 440         pinctrl_pwm4: pwm4-grp {
 441                 fsl,pins = <
 442                         MX6UL_PAD_NAND_WP_B__PWM4_OUT   0x00079         /* SODIMM 59 */
 443                 >;
 444         };
 445
 446         pinctrl_pwm5: pwm5-grp {
 447                 fsl,pins = <
 448                         MX6UL_PAD_NAND_DQS__PWM5_OUT    0x00079         /* SODIMM 28 */
 449                 >;
 450         };
 451
 452         pinctrl_pwm6: pwm6-grp {
 453                 fsl,pins = <
 454                         MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079         /* SODIMM 30 */
 455                 >;
 456         };
 457
 458         pinctrl_pwm7: pwm7-grp {
 459                 fsl,pins = <
 460                         MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x00079 /* SODIMM 67 */
 461                 >;
 462         };
 463
 464         pinctrl_uart1: uart1-grp {
 465                 fsl,pins = <
 466                         MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX   0x1b0b1 /* SODIMM 33 */
 467                         MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX   0x1b0b1 /* SODIMM 35 */
 468                         MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS    0x1b0b1 /* SODIMM 27 */
 469                         MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS    0x1b0b1 /* SODIMM 25 */
 470                 >;
 471         };
 472
 473         pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
 474                 fsl,pins = <
 475                         MX6UL_PAD_JTAG_TDI__GPIO1_IO13          0x70a0 /* SODIMM 31 */
 476                         MX6UL_PAD_LCD_DATA18__GPIO3_IO23        0x10b0 /* SODIMM 29 */
 477                         MX6UL_PAD_JTAG_TDO__GPIO1_IO12          0x90b1 /* SODIMM 23 */
 478                         MX6UL_PAD_LCD_DATA19__GPIO3_IO24        0x10b0 /* SODIMM 37 */
 479                 >;
 480         };
 481
 482         pinctrl_uart2: uart2-grp {
 483                 fsl,pins = <
 484                         MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX   0x1b0b1 /* SODIMM 36 */
 485                         MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX   0x1b0b1 /* SODIMM 38 */
 486                         MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS    0x1b0b1 /* SODIMM 32 */
 487                         MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS    0x1b0b1 /* SODIMM 34 */
 488                 >;
 489         };
 490         pinctrl_uart5: uart5-grp {
 491                 fsl,pins = <
 492                         MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX      0x1b0b1 /* SODIMM 19 */
 493                         MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX      0x1b0b1 /* SODIMM 21 */
 494                 >;
 495         };
 496
 497         pinctrl_usbh_reg: gpio-usbh-reg {
 498                 fsl,pins = <
 499                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x10b0 /* SODIMM 129 */
 500                 >;
 501         };
 502
 503         pinctrl_usdhc1: usdhc1-grp {
 504                 fsl,pins = <
 505                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x17059 /* SODIMM 47 */
 506                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x10059 /* SODIMM 190 */
 507                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059 /* SODIMM 192 */
 508                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059 /* SODIMM 49 */
 509                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059 /* SODIMM 51 */
 510                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059 /* SODIMM 53 */
 511                 >;
 512         };
 513
 514         pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
 515                 fsl,pins = <
 516                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170b9
 517                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100b9
 518                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
 519                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
 520                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
 521                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
 522                 >;
 523         };
 524
 525         pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
 526                 fsl,pins = <
 527                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x170f9
 528                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x100f9
 529                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
 530                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
 531                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
 532                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
 533                 >;
 534         };
 535
 536         pinctrl_usdhc2: usdhc2-grp {
 537                 fsl,pins = <
 538                         MX6UL_PAD_CSI_DATA00__USDHC2_DATA0      0x17069
 539                         MX6UL_PAD_CSI_DATA01__USDHC2_DATA1      0x17069
 540                         MX6UL_PAD_CSI_DATA02__USDHC2_DATA2      0x17069
 541                         MX6UL_PAD_CSI_DATA03__USDHC2_DATA3      0x17069
 542                         MX6UL_PAD_CSI_HSYNC__USDHC2_CMD         0x17069
 543                         MX6UL_PAD_CSI_VSYNC__USDHC2_CLK         0x17069
 544
 545                         MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT    0x10
 546                 >;
 547         };
 548
 549         pinctrl_usdhc2emmc: usdhc2emmcgrp {
 550                 fsl,pins = <
 551                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
 552                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 553                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 554                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 555                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 556                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 557                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
 558                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
 559                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
 560                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
 561                 >;
 562         };
 563
 564         pinctrl_wdog: wdog-grp {
 565                 fsl,pins = <
 566                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 567                 >;
 568         };
 569 };
 570
 571 &iomuxc_snvs {
 572         pinctrl_snvs_gpio1: snvs-gpio1-grp {
 573                 fsl,pins = <
 574                         MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06     0x110a0 /* SODIMM 93 */
 575                         MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03     0x110a0 /* SODIMM 95 */
 576                         MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10       0x1b0a0 /* SODIMM 105 */
 577                         MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05     0x0b0a0 /* SODIMM 131 */
 578                         MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08     0x110a0 /* SODIMM 138 */
 579                 >;
 580         };
 581
 582         pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
 583                 fsl,pins = <
 584                         MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04     0xb0a0  /* SODIMM 107 */
 585                 >;
 586         };
 587
 588         pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
 589                 fsl,pins = <
 590                         MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x130a0 /* SODIMM 127 */
 591                 >;
 592         };
 593
 594         pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
 595                 fsl,pins = <
 596                         MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07     0x100b0
 597                 >;
 598         };
 599
 600         pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
 601                 fsl,pins = <
 602                         MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09     0x400100b0
 603                 >;
 604         };
 605
 606         pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
 607                 fsl,pins = <
 608                         MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02     0x130b0
 609                 >;
 610         };
 611
 612         pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
 613                 fsl,pins = <
 614                         MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01     0x130a0 /* SODIMM 45 */
 615                 >;
 616         };
 617
 618         pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
 619                 fsl,pins = <
 620                         MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x1b0a0 /* SODIMM 43 */
 621                 >;
 622         };
 623
 624         pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp {
 625                 fsl,pins = <
 626                         MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x0
 627                 >;
 628         };
 629
 630         pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
 631                 fsl,pins = <
 632                         MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11       0x130a0
 633                 >;
 634         };
 635 };