1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2018-2022 Toradex
6 #include "imx6ull.dtsi"
9 /* Ethernet aliases to ensure correct MAC addresses */
15 backlight: backlight {
16 compatible = "pwm-backlight";
17 brightness-levels = <0 4 8 16 32 64 128 255>;
18 default-brightness-level = <6>;
19 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_gpio_bl_on>;
22 power-supply = <®_3v3>;
23 pwms = <&pwm4 0 5000000 1>;
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
33 debounce-interval = <10>;
34 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
36 linux,code = <KEY_WAKEUP>;
41 panel_dpi: panel-dpi {
42 compatible = "edt,et057090dhu";
43 backlight = <&backlight>;
44 power-supply = <®_3v3>;
48 lcd_panel_in: endpoint {
49 remote-endpoint = <&lcdif_out>;
54 reg_module_3v3: regulator-module-3v3 {
55 compatible = "regulator-fixed";
57 regulator-name = "+V3.3";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
62 reg_module_3v3_avdd: regulator-module-3v3-avdd {
63 compatible = "regulator-fixed";
65 regulator-name = "+V3.3_AVDD_AUDIO";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
70 reg_sd1_vqmmc: regulator-sd1-vqmmc {
71 compatible = "regulator-gpio";
72 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
76 regulator-name = "+V3.3_1.8_SD";
77 regulator-min-microvolt = <1800000>;
78 regulator-max-microvolt = <3300000>;
79 states = <1800000 0x1 3300000 0x0>;
80 vin-supply = <®_module_3v3>;
83 reg_eth_phy: regulator-eth-phy {
84 compatible = "regulator-fixed-clock";
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
88 regulator-name = "+V3.3_ETH";
89 regulator-type = "voltage";
90 vin-supply = <®_module_3v3>;
91 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
92 startup-delay-us = <150000>;
98 vref-supply = <®_module_3v3_avdd>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_adc1>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_flexcan1>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_flexcan2>;
117 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
124 pinctrl-names = "default", "sleep";
125 pinctrl-0 = <&pinctrl_enet2>;
126 pinctrl-1 = <&pinctrl_enet2_sleep>;
128 phy-handle = <ðphy1>;
129 phy-supply = <®_eth_phy>;
133 #address-cells = <1>;
136 ethphy1: ethernet-phy@2 {
137 compatible = "ethernet-phy-ieee802.3-c22";
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_gpmi_nand>;
150 nand-ecc-mode = "hw";
151 nand-ecc-strength = <8>;
152 nand-ecc-step-size = <512>;
156 /* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
158 pinctrl-names = "default", "gpio";
159 pinctrl-0 = <&pinctrl_i2c1>;
160 pinctrl-1 = <&pinctrl_i2c1_gpio>;
161 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
162 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
165 /* Atmel maxtouch controller */
166 atmel_mxt_ts: touchscreen@4a {
167 compatible = "atmel,maxtouch";
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_atmel_conn>;
171 interrupt-parent = <&gpio5>;
172 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */
173 reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */
179 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
180 * touch screen controller
183 /* Use low frequency to compensate for the high pull-up values. */
184 clock-frequency = <40000>;
185 pinctrl-names = "default", "gpio";
186 pinctrl-0 = <&pinctrl_i2c2>;
187 pinctrl-1 = <&pinctrl_i2c2_gpio>;
188 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
189 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
192 ad7879_ts: touchscreen@2c {
193 compatible = "adi,ad7879-1";
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
197 interrupt-parent = <&gpio5>;
198 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
199 touchscreen-max-pressure = <4096>;
200 adi,resistance-plate-x = <120>;
201 adi,first-conversion-delay = /bits/ 8 <3>;
202 adi,acquisition-time = /bits/ 8 <1>;
203 adi,median-filter-size = /bits/ 8 <2>;
204 adi,averaging = /bits/ 8 <1>;
205 adi,conversion-interval = /bits/ 8 <255>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_lcdif_dat
212 &pinctrl_lcdif_ctrl>;
215 lcdif_out: endpoint {
216 remote-endpoint = <&lcd_panel_in>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_pwm4>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_pwm5>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_pwm6>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_pwm7>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_uart2>;
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_uart5>;
291 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
292 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
293 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
294 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
295 pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>;
296 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
297 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
298 assigned-clock-rates = <0>, <198000000>;
300 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
302 keep-power-in-suspend;
304 vqmmc-supply = <®_sd1_vqmmc>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_wdog>;
311 fsl,ext-reset-output;
315 pinctrl_adc1: adc1grp {
317 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
318 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
319 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
320 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
324 pinctrl_atmel_adap: atmeladapgrp {
326 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */
327 MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */
331 pinctrl_atmel_conn: atmelconngrp {
333 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */
334 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
338 pinctrl_can_int: canintgrp {
340 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
344 pinctrl_enet2: enet2grp {
346 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
347 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
348 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
349 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
350 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
351 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
352 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
353 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
354 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
355 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
359 pinctrl_enet2_sleep: enet2-sleepgrp {
361 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
362 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
363 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
364 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
365 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
366 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
367 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
368 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
369 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
370 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
374 pinctrl_ecspi1_cs: ecspi1csgrp {
376 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
380 pinctrl_ecspi1: ecspi1grp {
382 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
383 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
384 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */
388 pinctrl_flexcan1: flexcan1grp {
390 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
391 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
395 pinctrl_flexcan2: flexcan2grp {
397 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
398 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
402 pinctrl_gpio_bl_on: gpioblongrp {
404 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
408 pinctrl_gpio1: gpio1grp {
410 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
411 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
412 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */
413 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */
414 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */
415 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */
416 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */
417 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */
421 pinctrl_gpio2: gpio2grp { /* Camera */
423 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
424 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
425 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */
426 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */
427 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */
431 pinctrl_gpio3: gpio3grp { /* CAN2 */
433 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
434 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
438 pinctrl_gpio4: gpio4grp {
440 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
444 pinctrl_gpio6: gpio6grp { /* Wifi pins */
446 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
447 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
448 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */
449 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */
450 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */
451 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */
452 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */
456 pinctrl_gpio7: gpio7grp { /* CAN1 */
458 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
459 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
464 * With an eMMC instead of a raw NAND device the following pins
465 * are available at SODIMM pins.
467 pinctrl_gpmi_gpio: gpmigpiogrp {
469 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */
470 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */
471 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */
472 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */
476 pinctrl_gpmi_nand: gpminandgrp {
478 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
479 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
480 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
481 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
482 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
483 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
484 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
485 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
486 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
487 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
488 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
489 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
490 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
491 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
495 pinctrl_i2c1: i2c1grp {
497 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
498 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
502 pinctrl_i2c1_gpio: i2c1-gpiogrp {
504 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
505 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
509 pinctrl_i2c2: i2c2grp {
511 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
512 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
516 pinctrl_i2c2_gpio: i2c2-gpiogrp {
518 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
519 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
523 pinctrl_lcdif_dat: lcdifdatgrp {
525 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
526 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
527 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */
528 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */
529 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */
530 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */
531 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */
532 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */
533 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */
534 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */
535 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */
536 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */
537 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */
538 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */
539 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */
540 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */
541 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */
542 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */
546 pinctrl_lcdif_ctrl: lcdifctrlgrp {
548 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
549 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
550 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */
551 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */
555 pinctrl_pwm4: pwm4grp {
557 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
561 pinctrl_pwm5: pwm5grp {
563 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
567 pinctrl_pwm6: pwm6grp {
569 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
573 pinctrl_pwm7: pwm7grp {
575 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
579 pinctrl_uart1: uart1grp {
581 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
582 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
583 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */
584 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
588 pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */
590 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
591 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
592 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */
593 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
597 pinctrl_uart2: uart2grp {
599 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
600 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
601 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */
602 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
605 pinctrl_uart5: uart5grp {
607 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
608 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
612 pinctrl_usbh_reg: usbhreggrp {
614 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
618 pinctrl_usdhc1: usdhc1grp {
620 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
621 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
622 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
623 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
624 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
625 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
629 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
631 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
632 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
633 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
634 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
635 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
636 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
640 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
642 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
643 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
644 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
645 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
646 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
647 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
651 pinctrl_usdhc2: usdhc2grp {
653 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069
654 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
655 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069
656 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069
657 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069
658 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069
660 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
664 pinctrl_usdhc2emmc: usdhc2emmcgrp {
666 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
667 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
668 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
669 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
670 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
671 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
672 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
673 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
674 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
675 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
679 pinctrl_wdog: wdoggrp {
681 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
687 pinctrl_snvs_gpio1: snvsgpio1grp {
689 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
690 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
691 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
692 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */
693 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
697 pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */
699 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
703 pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */
705 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
709 pinctrl_snvs_reg_sd: snvsregsdgrp {
711 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
715 pinctrl_snvs_usbc_det: snvsusbcdetgrp {
717 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
721 pinctrl_snvs_gpiokeys: snvsgpiokeysgrp {
723 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */
727 pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp {
729 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
733 pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp {
735 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
739 pinctrl_snvs_wifi_pdn: snvswifipdngrp {
741 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0