arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ul-pinfunc.h"
  14
  15 / {
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         /*
  19          * The decompressor and also some bootloaders rely on a
  20          * pre-existing /chosen node to be available to insert the
  21          * command line and merge other ATAGS info.
  22          * Also for U-Boot there must be a pre-existing /memory node.
  23          */
  24         chosen {};
  25         memory { device_type = "memory"; reg = <0 0>; };
  26
  27         aliases {
  28                 ethernet0 = &fec1;
  29                 ethernet1 = &fec2;
  30                 gpio0 = &gpio1;
  31                 gpio1 = &gpio2;
  32                 gpio2 = &gpio3;
  33                 gpio3 = &gpio4;
  34                 gpio4 = &gpio5;
  35                 i2c0 = &i2c1;
  36                 i2c1 = &i2c2;
  37                 i2c2 = &i2c3;
  38                 i2c3 = &i2c4;
  39                 mmc0 = &usdhc1;
  40                 mmc1 = &usdhc2;
  41                 serial0 = &uart1;
  42                 serial1 = &uart2;
  43                 serial2 = &uart3;
  44                 serial3 = &uart4;
  45                 serial4 = &uart5;
  46                 serial5 = &uart6;
  47                 serial6 = &uart7;
  48                 serial7 = &uart8;
  49                 sai1 = &sai1;
  50                 sai2 = &sai2;
  51                 sai3 = &sai3;
  52                 spi0 = &ecspi1;
  53                 spi1 = &ecspi2;
  54                 spi2 = &ecspi3;
  55                 spi3 = &ecspi4;
  56                 usbphy0 = &usbphy1;
  57                 usbphy1 = &usbphy2;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@0 {
  65                         compatible = "arm,cortex-a7";
  66                         device_type = "cpu";
  67                         reg = <0>;
  68                         clock-latency = <61036>; /* two CLK32 periods */
  69                         operating-points = <
  70                                 /* kHz  uV */
  71                                 696000  1275000
  72                                 528000  1175000
  73                                 396000  1025000
  74                                 198000  950000
  75                         >;
  76                         fsl,soc-operating-points = <
  77                                 /* KHz  uV */
  78                                 696000  1275000
  79                                 528000  1175000
  80                                 396000  1175000
  81                                 198000  1175000
  82                         >;
  83                         clocks = <&clks IMX6UL_CLK_ARM>,
  84                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  85                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  86                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  87                                  <&clks IMX6UL_CLK_STEP>,
  88                                  <&clks IMX6UL_CLK_PLL1_SW>,
  89                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  90                                  <&clks IMX6UL_PLL1_BYPASS>,
  91                                  <&clks IMX6UL_CLK_PLL1>,
  92                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  93                                  <&clks IMX6UL_CLK_OSC>;
  94                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  95                                       "secondary_sel", "step", "pll1_sw",
  96                                       "pll1_sys", "pll1_bypass", "pll1",
  97                                       "pll1_bypass_src", "osc";
  98                         arm-supply = <&reg_arm>;
  99                         soc-supply = <&reg_soc>;
 100                 };
 101         };
 102
 103         intc: interrupt-controller@a01000 {
 104                 compatible = "arm,gic-400", "arm,cortex-a7-gic";
 105                 #interrupt-cells = <3>;
 106                 interrupt-controller;
 107                 reg = <0x00a01000 0x1000>,
 108                       <0x00a02000 0x2000>,
 109                       <0x00a04000 0x2000>,
 110                       <0x00a06000 0x2000>;
 111         };
 112
 113         ckil: clock-cli {
 114                 compatible = "fixed-clock";
 115                 #clock-cells = <0>;
 116                 clock-frequency = <32768>;
 117                 clock-output-names = "ckil";
 118         };
 119
 120         osc: clock-osc {
 121                 compatible = "fixed-clock";
 122                 #clock-cells = <0>;
 123                 clock-frequency = <24000000>;
 124                 clock-output-names = "osc";
 125         };
 126
 127         ipp_di0: clock-di0 {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <0>;
 131                 clock-output-names = "ipp_di0";
 132         };
 133
 134         ipp_di1: clock-di1 {
 135                 compatible = "fixed-clock";
 136                 #clock-cells = <0>;
 137                 clock-frequency = <0>;
 138                 clock-output-names = "ipp_di1";
 139         };
 140
 141         soc {
 142                 #address-cells = <1>;
 143                 #size-cells = <1>;
 144                 compatible = "simple-bus";
 145                 interrupt-parent = <&gpc>;
 146                 ranges;
 147
 148                 pmu {
 149                         compatible = "arm,cortex-a7-pmu";
 150                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 151                         status = "disabled";
 152                 };
 153
 154                 ocram: sram@900000 {
 155                         compatible = "mmio-sram";
 156                         reg = <0x00900000 0x20000>;
 157                 };
 158
 159                 dma_apbh: dma-apbh@1804000 {
 160                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 161                         reg = <0x01804000 0x2000>;
 162                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 163                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 164                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 165                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 166                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 167                         #dma-cells = <1>;
 168                         dma-channels = <4>;
 169                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 170                 };
 171
 172                 gpmi: gpmi-nand@1806000         {
 173                         compatible = "fsl,imx6q-gpmi-nand";
 174                         #address-cells = <1>;
 175                         #size-cells = <1>;
 176                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 177                         reg-names = "gpmi-nand", "bch";
 178                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 179                         interrupt-names = "bch";
 180                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 181                                  <&clks IMX6UL_CLK_GPMI_APB>,
 182                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 183                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 184                                  <&clks IMX6UL_CLK_PER_BCH>;
 185                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 186                                       "gpmi_bch_apb", "per1_bch";
 187                         dmas = <&dma_apbh 0>;
 188                         dma-names = "rx-tx";
 189                         status = "disabled";
 190                 };
 191
 192                 aips1: aips-bus@2000000 {
 193                         compatible = "fsl,aips-bus", "simple-bus";
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196                         reg = <0x02000000 0x100000>;
 197                         ranges;
 198
 199                         spba-bus@2000000 {
 200                                 compatible = "fsl,spba-bus", "simple-bus";
 201                                 #address-cells = <1>;
 202                                 #size-cells = <1>;
 203                                 reg = <0x02000000 0x40000>;
 204                                 ranges;
 205
 206                                 ecspi1: ecspi@2008000 {
 207                                         #address-cells = <1>;
 208                                         #size-cells = <0>;
 209                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 210                                         reg = <0x02008000 0x4000>;
 211                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 212                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 213                                                  <&clks IMX6UL_CLK_ECSPI1>;
 214                                         clock-names = "ipg", "per";
 215                                         status = "disabled";
 216                                 };
 217
 218                                 ecspi2: ecspi@200c000 {
 219                                         #address-cells = <1>;
 220                                         #size-cells = <0>;
 221                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 222                                         reg = <0x0200c000 0x4000>;
 223                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 224                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 225                                                  <&clks IMX6UL_CLK_ECSPI2>;
 226                                         clock-names = "ipg", "per";
 227                                         status = "disabled";
 228                                 };
 229
 230                                 ecspi3: ecspi@2010000 {
 231                                         #address-cells = <1>;
 232                                         #size-cells = <0>;
 233                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 234                                         reg = <0x02010000 0x4000>;
 235                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 236                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 237                                                  <&clks IMX6UL_CLK_ECSPI3>;
 238                                         clock-names = "ipg", "per";
 239                                         status = "disabled";
 240                                 };
 241
 242                                 ecspi4: ecspi@2014000 {
 243                                         #address-cells = <1>;
 244                                         #size-cells = <0>;
 245                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 246                                         reg = <0x02014000 0x4000>;
 247                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 248                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 249                                                  <&clks IMX6UL_CLK_ECSPI4>;
 250                                         clock-names = "ipg", "per";
 251                                         status = "disabled";
 252                                 };
 253
 254                                 uart7: serial@2018000 {
 255                                         compatible = "fsl,imx6ul-uart",
 256                                                      "fsl,imx6q-uart";
 257                                         reg = <0x02018000 0x4000>;
 258                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 259                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 260                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 261                                         clock-names = "ipg", "per";
 262                                         status = "disabled";
 263                                 };
 264
 265                                 uart1: serial@2020000 {
 266                                         compatible = "fsl,imx6ul-uart",
 267                                                      "fsl,imx6q-uart";
 268                                         reg = <0x02020000 0x4000>;
 269                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 270                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 271                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 272                                         clock-names = "ipg", "per";
 273                                         status = "disabled";
 274                                 };
 275
 276                                 uart8: serial@2024000 {
 277                                         compatible = "fsl,imx6ul-uart",
 278                                                      "fsl,imx6q-uart";
 279                                         reg = <0x02024000 0x4000>;
 280                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 281                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 282                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 283                                         clock-names = "ipg", "per";
 284                                         status = "disabled";
 285                                 };
 286
 287                                 sai1: sai@2028000 {
 288                                         #sound-dai-cells = <0>;
 289                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 290                                         reg = <0x02028000 0x4000>;
 291                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 292                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 293                                                  <&clks IMX6UL_CLK_SAI1>,
 294                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 295                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 296                                         dmas = <&sdma 35 24 0>,
 297                                                <&sdma 36 24 0>;
 298                                         dma-names = "rx", "tx";
 299                                         status = "disabled";
 300                                 };
 301
 302                                 sai2: sai@202c000 {
 303                                         #sound-dai-cells = <0>;
 304                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 305                                         reg = <0x0202c000 0x4000>;
 306                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 307                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 308                                                  <&clks IMX6UL_CLK_SAI2>,
 309                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 310                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 311                                         dmas = <&sdma 37 24 0>,
 312                                                <&sdma 38 24 0>;
 313                                         dma-names = "rx", "tx";
 314                                         status = "disabled";
 315                                 };
 316
 317                                 sai3: sai@2030000 {
 318                                         #sound-dai-cells = <0>;
 319                                         compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
 320                                         reg = <0x02030000 0x4000>;
 321                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 322                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 323                                                  <&clks IMX6UL_CLK_SAI3>,
 324                                                  <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
 325                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 326                                         dmas = <&sdma 39 24 0>,
 327                                                <&sdma 40 24 0>;
 328                                         dma-names = "rx", "tx";
 329                                         status = "disabled";
 330                                 };
 331                         };
 332
 333                         tsc: tsc@2040000 {
 334                                 compatible = "fsl,imx6ul-tsc";
 335                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 336                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 337                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clks IMX6UL_CLK_IPG>,
 339                                          <&clks IMX6UL_CLK_ADC2>;
 340                                 clock-names = "tsc", "adc";
 341                                 status = "disabled";
 342                         };
 343
 344                         pwm1: pwm@2080000 {
 345                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 346                                 reg = <0x02080000 0x4000>;
 347                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 348                                 clocks = <&clks IMX6UL_CLK_PWM1>,
 349                                          <&clks IMX6UL_CLK_PWM1>;
 350                                 clock-names = "ipg", "per";
 351                                 #pwm-cells = <2>;
 352                                 status = "disabled";
 353                         };
 354
 355                         pwm2: pwm@2084000 {
 356                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 357                                 reg = <0x02084000 0x4000>;
 358                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 359                                 clocks = <&clks IMX6UL_CLK_PWM2>,
 360                                          <&clks IMX6UL_CLK_PWM2>;
 361                                 clock-names = "ipg", "per";
 362                                 #pwm-cells = <2>;
 363                                 status = "disabled";
 364                         };
 365
 366                         pwm3: pwm@2088000 {
 367                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 368                                 reg = <0x02088000 0x4000>;
 369                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 370                                 clocks = <&clks IMX6UL_CLK_PWM3>,
 371                                          <&clks IMX6UL_CLK_PWM3>;
 372                                 clock-names = "ipg", "per";
 373                                 #pwm-cells = <2>;
 374                                 status = "disabled";
 375                         };
 376
 377                         pwm4: pwm@208c000 {
 378                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 379                                 reg = <0x0208c000 0x4000>;
 380                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 381                                 clocks = <&clks IMX6UL_CLK_PWM4>,
 382                                          <&clks IMX6UL_CLK_PWM4>;
 383                                 clock-names = "ipg", "per";
 384                                 #pwm-cells = <2>;
 385                                 status = "disabled";
 386                         };
 387
 388                         can1: flexcan@2090000 {
 389                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 390                                 reg = <0x02090000 0x4000>;
 391                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 392                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 393                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 394                                 clock-names = "ipg", "per";
 395                                 status = "disabled";
 396                         };
 397
 398                         can2: flexcan@2094000 {
 399                                 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
 400                                 reg = <0x02094000 0x4000>;
 401                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 402                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 403                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 404                                 clock-names = "ipg", "per";
 405                                 status = "disabled";
 406                         };
 407
 408                         gpt1: gpt@2098000 {
 409                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 410                                 reg = <0x02098000 0x4000>;
 411                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 412                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 413                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 414                                 clock-names = "ipg", "per";
 415                         };
 416
 417                         gpio1: gpio@209c000 {
 418                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 419                                 reg = <0x0209c000 0x4000>;
 420                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 421                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 422                                 gpio-controller;
 423                                 #gpio-cells = <2>;
 424                                 interrupt-controller;
 425                                 #interrupt-cells = <2>;
 426                                 gpio-ranges = <&iomuxc  0 23 10>, <&iomuxc 10 17 6>,
 427                                               <&iomuxc 16 33 16>;
 428                         };
 429
 430                         gpio2: gpio@20a0000 {
 431                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 432                                 reg = <0x020a0000 0x4000>;
 433                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 434                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 435                                 gpio-controller;
 436                                 #gpio-cells = <2>;
 437                                 interrupt-controller;
 438                                 #interrupt-cells = <2>;
 439                                 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
 440                         };
 441
 442                         gpio3: gpio@20a4000 {
 443                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 444                                 reg = <0x020a4000 0x4000>;
 445                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 446                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 447                                 gpio-controller;
 448                                 #gpio-cells = <2>;
 449                                 interrupt-controller;
 450                                 #interrupt-cells = <2>;
 451                                 gpio-ranges = <&iomuxc 0 65 29>;
 452                         };
 453
 454                         gpio4: gpio@20a8000 {
 455                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 456                                 reg = <0x020a8000 0x4000>;
 457                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 458                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 459                                 gpio-controller;
 460                                 #gpio-cells = <2>;
 461                                 interrupt-controller;
 462                                 #interrupt-cells = <2>;
 463                                 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
 464                         };
 465
 466                         gpio5: gpio@20ac000 {
 467                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 468                                 reg = <0x020ac000 0x4000>;
 469                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 470                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 471                                 gpio-controller;
 472                                 #gpio-cells = <2>;
 473                                 interrupt-controller;
 474                                 #interrupt-cells = <2>;
 475                                 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
 476                         };
 477
 478                         fec2: ethernet@20b4000 {
 479                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 480                                 reg = <0x020b4000 0x4000>;
 481                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 482                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 483                                 clocks = <&clks IMX6UL_CLK_ENET>,
 484                                          <&clks IMX6UL_CLK_ENET_AHB>,
 485                                          <&clks IMX6UL_CLK_ENET_PTP>,
 486                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 487                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 488                                 clock-names = "ipg", "ahb", "ptp",
 489                                               "enet_clk_ref", "enet_out";
 490                                 fsl,num-tx-queues=<1>;
 491                                 fsl,num-rx-queues=<1>;
 492                                 status = "disabled";
 493                         };
 494
 495                         kpp: kpp@20b8000 {
 496                                 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
 497                                 reg = <0x020b8000 0x4000>;
 498                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 499                                 clocks = <&clks IMX6UL_CLK_KPP>;
 500                                 status = "disabled";
 501                         };
 502
 503                         wdog1: wdog@20bc000 {
 504                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 505                                 reg = <0x020bc000 0x4000>;
 506                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 507                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 508                         };
 509
 510                         wdog2: wdog@20c0000 {
 511                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 512                                 reg = <0x020c0000 0x4000>;
 513                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 514                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 515                                 status = "disabled";
 516                         };
 517
 518                         clks: ccm@20c4000 {
 519                                 compatible = "fsl,imx6ul-ccm";
 520                                 reg = <0x020c4000 0x4000>;
 521                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 522                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 523                                 #clock-cells = <1>;
 524                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 525                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 526                         };
 527
 528                         anatop: anatop@20c8000 {
 529                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 530                                              "syscon", "simple-bus";
 531                                 reg = <0x020c8000 0x1000>;
 532                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 533                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 534                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 535
 536                                 reg_3p0: regulator-3p0 {
 537                                         compatible = "fsl,anatop-regulator";
 538                                         regulator-name = "vdd3p0";
 539                                         regulator-min-microvolt = <2625000>;
 540                                         regulator-max-microvolt = <3400000>;
 541                                         anatop-reg-offset = <0x120>;
 542                                         anatop-vol-bit-shift = <8>;
 543                                         anatop-vol-bit-width = <5>;
 544                                         anatop-min-bit-val = <0>;
 545                                         anatop-min-voltage = <2625000>;
 546                                         anatop-max-voltage = <3400000>;
 547                                         anatop-enable-bit = <0>;
 548                                 };
 549
 550                                 reg_arm: regulator-vddcore {
 551                                         compatible = "fsl,anatop-regulator";
 552                                         regulator-name = "cpu";
 553                                         regulator-min-microvolt = <725000>;
 554                                         regulator-max-microvolt = <1450000>;
 555                                         regulator-always-on;
 556                                         anatop-reg-offset = <0x140>;
 557                                         anatop-vol-bit-shift = <0>;
 558                                         anatop-vol-bit-width = <5>;
 559                                         anatop-delay-reg-offset = <0x170>;
 560                                         anatop-delay-bit-shift = <24>;
 561                                         anatop-delay-bit-width = <2>;
 562                                         anatop-min-bit-val = <1>;
 563                                         anatop-min-voltage = <725000>;
 564                                         anatop-max-voltage = <1450000>;
 565                                 };
 566
 567                                 reg_soc: regulator-vddsoc {
 568                                         compatible = "fsl,anatop-regulator";
 569                                         regulator-name = "vddsoc";
 570                                         regulator-min-microvolt = <725000>;
 571                                         regulator-max-microvolt = <1450000>;
 572                                         regulator-always-on;
 573                                         anatop-reg-offset = <0x140>;
 574                                         anatop-vol-bit-shift = <18>;
 575                                         anatop-vol-bit-width = <5>;
 576                                         anatop-delay-reg-offset = <0x170>;
 577                                         anatop-delay-bit-shift = <28>;
 578                                         anatop-delay-bit-width = <2>;
 579                                         anatop-min-bit-val = <1>;
 580                                         anatop-min-voltage = <725000>;
 581                                         anatop-max-voltage = <1450000>;
 582                                 };
 583                         };
 584
 585                         usbphy1: usbphy@20c9000 {
 586                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 587                                 reg = <0x020c9000 0x1000>;
 588                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 589                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 590                                 phy-3p0-supply = <&reg_3p0>;
 591                                 fsl,anatop = <&anatop>;
 592                         };
 593
 594                         usbphy2: usbphy@20ca000 {
 595                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 596                                 reg = <0x020ca000 0x1000>;
 597                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 598                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 599                                 phy-3p0-supply = <&reg_3p0>;
 600                                 fsl,anatop = <&anatop>;
 601                         };
 602
 603                         tempmon: tempmon {
 604                                 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
 605                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 606                                 fsl,tempmon = <&anatop>;
 607                                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 608                                 nvmem-cell-names = "calib", "temp_grade";
 609                                 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
 610                         };
 611
 612                         snvs: snvs@20cc000 {
 613                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 614                                 reg = <0x020cc000 0x4000>;
 615
 616                                 snvs_rtc: snvs-rtc-lp {
 617                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 618                                         regmap = <&snvs>;
 619                                         offset = <0x34>;
 620                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 621                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 622                                 };
 623
 624                                 snvs_poweroff: snvs-poweroff {
 625                                         compatible = "syscon-poweroff";
 626                                         regmap = <&snvs>;
 627                                         offset = <0x38>;
 628                                         value = <0x60>;
 629                                         mask = <0x60>;
 630                                         status = "disabled";
 631                                 };
 632
 633                                 snvs_pwrkey: snvs-powerkey {
 634                                         compatible = "fsl,sec-v4.0-pwrkey";
 635                                         regmap = <&snvs>;
 636                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 637                                         linux,keycode = <KEY_POWER>;
 638                                         wakeup-source;
 639                                 };
 640                         };
 641
 642                         epit1: epit@20d0000 {
 643                                 reg = <0x020d0000 0x4000>;
 644                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 645                         };
 646
 647                         epit2: epit@20d4000 {
 648                                 reg = <0x020d4000 0x4000>;
 649                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 650                         };
 651
 652                         src: src@20d8000 {
 653                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 654                                 reg = <0x020d8000 0x4000>;
 655                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 656                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 657                                 #reset-cells = <1>;
 658                         };
 659
 660                         gpc: gpc@20dc000 {
 661                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 662                                 reg = <0x020dc000 0x4000>;
 663                                 interrupt-controller;
 664                                 #interrupt-cells = <3>;
 665                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 666                                 interrupt-parent = <&intc>;
 667                         };
 668
 669                         iomuxc: iomuxc@20e0000 {
 670                                 compatible = "fsl,imx6ul-iomuxc";
 671                                 reg = <0x020e0000 0x4000>;
 672                         };
 673
 674                         gpr: iomuxc-gpr@20e4000 {
 675                                 compatible = "fsl,imx6ul-iomuxc-gpr",
 676                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 677                                 reg = <0x020e4000 0x4000>;
 678                         };
 679
 680                         gpt2: gpt@20e8000 {
 681                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 682                                 reg = <0x020e8000 0x4000>;
 683                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 684                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 685                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 686                                 clock-names = "ipg", "per";
 687                         };
 688
 689                         sdma: sdma@20ec000 {
 690                                 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
 691                                              "fsl,imx35-sdma";
 692                                 reg = <0x020ec000 0x4000>;
 693                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 694                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 695                                          <&clks IMX6UL_CLK_SDMA>;
 696                                 clock-names = "ipg", "ahb";
 697                                 #dma-cells = <3>;
 698                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 699                         };
 700
 701                         pwm5: pwm@20f0000 {
 702                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 703                                 reg = <0x020f0000 0x4000>;
 704                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 705                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 706                                          <&clks IMX6UL_CLK_PWM5>;
 707                                 clock-names = "ipg", "per";
 708                                 #pwm-cells = <2>;
 709                                 status = "disabled";
 710                         };
 711
 712                         pwm6: pwm@20f4000 {
 713                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 714                                 reg = <0x020f4000 0x4000>;
 715                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 716                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 717                                          <&clks IMX6UL_CLK_PWM6>;
 718                                 clock-names = "ipg", "per";
 719                                 #pwm-cells = <2>;
 720                                 status = "disabled";
 721                         };
 722
 723                         pwm7: pwm@20f8000 {
 724                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 725                                 reg = <0x020f8000 0x4000>;
 726                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 727                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 728                                          <&clks IMX6UL_CLK_PWM7>;
 729                                 clock-names = "ipg", "per";
 730                                 #pwm-cells = <2>;
 731                                 status = "disabled";
 732                         };
 733
 734                         pwm8: pwm@20fc000 {
 735                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 736                                 reg = <0x020fc000 0x4000>;
 737                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 738                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 739                                          <&clks IMX6UL_CLK_PWM8>;
 740                                 clock-names = "ipg", "per";
 741                                 #pwm-cells = <2>;
 742                                 status = "disabled";
 743                         };
 744                 };
 745
 746                 aips2: aips-bus@2100000 {
 747                         compatible = "fsl,aips-bus", "simple-bus";
 748                         #address-cells = <1>;
 749                         #size-cells = <1>;
 750                         reg = <0x02100000 0x100000>;
 751                         ranges;
 752
 753                         usbotg1: usb@2184000 {
 754                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 755                                 reg = <0x02184000 0x200>;
 756                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 757                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 758                                 fsl,usbphy = <&usbphy1>;
 759                                 fsl,usbmisc = <&usbmisc 0>;
 760                                 fsl,anatop = <&anatop>;
 761                                 ahb-burst-config = <0x0>;
 762                                 tx-burst-size-dword = <0x10>;
 763                                 rx-burst-size-dword = <0x10>;
 764                                 status = "disabled";
 765                         };
 766
 767                         usbotg2: usb@2184200 {
 768                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 769                                 reg = <0x02184200 0x200>;
 770                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 771                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 772                                 fsl,usbphy = <&usbphy2>;
 773                                 fsl,usbmisc = <&usbmisc 1>;
 774                                 ahb-burst-config = <0x0>;
 775                                 tx-burst-size-dword = <0x10>;
 776                                 rx-burst-size-dword = <0x10>;
 777                                 status = "disabled";
 778                         };
 779
 780                         usbmisc: usbmisc@2184800 {
 781                                 #index-cells = <1>;
 782                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 783                                 reg = <0x02184800 0x200>;
 784                         };
 785
 786                         fec1: ethernet@2188000 {
 787                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 788                                 reg = <0x02188000 0x4000>;
 789                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 790                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 791                                 clocks = <&clks IMX6UL_CLK_ENET>,
 792                                          <&clks IMX6UL_CLK_ENET_AHB>,
 793                                          <&clks IMX6UL_CLK_ENET_PTP>,
 794                                          <&clks IMX6UL_CLK_ENET_REF>,
 795                                          <&clks IMX6UL_CLK_ENET_REF>;
 796                                 clock-names = "ipg", "ahb", "ptp",
 797                                               "enet_clk_ref", "enet_out";
 798                                 fsl,num-tx-queues=<1>;
 799                                 fsl,num-rx-queues=<1>;
 800                                 status = "disabled";
 801                         };
 802
 803                         usdhc1: usdhc@2190000 {
 804                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 805                                 reg = <0x02190000 0x4000>;
 806                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 807                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 808                                          <&clks IMX6UL_CLK_USDHC1>,
 809                                          <&clks IMX6UL_CLK_USDHC1>;
 810                                 clock-names = "ipg", "ahb", "per";
 811                                 bus-width = <4>;
 812                                 status = "disabled";
 813                         };
 814
 815                         usdhc2: usdhc@2194000 {
 816                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 817                                 reg = <0x02194000 0x4000>;
 818                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 819                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 820                                          <&clks IMX6UL_CLK_USDHC2>,
 821                                          <&clks IMX6UL_CLK_USDHC2>;
 822                                 clock-names = "ipg", "ahb", "per";
 823                                 bus-width = <4>;
 824                                 status = "disabled";
 825                         };
 826
 827                         adc1: adc@2198000 {
 828                                 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
 829                                 reg = <0x02198000 0x4000>;
 830                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 831                                 clocks = <&clks IMX6UL_CLK_ADC1>;
 832                                 num-channels = <2>;
 833                                 clock-names = "adc";
 834                                 fsl,adck-max-frequency = <30000000>, <40000000>,
 835                                                          <20000000>;
 836                                 status = "disabled";
 837                         };
 838
 839                         i2c1: i2c@21a0000 {
 840                                 #address-cells = <1>;
 841                                 #size-cells = <0>;
 842                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 843                                 reg = <0x021a0000 0x4000>;
 844                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 845                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 846                                 status = "disabled";
 847                         };
 848
 849                         i2c2: i2c@21a4000 {
 850                                 #address-cells = <1>;
 851                                 #size-cells = <0>;
 852                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 853                                 reg = <0x021a4000 0x4000>;
 854                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 855                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 856                                 status = "disabled";
 857                         };
 858
 859                         i2c3: i2c@21a8000 {
 860                                 #address-cells = <1>;
 861                                 #size-cells = <0>;
 862                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 863                                 reg = <0x021a8000 0x4000>;
 864                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 865                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 866                                 status = "disabled";
 867                         };
 868
 869                         mmdc: mmdc@21b0000 {
 870                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 871                                 reg = <0x021b0000 0x4000>;
 872                         };
 873
 874                         ocotp: ocotp-ctrl@21bc000 {
 875                                 #address-cells = <1>;
 876                                 #size-cells = <1>;
 877                                 compatible = "fsl,imx6ul-ocotp", "syscon";
 878                                 reg = <0x021bc000 0x4000>;
 879                                 clocks = <&clks IMX6UL_CLK_OCOTP>;
 880
 881                                 tempmon_calib: calib@38 {
 882                                         reg = <0x38 4>;
 883                                 };
 884
 885                                 tempmon_temp_grade: temp-grade@20 {
 886                                         reg = <0x20 4>;
 887                                 };
 888                         };
 889
 890                         lcdif: lcdif@21c8000 {
 891                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 892                                 reg = <0x021c8000 0x4000>;
 893                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 894                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 895                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 896                                          <&clks IMX6UL_CLK_DUMMY>;
 897                                 clock-names = "pix", "axi", "disp_axi";
 898                                 status = "disabled";
 899                         };
 900
 901                         qspi: qspi@21e0000 {
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 905                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 906                                 reg-names = "QuadSPI", "QuadSPI-memory";
 907                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 908                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 909                                          <&clks IMX6UL_CLK_QSPI>;
 910                                 clock-names = "qspi_en", "qspi";
 911                                 status = "disabled";
 912                         };
 913
 914                         uart2: serial@21e8000 {
 915                                 compatible = "fsl,imx6ul-uart",
 916                                              "fsl,imx6q-uart";
 917                                 reg = <0x021e8000 0x4000>;
 918                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 919                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 920                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 921                                 clock-names = "ipg", "per";
 922                                 status = "disabled";
 923                         };
 924
 925                         uart3: serial@21ec000 {
 926                                 compatible = "fsl,imx6ul-uart",
 927                                              "fsl,imx6q-uart";
 928                                 reg = <0x021ec000 0x4000>;
 929                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 930                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 931                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 932                                 clock-names = "ipg", "per";
 933                                 status = "disabled";
 934                         };
 935
 936                         uart4: serial@21f0000 {
 937                                 compatible = "fsl,imx6ul-uart",
 938                                              "fsl,imx6q-uart";
 939                                 reg = <0x021f0000 0x4000>;
 940                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 941                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 942                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 943                                 clock-names = "ipg", "per";
 944                                 status = "disabled";
 945                         };
 946
 947                         uart5: serial@21f4000 {
 948                                 compatible = "fsl,imx6ul-uart",
 949                                              "fsl,imx6q-uart";
 950                                 reg = <0x021f4000 0x4000>;
 951                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 952                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 953                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 954                                 clock-names = "ipg", "per";
 955                                 status = "disabled";
 956                         };
 957
 958                         i2c4: i2c@21f8000 {
 959                                 #address-cells = <1>;
 960                                 #size-cells = <0>;
 961                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 962                                 reg = <0x021f8000 0x4000>;
 963                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 964                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 965                                 status = "disabled";
 966                         };
 967
 968                         uart6: serial@21fc000 {
 969                                 compatible = "fsl,imx6ul-uart",
 970                                              "fsl,imx6q-uart";
 971                                 reg = <0x021fc000 0x4000>;
 972                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 973                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 974                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 975                                 clock-names = "ipg", "per";
 976                                 status = "disabled";
 977                         };
 978                 };
 979         };
 980 };