1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2015 Freescale Semiconductor, Inc.
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
59 compatible = "arm,cortex-a7";
62 clock-frequency = <696000000>;
63 clock-latency = <61036>; /* two CLK32 periods */
72 fsl,soc-operating-points = <
79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
85 <&clks IMX6UL_CLK_PLL1_SYS>;
86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
87 "secondary_sel", "step", "pll1_sw",
89 arm-supply = <®_arm>;
90 soc-supply = <®_soc>;
91 nvmem-cells = <&cpu_speed_grade>;
92 nvmem-cell-names = "speed_grade";
97 compatible = "arm,armv7-timer";
98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
102 interrupt-parent = <&intc>;
107 compatible = "fixed-clock";
109 clock-frequency = <32768>;
110 clock-output-names = "ckil";
114 compatible = "fixed-clock";
116 clock-frequency = <24000000>;
117 clock-output-names = "osc";
121 compatible = "fixed-clock";
123 clock-frequency = <0>;
124 clock-output-names = "ipp_di0";
128 compatible = "fixed-clock";
130 clock-frequency = <0>;
131 clock-output-names = "ipp_di1";
135 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
136 interrupt-parent = <&gpc>;
137 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
138 fsl,tempmon = <&anatop>;
139 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
140 nvmem-cell-names = "calib", "temp_grade";
141 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
145 compatible = "arm,cortex-a7-pmu";
146 interrupt-parent = <&gpc>;
147 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
151 #address-cells = <1>;
153 compatible = "simple-bus";
154 interrupt-parent = <&gpc>;
158 compatible = "mmio-sram";
159 reg = <0x00900000 0x20000>;
162 intc: interrupt-controller@a01000 {
163 compatible = "arm,gic-400", "arm,cortex-a7-gic";
164 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 interrupt-parent = <&intc>;
168 reg = <0x00a01000 0x1000>,
174 dma_apbh: dma-apbh@1804000 {
175 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
176 reg = <0x01804000 0x2000>;
177 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
178 <0 13 IRQ_TYPE_LEVEL_HIGH>,
179 <0 13 IRQ_TYPE_LEVEL_HIGH>,
180 <0 13 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
184 clocks = <&clks IMX6UL_CLK_APBHDMA>;
187 gpmi: gpmi-nand@1806000 {
188 compatible = "fsl,imx6q-gpmi-nand";
189 #address-cells = <1>;
191 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
192 reg-names = "gpmi-nand", "bch";
193 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
194 interrupt-names = "bch";
195 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
196 <&clks IMX6UL_CLK_GPMI_APB>,
197 <&clks IMX6UL_CLK_GPMI_BCH>,
198 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
199 <&clks IMX6UL_CLK_PER_BCH>;
200 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
201 "gpmi_bch_apb", "per1_bch";
202 dmas = <&dma_apbh 0>;
208 compatible = "fsl,aips-bus", "simple-bus";
209 #address-cells = <1>;
211 reg = <0x02000000 0x100000>;
215 compatible = "fsl,spba-bus", "simple-bus";
216 #address-cells = <1>;
218 reg = <0x02000000 0x40000>;
221 ecspi1: spi@2008000 {
222 #address-cells = <1>;
224 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
225 reg = <0x02008000 0x4000>;
226 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6UL_CLK_ECSPI1>,
228 <&clks IMX6UL_CLK_ECSPI1>;
229 clock-names = "ipg", "per";
230 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
231 dma-names = "rx", "tx";
235 ecspi2: spi@200c000 {
236 #address-cells = <1>;
238 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
239 reg = <0x0200c000 0x4000>;
240 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clks IMX6UL_CLK_ECSPI2>,
242 <&clks IMX6UL_CLK_ECSPI2>;
243 clock-names = "ipg", "per";
244 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
245 dma-names = "rx", "tx";
249 ecspi3: spi@2010000 {
250 #address-cells = <1>;
252 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
253 reg = <0x02010000 0x4000>;
254 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clks IMX6UL_CLK_ECSPI3>,
256 <&clks IMX6UL_CLK_ECSPI3>;
257 clock-names = "ipg", "per";
258 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
259 dma-names = "rx", "tx";
263 ecspi4: spi@2014000 {
264 #address-cells = <1>;
266 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6UL_CLK_ECSPI4>,
270 <&clks IMX6UL_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
272 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
273 dma-names = "rx", "tx";
277 uart7: serial@2018000 {
278 compatible = "fsl,imx6ul-uart",
280 reg = <0x02018000 0x4000>;
281 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
283 <&clks IMX6UL_CLK_UART7_SERIAL>;
284 clock-names = "ipg", "per";
288 uart1: serial@2020000 {
289 compatible = "fsl,imx6ul-uart",
291 reg = <0x02020000 0x4000>;
292 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
294 <&clks IMX6UL_CLK_UART1_SERIAL>;
295 clock-names = "ipg", "per";
299 uart8: serial@2024000 {
300 compatible = "fsl,imx6ul-uart",
302 reg = <0x02024000 0x4000>;
303 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
305 <&clks IMX6UL_CLK_UART8_SERIAL>;
306 clock-names = "ipg", "per";
311 #sound-dai-cells = <0>;
312 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
313 reg = <0x02028000 0x4000>;
314 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
316 <&clks IMX6UL_CLK_SAI1>,
317 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
318 clock-names = "bus", "mclk1", "mclk2", "mclk3";
319 dmas = <&sdma 35 24 0>,
321 dma-names = "rx", "tx";
326 #sound-dai-cells = <0>;
327 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
328 reg = <0x0202c000 0x4000>;
329 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
331 <&clks IMX6UL_CLK_SAI2>,
332 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
333 clock-names = "bus", "mclk1", "mclk2", "mclk3";
334 dmas = <&sdma 37 24 0>,
336 dma-names = "rx", "tx";
341 #sound-dai-cells = <0>;
342 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
343 reg = <0x02030000 0x4000>;
344 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
346 <&clks IMX6UL_CLK_SAI3>,
347 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
348 clock-names = "bus", "mclk1", "mclk2", "mclk3";
349 dmas = <&sdma 39 24 0>,
351 dma-names = "rx", "tx";
357 compatible = "fsl,imx6ul-tsc";
358 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
359 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6UL_CLK_IPG>,
362 <&clks IMX6UL_CLK_ADC2>;
363 clock-names = "tsc", "adc";
368 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
369 reg = <0x02080000 0x4000>;
370 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6UL_CLK_PWM1>,
372 <&clks IMX6UL_CLK_PWM1>;
373 clock-names = "ipg", "per";
379 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
380 reg = <0x02084000 0x4000>;
381 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clks IMX6UL_CLK_PWM2>,
383 <&clks IMX6UL_CLK_PWM2>;
384 clock-names = "ipg", "per";
390 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
391 reg = <0x02088000 0x4000>;
392 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&clks IMX6UL_CLK_PWM3>,
394 <&clks IMX6UL_CLK_PWM3>;
395 clock-names = "ipg", "per";
401 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
402 reg = <0x0208c000 0x4000>;
403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clks IMX6UL_CLK_PWM4>,
405 <&clks IMX6UL_CLK_PWM4>;
406 clock-names = "ipg", "per";
411 can1: flexcan@2090000 {
412 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
413 reg = <0x02090000 0x4000>;
414 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
416 <&clks IMX6UL_CLK_CAN1_SERIAL>;
417 clock-names = "ipg", "per";
418 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
422 can2: flexcan@2094000 {
423 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
424 reg = <0x02094000 0x4000>;
425 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
427 <&clks IMX6UL_CLK_CAN2_SERIAL>;
428 clock-names = "ipg", "per";
429 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
433 gpt1: timer@2098000 {
434 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
435 reg = <0x02098000 0x4000>;
436 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
438 <&clks IMX6UL_CLK_GPT1_SERIAL>;
439 clock-names = "ipg", "per";
442 gpio1: gpio@209c000 {
443 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
444 reg = <0x0209c000 0x4000>;
445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&clks IMX6UL_CLK_GPIO1>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
456 gpio2: gpio@20a0000 {
457 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
458 reg = <0x020a0000 0x4000>;
459 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX6UL_CLK_GPIO2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
469 gpio3: gpio@20a4000 {
470 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
471 reg = <0x020a4000 0x4000>;
472 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clks IMX6UL_CLK_GPIO3>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 gpio-ranges = <&iomuxc 0 65 29>;
482 gpio4: gpio@20a8000 {
483 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
484 reg = <0x020a8000 0x4000>;
485 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&clks IMX6UL_CLK_GPIO4>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
495 gpio5: gpio@20ac000 {
496 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
497 reg = <0x020ac000 0x4000>;
498 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&clks IMX6UL_CLK_GPIO5>;
503 interrupt-controller;
504 #interrupt-cells = <2>;
505 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
508 fec2: ethernet@20b4000 {
509 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
510 reg = <0x020b4000 0x4000>;
511 interrupt-names = "int0", "pps";
512 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clks IMX6UL_CLK_ENET>,
515 <&clks IMX6UL_CLK_ENET_AHB>,
516 <&clks IMX6UL_CLK_ENET_PTP>,
517 <&clks IMX6UL_CLK_ENET2_REF_125M>,
518 <&clks IMX6UL_CLK_ENET2_REF_125M>;
519 clock-names = "ipg", "ahb", "ptp",
520 "enet_clk_ref", "enet_out";
521 fsl,num-tx-queues = <1>;
522 fsl,num-rx-queues = <1>;
523 fsl,stop-mode = <&gpr 0x10 4>;
527 kpp: keypad@20b8000 {
528 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
529 reg = <0x020b8000 0x4000>;
530 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clks IMX6UL_CLK_KPP>;
535 wdog1: watchdog@20bc000 {
536 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
537 reg = <0x020bc000 0x4000>;
538 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&clks IMX6UL_CLK_WDOG1>;
542 wdog2: watchdog@20c0000 {
543 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
544 reg = <0x020c0000 0x4000>;
545 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clks IMX6UL_CLK_WDOG2>;
550 clks: clock-controller@20c4000 {
551 compatible = "fsl,imx6ul-ccm";
552 reg = <0x020c4000 0x4000>;
553 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
557 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
560 anatop: anatop@20c8000 {
561 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
562 "syscon", "simple-mfd";
563 reg = <0x020c8000 0x1000>;
564 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
568 reg_3p0: regulator-3p0 {
569 compatible = "fsl,anatop-regulator";
570 regulator-name = "vdd3p0";
571 regulator-min-microvolt = <2625000>;
572 regulator-max-microvolt = <3400000>;
573 anatop-reg-offset = <0x120>;
574 anatop-vol-bit-shift = <8>;
575 anatop-vol-bit-width = <5>;
576 anatop-min-bit-val = <0>;
577 anatop-min-voltage = <2625000>;
578 anatop-max-voltage = <3400000>;
579 anatop-enable-bit = <0>;
582 reg_arm: regulator-vddcore {
583 compatible = "fsl,anatop-regulator";
584 regulator-name = "cpu";
585 regulator-min-microvolt = <725000>;
586 regulator-max-microvolt = <1450000>;
588 anatop-reg-offset = <0x140>;
589 anatop-vol-bit-shift = <0>;
590 anatop-vol-bit-width = <5>;
591 anatop-delay-reg-offset = <0x170>;
592 anatop-delay-bit-shift = <24>;
593 anatop-delay-bit-width = <2>;
594 anatop-min-bit-val = <1>;
595 anatop-min-voltage = <725000>;
596 anatop-max-voltage = <1450000>;
599 reg_soc: regulator-vddsoc {
600 compatible = "fsl,anatop-regulator";
601 regulator-name = "vddsoc";
602 regulator-min-microvolt = <725000>;
603 regulator-max-microvolt = <1450000>;
605 anatop-reg-offset = <0x140>;
606 anatop-vol-bit-shift = <18>;
607 anatop-vol-bit-width = <5>;
608 anatop-delay-reg-offset = <0x170>;
609 anatop-delay-bit-shift = <28>;
610 anatop-delay-bit-width = <2>;
611 anatop-min-bit-val = <1>;
612 anatop-min-voltage = <725000>;
613 anatop-max-voltage = <1450000>;
617 usbphy1: usbphy@20c9000 {
618 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
619 reg = <0x020c9000 0x1000>;
620 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&clks IMX6UL_CLK_USBPHY1>;
622 phy-3p0-supply = <®_3p0>;
623 fsl,anatop = <&anatop>;
626 usbphy2: usbphy@20ca000 {
627 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
628 reg = <0x020ca000 0x1000>;
629 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&clks IMX6UL_CLK_USBPHY2>;
631 phy-3p0-supply = <®_3p0>;
632 fsl,anatop = <&anatop>;
636 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
637 reg = <0x020cc000 0x4000>;
639 snvs_rtc: snvs-rtc-lp {
640 compatible = "fsl,sec-v4.0-mon-rtc-lp";
643 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
647 snvs_poweroff: snvs-poweroff {
648 compatible = "syscon-poweroff";
656 snvs_pwrkey: snvs-powerkey {
657 compatible = "fsl,sec-v4.0-pwrkey";
659 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
660 linux,keycode = <KEY_POWER>;
665 snvs_lpgpr: snvs-lpgpr {
666 compatible = "fsl,imx6ul-snvs-lpgpr";
670 epit1: epit@20d0000 {
671 reg = <0x020d0000 0x4000>;
672 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
675 epit2: epit@20d4000 {
676 reg = <0x020d4000 0x4000>;
677 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
680 src: reset-controller@20d8000 {
681 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
682 reg = <0x020d8000 0x4000>;
683 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
689 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
690 reg = <0x020dc000 0x4000>;
691 interrupt-controller;
692 #interrupt-cells = <3>;
693 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
694 interrupt-parent = <&intc>;
697 iomuxc: pinctrl@20e0000 {
698 compatible = "fsl,imx6ul-iomuxc";
699 reg = <0x020e0000 0x4000>;
702 gpr: iomuxc-gpr@20e4000 {
703 compatible = "fsl,imx6ul-iomuxc-gpr",
704 "fsl,imx6q-iomuxc-gpr", "syscon";
705 reg = <0x020e4000 0x4000>;
708 gpt2: timer@20e8000 {
709 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
710 reg = <0x020e8000 0x4000>;
711 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
713 <&clks IMX6UL_CLK_GPT2_SERIAL>;
714 clock-names = "ipg", "per";
719 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
721 reg = <0x020ec000 0x4000>;
722 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&clks IMX6UL_CLK_IPG>,
724 <&clks IMX6UL_CLK_SDMA>;
725 clock-names = "ipg", "ahb";
727 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
731 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
732 reg = <0x020f0000 0x4000>;
733 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clks IMX6UL_CLK_PWM5>,
735 <&clks IMX6UL_CLK_PWM5>;
736 clock-names = "ipg", "per";
742 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
743 reg = <0x020f4000 0x4000>;
744 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clks IMX6UL_CLK_PWM6>,
746 <&clks IMX6UL_CLK_PWM6>;
747 clock-names = "ipg", "per";
753 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
754 reg = <0x020f8000 0x4000>;
755 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clks IMX6UL_CLK_PWM7>,
757 <&clks IMX6UL_CLK_PWM7>;
758 clock-names = "ipg", "per";
764 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
765 reg = <0x020fc000 0x4000>;
766 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&clks IMX6UL_CLK_PWM8>,
768 <&clks IMX6UL_CLK_PWM8>;
769 clock-names = "ipg", "per";
776 compatible = "fsl,aips-bus", "simple-bus";
777 #address-cells = <1>;
779 reg = <0x02100000 0x100000>;
782 crypto: crypto@2140000 {
783 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
784 #address-cells = <1>;
786 reg = <0x2140000 0x3c000>;
787 ranges = <0 0x2140000 0x3c000>;
788 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
790 <&clks IMX6UL_CLK_CAAM_MEM>;
791 clock-names = "ipg", "aclk", "mem";
794 compatible = "fsl,sec-v4.0-job-ring";
795 reg = <0x1000 0x1000>;
796 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
800 compatible = "fsl,sec-v4.0-job-ring";
801 reg = <0x2000 0x1000>;
802 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
806 compatible = "fsl,sec-v4.0-job-ring";
807 reg = <0x3000 0x1000>;
808 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
812 usbotg1: usb@2184000 {
813 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
814 reg = <0x02184000 0x200>;
815 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clks IMX6UL_CLK_USBOH3>;
817 fsl,usbphy = <&usbphy1>;
818 fsl,usbmisc = <&usbmisc 0>;
819 fsl,anatop = <&anatop>;
820 ahb-burst-config = <0x0>;
821 tx-burst-size-dword = <0x10>;
822 rx-burst-size-dword = <0x10>;
826 usbotg2: usb@2184200 {
827 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
828 reg = <0x02184200 0x200>;
829 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&clks IMX6UL_CLK_USBOH3>;
831 fsl,usbphy = <&usbphy2>;
832 fsl,usbmisc = <&usbmisc 1>;
833 ahb-burst-config = <0x0>;
834 tx-burst-size-dword = <0x10>;
835 rx-burst-size-dword = <0x10>;
839 usbmisc: usbmisc@2184800 {
841 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
842 reg = <0x02184800 0x200>;
845 fec1: ethernet@2188000 {
846 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
847 reg = <0x02188000 0x4000>;
848 interrupt-names = "int0", "pps";
849 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6UL_CLK_ENET>,
852 <&clks IMX6UL_CLK_ENET_AHB>,
853 <&clks IMX6UL_CLK_ENET_PTP>,
854 <&clks IMX6UL_CLK_ENET_REF>,
855 <&clks IMX6UL_CLK_ENET_REF>;
856 clock-names = "ipg", "ahb", "ptp",
857 "enet_clk_ref", "enet_out";
858 fsl,num-tx-queues = <1>;
859 fsl,num-rx-queues = <1>;
860 fsl,stop-mode = <&gpr 0x10 3>;
864 usdhc1: usdhc@2190000 {
865 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
866 reg = <0x02190000 0x4000>;
867 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&clks IMX6UL_CLK_USDHC1>,
869 <&clks IMX6UL_CLK_USDHC1>,
870 <&clks IMX6UL_CLK_USDHC1>;
871 clock-names = "ipg", "ahb", "per";
872 fsl,tuning-step = <2>;
873 fsl,tuning-start-tap = <20>;
878 usdhc2: usdhc@2194000 {
879 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
880 reg = <0x02194000 0x4000>;
881 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clks IMX6UL_CLK_USDHC2>,
883 <&clks IMX6UL_CLK_USDHC2>,
884 <&clks IMX6UL_CLK_USDHC2>;
885 clock-names = "ipg", "ahb", "per";
887 fsl,tuning-step = <2>;
888 fsl,tuning-start-tap = <20>;
893 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
894 reg = <0x02198000 0x4000>;
895 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&clks IMX6UL_CLK_ADC1>;
899 fsl,adck-max-frequency = <30000000>, <40000000>,
905 #address-cells = <1>;
907 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
908 reg = <0x021a0000 0x4000>;
909 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&clks IMX6UL_CLK_I2C1>;
915 #address-cells = <1>;
917 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
918 reg = <0x021a4000 0x4000>;
919 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&clks IMX6UL_CLK_I2C2>;
925 #address-cells = <1>;
927 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
928 reg = <0x021a8000 0x4000>;
929 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&clks IMX6UL_CLK_I2C3>;
934 memory-controller@21b0000 {
935 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
936 reg = <0x021b0000 0x4000>;
937 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
941 #address-cells = <2>;
943 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
944 reg = <0x021b8000 0x4000>;
945 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clks IMX6UL_CLK_EIM>;
947 fsl,weim-cs-gpr = <&gpr>;
951 ocotp: ocotp-ctrl@21bc000 {
952 #address-cells = <1>;
954 compatible = "fsl,imx6ul-ocotp", "syscon";
955 reg = <0x021bc000 0x4000>;
956 clocks = <&clks IMX6UL_CLK_OCOTP>;
958 tempmon_calib: calib@38 {
962 tempmon_temp_grade: temp-grade@20 {
966 cpu_speed_grade: speed-grade@10 {
972 compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
973 reg = <0x021c4000 0x4000>;
974 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&clks IMX6UL_CLK_CSI>;
976 clock-names = "mclk";
980 lcdif: lcdif@21c8000 {
981 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
982 reg = <0x021c8000 0x4000>;
983 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
985 <&clks IMX6UL_CLK_LCDIF_APB>,
986 <&clks IMX6UL_CLK_DUMMY>;
987 clock-names = "pix", "axi", "disp_axi";
992 compatible = "fsl,imx6ul-pxp";
993 reg = <0x021cc000 0x4000>;
994 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&clks IMX6UL_CLK_PXP>;
1000 #address-cells = <1>;
1002 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
1003 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1004 reg-names = "QuadSPI", "QuadSPI-memory";
1005 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&clks IMX6UL_CLK_QSPI>,
1007 <&clks IMX6UL_CLK_QSPI>;
1008 clock-names = "qspi_en", "qspi";
1009 status = "disabled";
1012 wdog3: watchdog@21e4000 {
1013 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1014 reg = <0x021e4000 0x4000>;
1015 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&clks IMX6UL_CLK_WDOG3>;
1017 status = "disabled";
1020 uart2: serial@21e8000 {
1021 compatible = "fsl,imx6ul-uart",
1023 reg = <0x021e8000 0x4000>;
1024 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1025 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1026 <&clks IMX6UL_CLK_UART2_SERIAL>;
1027 clock-names = "ipg", "per";
1028 status = "disabled";
1031 uart3: serial@21ec000 {
1032 compatible = "fsl,imx6ul-uart",
1034 reg = <0x021ec000 0x4000>;
1035 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1037 <&clks IMX6UL_CLK_UART3_SERIAL>;
1038 clock-names = "ipg", "per";
1039 status = "disabled";
1042 uart4: serial@21f0000 {
1043 compatible = "fsl,imx6ul-uart",
1045 reg = <0x021f0000 0x4000>;
1046 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1048 <&clks IMX6UL_CLK_UART4_SERIAL>;
1049 clock-names = "ipg", "per";
1050 status = "disabled";
1053 uart5: serial@21f4000 {
1054 compatible = "fsl,imx6ul-uart",
1056 reg = <0x021f4000 0x4000>;
1057 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1058 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1059 <&clks IMX6UL_CLK_UART5_SERIAL>;
1060 clock-names = "ipg", "per";
1061 status = "disabled";
1065 #address-cells = <1>;
1067 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1068 reg = <0x021f8000 0x4000>;
1069 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clks IMX6UL_CLK_I2C4>;
1071 status = "disabled";
1074 uart6: serial@21fc000 {
1075 compatible = "fsl,imx6ul-uart",
1077 reg = <0x021fc000 0x4000>;
1078 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1080 <&clks IMX6UL_CLK_UART6_SERIAL>;
1081 clock-names = "ipg", "per";
1082 status = "disabled";