arch/arm/boot/dts/imx6ul-pico.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Copyright 2015 Technexion Ltd.
   4 //
   5 // Author: Wig Cheng  <wig.cheng@technexion.com>
   6 //         Richard Hu <richard.hu@technexion.com>
   7 //         Tapani Utriainen <tapani@technexion.com>
   8 /dts-v1/;
   9
  10 #include "imx6ul.dtsi"
  11
  12 / {
  13         /* Will be filled by the bootloader */
  14         memory@80000000 {
  15                 device_type = "memory";
  16                 reg = <0x80000000 0>;
  17         };
  18
  19         chosen {
  20                 stdout-path = &uart6;
  21         };
  22
  23         backlight: backlight {
  24                 compatible = "pwm-backlight";
  25                 pwms = <&pwm3 0 5000000>;
  26                 brightness-levels = <0 4 8 16 32 64 128 255>;
  27                 default-brightness-level = <6>;
  28                 status = "okay";
  29         };
  30
  31         reg_2p5v: regulator-2p5v {
  32                 compatible = "regulator-fixed";
  33                 regulator-name = "2P5V";
  34                 regulator-min-microvolt = <2500000>;
  35                 regulator-max-microvolt = <2500000>;
  36         };
  37
  38         reg_3p3v: regulator-3p3v {
  39                 compatible = "regulator-fixed";
  40                 regulator-name = "3P3V";
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43         };
  44
  45         reg_sd1_vmmc: regulator-sd1-vmmc {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "VSD_3V3";
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  51                 enable-active-high;
  52         };
  53
  54         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  55                 compatible = "regulator-fixed";
  56                 pinctrl-names = "default";
  57                 pinctrl-0 = <&pinctrl_usb_otg1>;
  58                 regulator-name = "usb_otg_vbus";
  59                 regulator-min-microvolt = <5000000>;
  60                 regulator-max-microvolt = <5000000>;
  61                 gpio = <&gpio1 6 0>;
  62         };
  63
  64         reg_brcm: regulator-brcm {
  65                 compatible = "regulator-fixed";
  66                 enable-active-high;
  67                 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&pinctrl_brcm_reg>;
  70                 regulator-name = "brcm_reg";
  71                 regulator-min-microvolt = <3300000>;
  72                 regulator-max-microvolt = <3300000>;
  73                 startup-delay-us = <200000>;
  74         };
  75
  76         panel {
  77                 compatible = "vxt,vl050-8048nt-c01";
  78                 backlight = <&backlight>;
  79
  80                 port {
  81                         panel_in: endpoint {
  82                                 remote-endpoint = <&display_out>;
  83                         };
  84                 };
  85         };
  86 };
  87
  88 &can1 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_flexcan1>;
  91         status = "okay";
  92 };
  93
  94 &can2 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_flexcan2>;
  97         status = "okay";
  98 };
  99
 100 &clks {
 101         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 102         assigned-clock-rates = <786432000>;
 103 };
 104
 105 &fec2 {
 106         pinctrl-names = "default";
 107         pinctrl-0 = <&pinctrl_enet2>;
 108         phy-mode = "rmii";
 109         phy-handle = <&ethphy1>;
 110         status = "okay";
 111         phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
 112         phy-reset-duration = <1>;
 113
 114         mdio {
 115                 #address-cells = <1>;
 116                 #size-cells = <0>;
 117
 118                 ethphy1: ethernet-phy@1 {
 119                         compatible = "ethernet-phy-ieee802.3-c22";
 120                         reg = <1>;
 121                         max-speed = <100>;
 122                         interrupt-parent = <&gpio5>;
 123                         interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
 124                 };
 125         };
 126 };
 127
 128 &i2c1 {
 129         clock-frequency = <100000>;
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_i2c1>;
 132         status = "okay";
 133
 134         pmic: pfuze3000@8 {
 135                 compatible = "fsl,pfuze3000";
 136                 reg = <0x08>;
 137
 138                 regulators {
 139                         /* VDD_ARM_SOC_IN*/
 140                         sw1b_reg: sw1b {
 141                                 regulator-min-microvolt = <700000>;
 142                                 regulator-max-microvolt = <1475000>;
 143                                 regulator-boot-on;
 144                                 regulator-always-on;
 145                                 regulator-ramp-delay = <6250>;
 146                         };
 147
 148                         /* DRAM */
 149                         sw3a_reg: sw3 {
 150                                 regulator-min-microvolt = <900000>;
 151                                 regulator-max-microvolt = <1650000>;
 152                                 regulator-boot-on;
 153                                 regulator-always-on;
 154                         };
 155
 156                         /* DRAM */
 157                         vref_reg: vrefddr {
 158                                 regulator-boot-on;
 159                                 regulator-always-on;
 160                         };
 161                 };
 162         };
 163 };
 164
 165 &lcdif {
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
 168         status = "okay";
 169
 170         port {
 171                 display_out: endpoint {
 172                         remote-endpoint = <&panel_in>;
 173                 };
 174         };
 175 };
 176
 177 &pwm3 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_pwm3>;
 180         status = "okay";
 181 };
 182
 183 &pwm7 {
 184         pinctrl-names = "default";
 185         pinctrl-0 = <&pinctrl_pwm7>;
 186         status = "okay";
 187 };
 188
 189 &pwm8 {
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_pwm8>;
 192         status = "okay";
 193 };
 194
 195 &sai1 {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_sai1>;
 198         status = "okay";
 199 };
 200
 201 &uart3 {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_uart3>;
 204         uart-has-rtscts;
 205         status = "okay";
 206 };
 207
 208 &uart6 {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_uart6>;
 211         status = "okay";
 212 };
 213
 214 &usbotg1 {
 215         vbus-supply = <&reg_usb_otg_vbus>;
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_usb_otg1_id>;
 218         dr_mode = "otg";
 219         disable-over-current;
 220         status = "okay";
 221 };
 222
 223 &usbotg2 {
 224         dr_mode = "host";
 225         disable-over-current;
 226         status = "okay";
 227 };
 228
 229 &usdhc1 {
 230         pinctrl-names = "default";
 231         pinctrl-0 = <&pinctrl_usdhc1>;
 232         bus-width = <8>;
 233         no-1-8-v;
 234         non-removable;
 235         keep-power-in-suspend;
 236         status = "okay";
 237 };
 238
 239 &usdhc2 {  /* Wifi SDIO */
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_usdhc2>;
 242         no-1-8-v;
 243         non-removable;
 244         keep-power-in-suspend;
 245         wakeup-source;
 246         vmmc-supply = <&reg_brcm>;
 247         status = "okay";
 248 };
 249
 250 &wdog1 {
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_wdog>;
 253         fsl,ext-reset-output;
 254 };
 255
 256 &iomuxc {
 257         pinctrl_brcm_reg: brcmreggrp {
 258                 fsl,pins = <
 259                         MX6UL_PAD_NAND_DATA06__GPIO4_IO08       0x10b0  /* WL_REG_ON */
 260                         MX6UL_PAD_NAND_DATA04__GPIO4_IO06       0x10b0  /* WL_HOST_WAKE */
 261                 >;
 262         };
 263
 264         pinctrl_enet2: enet2grp {
 265                 fsl,pins = <
 266                         MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO    0x1b0b0
 267                         MX6UL_PAD_ENET1_TX_EN__ENET2_MDC        0x1b0b0
 268                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 269                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 270                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 271                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 272                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 273                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 274                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 275                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 276                         MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06      0x800
 277                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28     0x79
 278                 >;
 279         };
 280
 281         pinctrl_flexcan1: flexcan1grp {
 282                 fsl,pins = <
 283                         MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX   0x1b020
 284                         MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX   0x1b020
 285                 >;
 286         };
 287
 288         pinctrl_flexcan2: flexcan2grp {
 289                 fsl,pins = <
 290                         MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX   0x1b020
 291                         MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX      0x1b020
 292                 >;
 293         };
 294
 295         pinctrl_i2c1: i2c1grp {
 296                 fsl,pins = <
 297                         MX6UL_PAD_GPIO1_IO02__I2C1_SCL          0x4001b8b0
 298                         MX6UL_PAD_GPIO1_IO03__I2C1_SDA          0x4001b8b0
 299                 >;
 300         };
 301
 302         pinctrl_i2c2: i2c2grp {
 303                 fsl,pins = <
 304                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL       0x4001b8b0
 305                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA       0x4001b8b0
 306                 >;
 307         };
 308
 309         pinctrl_i2c3: i2c3grp {
 310                 fsl,pins = <
 311                         MX6UL_PAD_UART1_TX_DATA__I2C3_SCL       0x4001b8b0
 312                         MX6UL_PAD_UART1_RX_DATA__I2C3_SDA       0x4001b8b0
 313                         >;
 314         };
 315
 316         pinctrl_lcdif_dat: lcdifdatgrp {
 317                 fsl,pins = <
 318                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00      0x79
 319                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01      0x79
 320                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x79
 321                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x79
 322                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x79
 323                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x79
 324                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x79
 325                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x79
 326                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08      0x79
 327                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09      0x79
 328                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x79
 329                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x79
 330                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x79
 331                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x79
 332                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x79
 333                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x79
 334                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16      0x79
 335                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17      0x79
 336                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x79
 337                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x79
 338                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x79
 339                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x79
 340                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x79
 341                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x79
 342                 >;
 343         };
 344
 345         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 346                 fsl,pins = <
 347                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x79
 348                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x79
 349                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x79
 350                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x79
 351                         /* LCD reset */
 352                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x79
 353                 >;
 354         };
 355
 356         pinctrl_pwm3: pwm3grp {
 357                 fsl,pins = <
 358                         MX6UL_PAD_NAND_ALE__PWM3_OUT            0x110b0
 359                 >;
 360         };
 361
 362         pinctrl_pwm7: pwm7grp {
 363                 fsl,pins = <
 364                         MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT        0x110b0
 365                 >;
 366         };
 367
 368         pinctrl_pwm8: pwm8grp {
 369                 fsl,pins = <
 370                         MX6UL_PAD_ENET1_RX_ER__PWM8_OUT         0x110b0
 371                 >;
 372         };
 373
 374         pinctrl_sai1: sai1grp {
 375                 fsl,pins = <
 376                         MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC      0x1b0b0
 377                         MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK      0x1b0b0
 378                         MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA      0x110b0
 379                         MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA      0x1f0b8
 380                 >;
 381         };
 382
 383         pinctrl_uart3: uart3grp {
 384                 fsl,pins = <
 385                         MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x1b0b0
 386                         MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x1b0b0
 387                         MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS    0x1b0b0
 388                         MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS    0x1b0b0
 389                 >;
 390         };
 391
 392         pinctrl_uart5: uart5grp {
 393                 fsl,pins = <
 394                         MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX      0x1b0b1
 395                         MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX      0x1b0b1
 396                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x1b0b1
 397                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x1b0b1
 398                 >;
 399         };
 400
 401         pinctrl_uart6: uart6grp {
 402                 fsl,pins = <
 403                         MX6UL_PAD_CSI_MCLK__UART6_DCE_TX        0x1b0b1
 404                         MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX      0x1b0b1
 405                 >;
 406         };
 407
 408         pinctrl_usb_otg1: usbotg1grp {
 409                 fsl,pins = <
 410                         MX6UL_PAD_GPIO1_IO06__GPIO1_IO06        0x10b0
 411                         >;
 412         };
 413
 414         pinctrl_usb_otg1_id: usbotg1idgrp {
 415                 fsl,pins = <
 416                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
 417                 >;
 418         };
 419
 420         pinctrl_usdhc1: usdhc1grp {
 421                 fsl,pins = <
 422                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 423                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10071
 424                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 425                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 426                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 427                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 428                         MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B      0x03029
 429                         MX6UL_PAD_NAND_READY_B__USDHC1_DATA4    0x17059
 430                         MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5      0x17059
 431                         MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6      0x17059
 432                         MX6UL_PAD_NAND_CLE__USDHC1_DATA7        0x17059
 433                 >;
 434         };
 435
 436         pinctrl_usdhc2: usdhc2grp {
 437                 fsl,pins = <
 438                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
 439                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x10059
 440                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x17059
 441                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x17059
 442                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x17059
 443                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x17059
 444                 >;
 445         };
 446
 447         pinctrl_wdog: wdoggrp {
 448                 fsl,pins = <
 449                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 450                 >;
 451         };
 452 };