1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
8 model = "Phytec phyBOARD-Segin i.MX6 UltraLite";
9 compatible = "phytec,imx6ul-pbacd-10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
16 reg_sound_1v8: regulator-1v8 {
17 compatible = "regulator-fixed";
18 regulator-name = "i2s-audio-1v8";
19 regulator-min-microvolt = <1800000>;
20 regulator-max-microvolt = <1800000>;
24 reg_sound_3v3: regulator-3v3 {
25 compatible = "regulator-fixed";
26 regulator-name = "i2s-audio-3v3";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
32 reg_can1_en: regulator-can1 {
33 compatible = "regulator-fixed";
34 pinctrl-names = "default";
35 pinctrl-0 = <&princtrl_flexcan1_en>;
36 regulator-name = "Can";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
39 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
44 reg_adc1_vref_3v3: regulator-vref-3v3 {
45 compatible = "regulator-fixed";
46 regulator-name = "vref-3v3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
52 compatible = "simple-audio-card";
53 simple-audio-card,name = "phyBOARD-Segin-TLV320AIC3007";
54 simple-audio-card,format = "i2s";
55 simple-audio-card,bitclock-master = <&dailink_master>;
56 simple-audio-card,frame-master = <&dailink_master>;
57 simple-audio-card,widgets =
61 simple-audio-card,routing =
70 simple-audio-card,cpu {
74 dailink_master: simple-audio-card,codec {
75 sound-dai = <&tlv320>;
76 clocks = <&clks IMX6UL_CLK_SAI2>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_adc1>;
85 vref-supply = <®_adc1_vref_3v3>;
87 * driver can not separate a specific channel so we request 4 channels
88 * here - we need only the fourth channel
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_flexcan1>;
97 xceiver-supply = <®_can1_en>;
102 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
103 assigned-clock-rates = <786432000>;
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_enet2>;
110 phy-handle = <ðphy1>;
116 compatible = "ti,tlv320aic3007";
117 #sound-dai-cells = <0>;
119 AVDD-supply = <®_sound_3v3>;
120 IOVDD-supply = <®_sound_3v3>;
121 DRVDD-supply = <®_sound_3v3>;
122 DVDD-supply = <®_sound_1v8>;
126 stmpe: touchscreen@44 {
127 compatible = "st,stmpe811";
129 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
130 interrupt-parent = <&gpio5>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_stmpe>;
136 compatible = "st,stmpe-ts";
137 st,sample-time = <4>;
142 st,touch-det-delay = <2>;
146 touchscreen-inverted-x = <1>;
147 touchscreen-inverted-y = <1>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_rtc_int>;
154 compatible = "microcrystal,rv4162";
156 interrupt-parent = <&gpio5>;
157 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
163 ethphy1: ethernet-phy@2 {
165 micrel,led-mode = <1>;
166 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
167 clock-names = "rmii-ref";
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_pwm3>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_sai2>;
180 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
181 <&clks IMX6UL_CLK_SAI2>;
182 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
183 assigned-clock-rates = <0>, <19200000>;
184 fsl,sai-mclk-direction-output;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_uart5>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_usb_otg1_id>;
204 disable-over-current;
209 pinctrl-names = "default", "state_100mhz", "state_200mhz";
210 pinctrl-0 = <&pinctrl_usdhc1>;
211 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
212 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
213 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
215 keep-power-in-suspend;
221 pinctrl_adc1: adc1grp {
223 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
227 pinctrl_enet2: enet2grp {
229 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
230 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
231 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
232 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
233 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
234 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
235 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
236 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
240 pinctrl_flexcan1: flexcan1 {
242 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
243 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
247 princtrl_flexcan1_en: flexcan1engrp {
249 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
253 pinctrl_pwm3: pwm3grp {
255 MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
259 pinctrl_rtc_int: rtcintgrp {
261 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
265 pinctrl_sai2: sai2grp {
267 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
268 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
269 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
270 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
271 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
275 pinctrl_stmpe: stmpegrp {
277 MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
281 pinctrl_uart5: uart5grp {
283 MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
284 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
285 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
286 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
290 pinctrl_usb_otg1_id: usbotg1idgrp {
292 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
296 pinctrl_usdhc1: usdhc1grp {
298 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
299 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
300 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
301 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
302 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
303 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
304 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
308 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
310 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
311 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
312 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
313 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
314 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
315 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
319 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
321 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
322 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
323 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
324 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
325 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
326 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9