1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2014 Freescale Semiconductor, Inc.
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
61 compatible = "arm,cortex-a9";
64 next-level-cache = <&L2>;
72 fsl,soc-operating-points = <
79 clock-latency = <61036>; /* two CLK32 periods */
81 clocks = <&clks IMX6SX_CLK_ARM>,
82 <&clks IMX6SX_CLK_PLL2_PFD2>,
83 <&clks IMX6SX_CLK_STEP>,
84 <&clks IMX6SX_CLK_PLL1_SW>,
85 <&clks IMX6SX_CLK_PLL1_SYS>;
86 clock-names = "arm", "pll2_pfd2_396m", "step",
87 "pll1_sw", "pll1_sys";
88 arm-supply = <®_arm>;
89 soc-supply = <®_soc>;
90 nvmem-cells = <&cpu_speed_grade>;
91 nvmem-cell-names = "speed_grade";
96 compatible = "fixed-clock";
98 clock-frequency = <32768>;
99 clock-output-names = "ckil";
103 compatible = "fixed-clock";
105 clock-frequency = <24000000>;
106 clock-output-names = "osc";
109 ipp_di0: clock-ipp-di0 {
110 compatible = "fixed-clock";
112 clock-frequency = <0>;
113 clock-output-names = "ipp_di0";
116 ipp_di1: clock-ipp-di1 {
117 compatible = "fixed-clock";
119 clock-frequency = <0>;
120 clock-output-names = "ipp_di1";
123 anaclk1: clock-anaclk1 {
124 compatible = "fixed-clock";
126 clock-frequency = <0>;
127 clock-output-names = "anaclk1";
130 anaclk2: clock-anaclk2 {
131 compatible = "fixed-clock";
133 clock-frequency = <0>;
134 clock-output-names = "anaclk2";
138 compatible = "fsl,imx6sx-mqs";
144 compatible = "arm,cortex-a9-pmu";
145 interrupt-parent = <&gpc>;
146 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
149 usbphynop1: usbphynop1 {
150 compatible = "usb-nop-xceiv";
155 #address-cells = <1>;
157 compatible = "simple-bus";
158 interrupt-parent = <&gpc>;
161 ocram_s: sram@8f8000 {
162 compatible = "mmio-sram";
163 reg = <0x008f8000 0x4000>;
164 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
168 compatible = "mmio-sram";
169 reg = <0x00900000 0x20000>;
170 clocks = <&clks IMX6SX_CLK_OCRAM>;
173 intc: interrupt-controller@a01000 {
174 compatible = "arm,cortex-a9-gic";
175 #interrupt-cells = <3>;
176 interrupt-controller;
177 reg = <0x00a01000 0x1000>,
179 interrupt-parent = <&intc>;
182 L2: cache-controller@a02000 {
183 compatible = "arm,pl310-cache";
184 reg = <0x00a02000 0x1000>;
185 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
188 arm,tag-latency = <4 2 3>;
189 arm,data-latency = <4 2 3>;
193 compatible = "vivante,gc";
194 reg = <0x01800000 0x4000>;
195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&clks IMX6SX_CLK_GPU>,
197 <&clks IMX6SX_CLK_GPU>,
198 <&clks IMX6SX_CLK_GPU>;
199 clock-names = "bus", "core", "shader";
200 power-domains = <&pd_pu>;
203 dma_apbh: dma-apbh@1804000 {
204 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
205 reg = <0x01804000 0x2000>;
206 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
210 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
213 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
216 gpmi: gpmi-nand@1806000{
217 compatible = "fsl,imx6sx-gpmi-nand";
218 #address-cells = <1>;
220 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
221 reg-names = "gpmi-nand", "bch";
222 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "bch";
224 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
225 <&clks IMX6SX_CLK_GPMI_APB>,
226 <&clks IMX6SX_CLK_GPMI_BCH>,
227 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
228 <&clks IMX6SX_CLK_PER1_BCH>;
229 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
230 "gpmi_bch_apb", "per1_bch";
231 dmas = <&dma_apbh 0>;
237 compatible = "fsl,aips-bus", "simple-bus";
238 #address-cells = <1>;
240 reg = <0x02000000 0x100000>;
244 compatible = "fsl,spba-bus", "simple-bus";
245 #address-cells = <1>;
247 reg = <0x02000000 0x40000>;
250 spdif: spdif@2004000 {
251 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
252 reg = <0x02004000 0x4000>;
253 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
254 dmas = <&sdma 14 18 0>,
256 dma-names = "rx", "tx";
257 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
258 <&clks IMX6SX_CLK_OSC>,
259 <&clks IMX6SX_CLK_SPDIF>,
260 <&clks 0>, <&clks 0>, <&clks 0>,
261 <&clks IMX6SX_CLK_IPG>,
262 <&clks 0>, <&clks 0>,
263 <&clks IMX6SX_CLK_SPBA>;
264 clock-names = "core", "rxtx0",
272 ecspi1: spi@2008000 {
273 #address-cells = <1>;
275 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
276 reg = <0x02008000 0x4000>;
277 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&clks IMX6SX_CLK_ECSPI1>,
279 <&clks IMX6SX_CLK_ECSPI1>;
280 clock-names = "ipg", "per";
284 ecspi2: spi@200c000 {
285 #address-cells = <1>;
287 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
288 reg = <0x0200c000 0x4000>;
289 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6SX_CLK_ECSPI2>,
291 <&clks IMX6SX_CLK_ECSPI2>;
292 clock-names = "ipg", "per";
296 ecspi3: spi@2010000 {
297 #address-cells = <1>;
299 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
300 reg = <0x02010000 0x4000>;
301 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&clks IMX6SX_CLK_ECSPI3>,
303 <&clks IMX6SX_CLK_ECSPI3>;
304 clock-names = "ipg", "per";
308 ecspi4: spi@2014000 {
309 #address-cells = <1>;
311 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
312 reg = <0x02014000 0x4000>;
313 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clks IMX6SX_CLK_ECSPI4>,
315 <&clks IMX6SX_CLK_ECSPI4>;
316 clock-names = "ipg", "per";
320 uart1: serial@2020000 {
321 compatible = "fsl,imx6sx-uart",
322 "fsl,imx6q-uart", "fsl,imx21-uart";
323 reg = <0x02020000 0x4000>;
324 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&clks IMX6SX_CLK_UART_IPG>,
326 <&clks IMX6SX_CLK_UART_SERIAL>;
327 clock-names = "ipg", "per";
328 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
329 dma-names = "rx", "tx";
334 compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
335 reg = <0x02024000 0x4000>;
336 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
338 <&clks IMX6SX_CLK_ESAI_MEM>,
339 <&clks IMX6SX_CLK_ESAI_EXTAL>,
340 <&clks IMX6SX_CLK_ESAI_IPG>,
341 <&clks IMX6SX_CLK_SPBA>;
342 clock-names = "core", "mem", "extal",
344 dmas = <&sdma 23 21 0>,
346 dma-names = "rx", "tx";
351 #sound-dai-cells = <0>;
352 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
353 reg = <0x02028000 0x4000>;
354 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
356 <&clks IMX6SX_CLK_SSI1>;
357 clock-names = "ipg", "baud";
358 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
359 dma-names = "rx", "tx";
360 fsl,fifo-depth = <15>;
365 #sound-dai-cells = <0>;
366 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
367 reg = <0x0202c000 0x4000>;
368 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
370 <&clks IMX6SX_CLK_SSI2>;
371 clock-names = "ipg", "baud";
372 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
373 dma-names = "rx", "tx";
374 fsl,fifo-depth = <15>;
379 #sound-dai-cells = <0>;
380 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
381 reg = <0x02030000 0x4000>;
382 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
384 <&clks IMX6SX_CLK_SSI3>;
385 clock-names = "ipg", "baud";
386 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
387 dma-names = "rx", "tx";
388 fsl,fifo-depth = <15>;
393 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
394 reg = <0x02034000 0x4000>;
395 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
397 <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
398 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
399 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
400 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
401 <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
402 <&clks IMX6SX_CLK_SPBA>;
403 clock-names = "mem", "ipg", "asrck_0",
404 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
405 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
406 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
407 "asrck_d", "asrck_e", "asrck_f", "spba";
408 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
409 <&sdma 19 23 1>, <&sdma 20 23 1>,
410 <&sdma 21 23 1>, <&sdma 22 23 1>;
411 dma-names = "rxa", "rxb", "rxc",
413 fsl,asrc-rate = <48000>;
414 fsl,asrc-width = <16>;
420 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
421 reg = <0x02080000 0x4000>;
422 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&clks IMX6SX_CLK_PWM1>,
424 <&clks IMX6SX_CLK_PWM1>;
425 clock-names = "ipg", "per";
430 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
431 reg = <0x02084000 0x4000>;
432 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&clks IMX6SX_CLK_PWM2>,
434 <&clks IMX6SX_CLK_PWM2>;
435 clock-names = "ipg", "per";
440 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
441 reg = <0x02088000 0x4000>;
442 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX6SX_CLK_PWM3>,
444 <&clks IMX6SX_CLK_PWM3>;
445 clock-names = "ipg", "per";
450 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
451 reg = <0x0208c000 0x4000>;
452 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clks IMX6SX_CLK_PWM4>,
454 <&clks IMX6SX_CLK_PWM4>;
455 clock-names = "ipg", "per";
459 flexcan1: can@2090000 {
460 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
461 reg = <0x02090000 0x4000>;
462 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
464 <&clks IMX6SX_CLK_CAN1_SERIAL>;
465 clock-names = "ipg", "per";
466 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
470 flexcan2: can@2094000 {
471 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
472 reg = <0x02094000 0x4000>;
473 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
475 <&clks IMX6SX_CLK_CAN2_SERIAL>;
476 clock-names = "ipg", "per";
477 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
482 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
483 reg = <0x02098000 0x4000>;
484 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
486 <&clks IMX6SX_CLK_GPT_3M>;
487 clock-names = "ipg", "per";
490 gpio1: gpio@209c000 {
491 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
492 reg = <0x0209c000 0x4000>;
493 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 gpio-ranges = <&iomuxc 0 5 26>;
502 gpio2: gpio@20a0000 {
503 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
504 reg = <0x020a0000 0x4000>;
505 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 gpio-ranges = <&iomuxc 0 31 20>;
514 gpio3: gpio@20a4000 {
515 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
516 reg = <0x020a4000 0x4000>;
517 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 gpio-ranges = <&iomuxc 0 51 29>;
526 gpio4: gpio@20a8000 {
527 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
528 reg = <0x020a8000 0x4000>;
529 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 gpio-ranges = <&iomuxc 0 80 32>;
538 gpio5: gpio@20ac000 {
539 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
540 reg = <0x020ac000 0x4000>;
541 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 gpio-ranges = <&iomuxc 0 112 24>;
550 gpio6: gpio@20b0000 {
551 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
552 reg = <0x020b0000 0x4000>;
553 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-controller;
558 #interrupt-cells = <2>;
559 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
562 gpio7: gpio@20b4000 {
563 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
564 reg = <0x020b4000 0x4000>;
565 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
571 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
574 kpp: keypad@20b8000 {
575 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
576 reg = <0x020b8000 0x4000>;
577 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clks IMX6SX_CLK_IPG>;
582 wdog1: watchdog@20bc000 {
583 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
584 reg = <0x020bc000 0x4000>;
585 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&clks IMX6SX_CLK_IPG>;
589 wdog2: watchdog@20c0000 {
590 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
591 reg = <0x020c0000 0x4000>;
592 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clks IMX6SX_CLK_IPG>;
597 clks: clock-controller@20c4000 {
598 compatible = "fsl,imx6sx-ccm";
599 reg = <0x020c4000 0x4000>;
600 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
604 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
607 anatop: anatop@20c8000 {
608 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
609 "syscon", "simple-mfd";
610 reg = <0x020c8000 0x1000>;
611 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
615 reg_vdd1p1: regulator-1p1 {
616 compatible = "fsl,anatop-regulator";
617 regulator-name = "vdd1p1";
618 regulator-min-microvolt = <1000000>;
619 regulator-max-microvolt = <1200000>;
621 anatop-reg-offset = <0x110>;
622 anatop-vol-bit-shift = <8>;
623 anatop-vol-bit-width = <5>;
624 anatop-min-bit-val = <4>;
625 anatop-min-voltage = <800000>;
626 anatop-max-voltage = <1375000>;
627 anatop-enable-bit = <0>;
630 reg_vdd3p0: regulator-3p0 {
631 compatible = "fsl,anatop-regulator";
632 regulator-name = "vdd3p0";
633 regulator-min-microvolt = <2800000>;
634 regulator-max-microvolt = <3150000>;
636 anatop-reg-offset = <0x120>;
637 anatop-vol-bit-shift = <8>;
638 anatop-vol-bit-width = <5>;
639 anatop-min-bit-val = <0>;
640 anatop-min-voltage = <2625000>;
641 anatop-max-voltage = <3400000>;
642 anatop-enable-bit = <0>;
645 reg_vdd2p5: regulator-2p5 {
646 compatible = "fsl,anatop-regulator";
647 regulator-name = "vdd2p5";
648 regulator-min-microvolt = <2250000>;
649 regulator-max-microvolt = <2750000>;
651 anatop-reg-offset = <0x130>;
652 anatop-vol-bit-shift = <8>;
653 anatop-vol-bit-width = <5>;
654 anatop-min-bit-val = <0>;
655 anatop-min-voltage = <2100000>;
656 anatop-max-voltage = <2875000>;
657 anatop-enable-bit = <0>;
660 reg_arm: regulator-vddcore {
661 compatible = "fsl,anatop-regulator";
662 regulator-name = "vddarm";
663 regulator-min-microvolt = <725000>;
664 regulator-max-microvolt = <1450000>;
666 anatop-reg-offset = <0x140>;
667 anatop-vol-bit-shift = <0>;
668 anatop-vol-bit-width = <5>;
669 anatop-delay-reg-offset = <0x170>;
670 anatop-delay-bit-shift = <24>;
671 anatop-delay-bit-width = <2>;
672 anatop-min-bit-val = <1>;
673 anatop-min-voltage = <725000>;
674 anatop-max-voltage = <1450000>;
677 reg_pcie: regulator-vddpcie {
678 compatible = "fsl,anatop-regulator";
679 regulator-name = "vddpcie";
680 regulator-min-microvolt = <725000>;
681 regulator-max-microvolt = <1450000>;
682 anatop-reg-offset = <0x140>;
683 anatop-vol-bit-shift = <9>;
684 anatop-vol-bit-width = <5>;
685 anatop-delay-reg-offset = <0x170>;
686 anatop-delay-bit-shift = <26>;
687 anatop-delay-bit-width = <2>;
688 anatop-min-bit-val = <1>;
689 anatop-min-voltage = <725000>;
690 anatop-max-voltage = <1450000>;
693 reg_soc: regulator-vddsoc {
694 compatible = "fsl,anatop-regulator";
695 regulator-name = "vddsoc";
696 regulator-min-microvolt = <725000>;
697 regulator-max-microvolt = <1450000>;
699 anatop-reg-offset = <0x140>;
700 anatop-vol-bit-shift = <18>;
701 anatop-vol-bit-width = <5>;
702 anatop-delay-reg-offset = <0x170>;
703 anatop-delay-bit-shift = <28>;
704 anatop-delay-bit-width = <2>;
705 anatop-min-bit-val = <1>;
706 anatop-min-voltage = <725000>;
707 anatop-max-voltage = <1450000>;
711 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
712 interrupt-parent = <&gpc>;
713 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
714 fsl,tempmon = <&anatop>;
715 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
716 nvmem-cell-names = "calib", "temp_grade";
717 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
721 usbphy1: usbphy@20c9000 {
722 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
723 reg = <0x020c9000 0x1000>;
724 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clks IMX6SX_CLK_USBPHY1>;
726 fsl,anatop = <&anatop>;
729 usbphy2: usbphy@20ca000 {
730 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
731 reg = <0x020ca000 0x1000>;
732 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clks IMX6SX_CLK_USBPHY2>;
734 fsl,anatop = <&anatop>;
738 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
739 reg = <0x020cc000 0x4000>;
741 snvs_rtc: snvs-rtc-lp {
742 compatible = "fsl,sec-v4.0-mon-rtc-lp";
745 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
748 snvs_poweroff: snvs-poweroff {
749 compatible = "syscon-poweroff";
757 snvs_pwrkey: snvs-powerkey {
758 compatible = "fsl,sec-v4.0-pwrkey";
760 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
761 linux,keycode = <KEY_POWER>;
767 epit1: epit@20d0000 {
768 reg = <0x020d0000 0x4000>;
769 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
772 epit2: epit@20d4000 {
773 reg = <0x020d4000 0x4000>;
774 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
777 src: reset-controller@20d8000 {
778 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
779 reg = <0x020d8000 0x4000>;
780 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
786 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
787 reg = <0x020dc000 0x4000>;
788 interrupt-controller;
789 #interrupt-cells = <3>;
790 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
791 interrupt-parent = <&intc>;
792 clocks = <&clks IMX6SX_CLK_IPG>;
796 #address-cells = <1>;
801 #power-domain-cells = <0>;
804 pd_pu: power-domain@1 {
806 #power-domain-cells = <0>;
807 power-supply = <®_soc>;
808 clocks = <&clks IMX6SX_CLK_GPU>;
811 pd_disp: power-domain@2 {
813 #power-domain-cells = <0>;
814 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
815 <&clks IMX6SX_CLK_DISPLAY_AXI>,
816 <&clks IMX6SX_CLK_LCDIF1_PIX>,
817 <&clks IMX6SX_CLK_LCDIF_APB>,
818 <&clks IMX6SX_CLK_LCDIF2_PIX>,
819 <&clks IMX6SX_CLK_CSI>,
820 <&clks IMX6SX_CLK_VADC>;
823 pd_pci: power-domain@3 {
825 #power-domain-cells = <0>;
826 power-supply = <®_pcie>;
831 iomuxc: pinctrl@20e0000 {
832 compatible = "fsl,imx6sx-iomuxc";
833 reg = <0x020e0000 0x4000>;
836 gpr: iomuxc-gpr@20e4000 {
837 compatible = "fsl,imx6sx-iomuxc-gpr",
838 "fsl,imx6q-iomuxc-gpr", "syscon";
839 reg = <0x020e4000 0x4000>;
843 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
844 reg = <0x020ec000 0x4000>;
845 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&clks IMX6SX_CLK_IPG>,
847 <&clks IMX6SX_CLK_SDMA>;
848 clock-names = "ipg", "ahb";
850 /* imx6sx reuses imx6q sdma firmware */
851 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
856 compatible = "fsl,aips-bus", "simple-bus";
857 #address-cells = <1>;
859 reg = <0x02100000 0x100000>;
862 crypto: crypto@2100000 {
863 compatible = "fsl,sec-v4.0";
864 #address-cells = <1>;
866 reg = <0x2100000 0x10000>;
867 ranges = <0 0x2100000 0x10000>;
868 interrupt-parent = <&intc>;
869 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
870 <&clks IMX6SX_CLK_CAAM_ACLK>,
871 <&clks IMX6SX_CLK_CAAM_IPG>,
872 <&clks IMX6SX_CLK_EIM_SLOW>;
873 clock-names = "mem", "aclk", "ipg", "emi_slow";
876 compatible = "fsl,sec-v4.0-job-ring";
877 reg = <0x1000 0x1000>;
878 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
882 compatible = "fsl,sec-v4.0-job-ring";
883 reg = <0x2000 0x1000>;
884 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
888 usbotg1: usb@2184000 {
889 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
890 reg = <0x02184000 0x200>;
891 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&clks IMX6SX_CLK_USBOH3>;
893 fsl,usbphy = <&usbphy1>;
894 fsl,usbmisc = <&usbmisc 0>;
895 fsl,anatop = <&anatop>;
896 ahb-burst-config = <0x0>;
897 tx-burst-size-dword = <0x10>;
898 rx-burst-size-dword = <0x10>;
902 usbotg2: usb@2184200 {
903 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
904 reg = <0x02184200 0x200>;
905 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&clks IMX6SX_CLK_USBOH3>;
907 fsl,usbphy = <&usbphy2>;
908 fsl,usbmisc = <&usbmisc 1>;
909 ahb-burst-config = <0x0>;
910 tx-burst-size-dword = <0x10>;
911 rx-burst-size-dword = <0x10>;
916 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
917 reg = <0x02184400 0x200>;
918 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&clks IMX6SX_CLK_USBOH3>;
920 fsl,usbphy = <&usbphynop1>;
921 fsl,usbmisc = <&usbmisc 2>;
923 fsl,anatop = <&anatop>;
925 ahb-burst-config = <0x0>;
926 tx-burst-size-dword = <0x10>;
927 rx-burst-size-dword = <0x10>;
931 usbmisc: usbmisc@2184800 {
933 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
934 reg = <0x02184800 0x200>;
935 clocks = <&clks IMX6SX_CLK_USBOH3>;
938 fec1: ethernet@2188000 {
939 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
940 reg = <0x02188000 0x4000>;
941 interrupt-names = "int0", "pps";
942 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
944 clocks = <&clks IMX6SX_CLK_ENET>,
945 <&clks IMX6SX_CLK_ENET_AHB>,
946 <&clks IMX6SX_CLK_ENET_PTP>,
947 <&clks IMX6SX_CLK_ENET_REF>,
948 <&clks IMX6SX_CLK_ENET_PTP>;
949 clock-names = "ipg", "ahb", "ptp",
950 "enet_clk_ref", "enet_out";
951 fsl,num-tx-queues = <3>;
952 fsl,num-rx-queues = <3>;
953 fsl,stop-mode = <&gpr 0x10 3>;
958 reg = <0x0218c000 0x4000>;
959 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&clks IMX6SX_CLK_MLB>;
966 usdhc1: mmc@2190000 {
967 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
968 reg = <0x02190000 0x4000>;
969 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&clks IMX6SX_CLK_USDHC1>,
971 <&clks IMX6SX_CLK_USDHC1>,
972 <&clks IMX6SX_CLK_USDHC1>;
973 clock-names = "ipg", "ahb", "per";
978 usdhc2: mmc@2194000 {
979 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
980 reg = <0x02194000 0x4000>;
981 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&clks IMX6SX_CLK_USDHC2>,
983 <&clks IMX6SX_CLK_USDHC2>,
984 <&clks IMX6SX_CLK_USDHC2>;
985 clock-names = "ipg", "ahb", "per";
990 usdhc3: mmc@2198000 {
991 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
992 reg = <0x02198000 0x4000>;
993 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&clks IMX6SX_CLK_USDHC3>,
995 <&clks IMX6SX_CLK_USDHC3>,
996 <&clks IMX6SX_CLK_USDHC3>;
997 clock-names = "ipg", "ahb", "per";
1002 usdhc4: mmc@219c000 {
1003 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1004 reg = <0x0219c000 0x4000>;
1005 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&clks IMX6SX_CLK_USDHC4>,
1007 <&clks IMX6SX_CLK_USDHC4>,
1008 <&clks IMX6SX_CLK_USDHC4>;
1009 clock-names = "ipg", "ahb", "per";
1011 status = "disabled";
1015 #address-cells = <1>;
1017 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1018 reg = <0x021a0000 0x4000>;
1019 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&clks IMX6SX_CLK_I2C1>;
1021 status = "disabled";
1025 #address-cells = <1>;
1027 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1028 reg = <0x021a4000 0x4000>;
1029 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&clks IMX6SX_CLK_I2C2>;
1031 status = "disabled";
1035 #address-cells = <1>;
1037 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1038 reg = <0x021a8000 0x4000>;
1039 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&clks IMX6SX_CLK_I2C3>;
1041 status = "disabled";
1044 memory-controller@21b0000 {
1045 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1046 reg = <0x021b0000 0x4000>;
1047 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1050 fec2: ethernet@21b4000 {
1051 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1052 reg = <0x021b4000 0x4000>;
1053 interrupt-names = "int0", "pps";
1054 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&clks IMX6SX_CLK_ENET>,
1057 <&clks IMX6SX_CLK_ENET_AHB>,
1058 <&clks IMX6SX_CLK_ENET_PTP>,
1059 <&clks IMX6SX_CLK_ENET2_REF_125M>,
1060 <&clks IMX6SX_CLK_ENET_PTP>;
1061 clock-names = "ipg", "ahb", "ptp",
1062 "enet_clk_ref", "enet_out";
1063 fsl,stop-mode = <&gpr 0x10 4>;
1064 status = "disabled";
1067 weim: weim@21b8000 {
1068 #address-cells = <2>;
1070 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1071 reg = <0x021b8000 0x4000>;
1072 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1074 fsl,weim-cs-gpr = <&gpr>;
1075 status = "disabled";
1078 ocotp: efuse@21bc000 {
1079 #address-cells = <1>;
1081 compatible = "fsl,imx6sx-ocotp", "syscon";
1082 reg = <0x021bc000 0x4000>;
1083 clocks = <&clks IMX6SX_CLK_OCOTP>;
1085 cpu_speed_grade: speed-grade@10 {
1089 tempmon_calib: calib@38 {
1093 tempmon_temp_grade: temp-grade@20 {
1099 compatible = "fsl,imx6sx-sai";
1100 reg = <0x021d4000 0x4000>;
1101 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1102 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1103 <&clks IMX6SX_CLK_SAI1>,
1104 <&clks 0>, <&clks 0>;
1105 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1106 dma-names = "rx", "tx";
1107 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1108 status = "disabled";
1111 audmux: audmux@21d8000 {
1112 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1113 reg = <0x021d8000 0x4000>;
1114 status = "disabled";
1118 compatible = "fsl,imx6sx-sai";
1119 reg = <0x021dc000 0x4000>;
1120 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1122 <&clks IMX6SX_CLK_SAI2>,
1123 <&clks 0>, <&clks 0>;
1124 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1125 dma-names = "rx", "tx";
1126 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1127 status = "disabled";
1130 qspi1: spi@21e0000 {
1131 #address-cells = <1>;
1133 compatible = "fsl,imx6sx-qspi";
1134 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1135 reg-names = "QuadSPI", "QuadSPI-memory";
1136 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1137 clocks = <&clks IMX6SX_CLK_QSPI1>,
1138 <&clks IMX6SX_CLK_QSPI1>;
1139 clock-names = "qspi_en", "qspi";
1140 status = "disabled";
1143 qspi2: spi@21e4000 {
1144 #address-cells = <1>;
1146 compatible = "fsl,imx6sx-qspi";
1147 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1148 reg-names = "QuadSPI", "QuadSPI-memory";
1149 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&clks IMX6SX_CLK_QSPI2>,
1151 <&clks IMX6SX_CLK_QSPI2>;
1152 clock-names = "qspi_en", "qspi";
1153 status = "disabled";
1156 uart2: serial@21e8000 {
1157 compatible = "fsl,imx6sx-uart",
1158 "fsl,imx6q-uart", "fsl,imx21-uart";
1159 reg = <0x021e8000 0x4000>;
1160 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1162 <&clks IMX6SX_CLK_UART_SERIAL>;
1163 clock-names = "ipg", "per";
1164 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1165 dma-names = "rx", "tx";
1166 status = "disabled";
1169 uart3: serial@21ec000 {
1170 compatible = "fsl,imx6sx-uart",
1171 "fsl,imx6q-uart", "fsl,imx21-uart";
1172 reg = <0x021ec000 0x4000>;
1173 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1174 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1175 <&clks IMX6SX_CLK_UART_SERIAL>;
1176 clock-names = "ipg", "per";
1177 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1178 dma-names = "rx", "tx";
1179 status = "disabled";
1182 uart4: serial@21f0000 {
1183 compatible = "fsl,imx6sx-uart",
1184 "fsl,imx6q-uart", "fsl,imx21-uart";
1185 reg = <0x021f0000 0x4000>;
1186 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1187 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1188 <&clks IMX6SX_CLK_UART_SERIAL>;
1189 clock-names = "ipg", "per";
1190 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1191 dma-names = "rx", "tx";
1192 status = "disabled";
1195 uart5: serial@21f4000 {
1196 compatible = "fsl,imx6sx-uart",
1197 "fsl,imx6q-uart", "fsl,imx21-uart";
1198 reg = <0x021f4000 0x4000>;
1199 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1200 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1201 <&clks IMX6SX_CLK_UART_SERIAL>;
1202 clock-names = "ipg", "per";
1203 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1204 dma-names = "rx", "tx";
1205 status = "disabled";
1209 #address-cells = <1>;
1211 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1212 reg = <0x021f8000 0x4000>;
1213 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&clks IMX6SX_CLK_I2C4>;
1215 status = "disabled";
1219 aips3: bus@2200000 {
1220 compatible = "fsl,aips-bus", "simple-bus";
1221 #address-cells = <1>;
1223 reg = <0x02200000 0x100000>;
1227 compatible = "fsl,spba-bus", "simple-bus";
1228 #address-cells = <1>;
1230 reg = <0x02240000 0x40000>;
1234 reg = <0x02214000 0x4000>;
1235 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1237 <&clks IMX6SX_CLK_CSI>,
1238 <&clks IMX6SX_CLK_DCIC1>;
1239 clock-names = "disp-axi", "csi_mclk", "dcic";
1240 status = "disabled";
1244 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1245 reg = <0x02218000 0x4000>;
1246 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1248 clock-names = "axi";
1249 power-domains = <&pd_disp>;
1250 status = "disabled";
1254 reg = <0x0221c000 0x4000>;
1255 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1257 <&clks IMX6SX_CLK_CSI>,
1258 <&clks IMX6SX_CLK_DCIC2>;
1259 clock-names = "disp-axi", "csi_mclk", "dcic";
1260 status = "disabled";
1263 lcdif1: lcdif@2220000 {
1264 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1265 reg = <0x02220000 0x4000>;
1266 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1267 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1268 <&clks IMX6SX_CLK_LCDIF_APB>,
1269 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1270 clock-names = "pix", "axi", "disp_axi";
1271 power-domains = <&pd_disp>;
1272 status = "disabled";
1275 lcdif2: lcdif@2224000 {
1276 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1277 reg = <0x02224000 0x4000>;
1278 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1279 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1280 <&clks IMX6SX_CLK_LCDIF_APB>,
1281 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1282 clock-names = "pix", "axi", "disp_axi";
1283 power-domains = <&pd_disp>;
1284 status = "disabled";
1287 vadc: vadc@2228000 {
1288 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1289 reg-names = "vadc-vafe", "vadc-vdec";
1290 clocks = <&clks IMX6SX_CLK_VADC>,
1291 <&clks IMX6SX_CLK_CSI>;
1292 clock-names = "vadc", "csi";
1293 power-domains = <&pd_disp>;
1294 status = "disabled";
1299 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1300 reg = <0x02280000 0x4000>;
1301 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&clks IMX6SX_CLK_IPG>;
1303 clock-names = "adc";
1304 fsl,adck-max-frequency = <30000000>, <40000000>,
1306 status = "disabled";
1310 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1311 reg = <0x02284000 0x4000>;
1312 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1313 clocks = <&clks IMX6SX_CLK_IPG>;
1314 clock-names = "adc";
1315 fsl,adck-max-frequency = <30000000>, <40000000>,
1317 status = "disabled";
1320 wdog3: watchdog@2288000 {
1321 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1322 reg = <0x02288000 0x4000>;
1323 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1324 clocks = <&clks IMX6SX_CLK_IPG>;
1325 status = "disabled";
1328 ecspi5: spi@228c000 {
1329 #address-cells = <1>;
1331 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1332 reg = <0x0228c000 0x4000>;
1333 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1334 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1335 <&clks IMX6SX_CLK_ECSPI5>;
1336 clock-names = "ipg", "per";
1337 status = "disabled";
1340 uart6: serial@22a0000 {
1341 compatible = "fsl,imx6sx-uart",
1342 "fsl,imx6q-uart", "fsl,imx21-uart";
1343 reg = <0x022a0000 0x4000>;
1344 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1346 <&clks IMX6SX_CLK_UART_SERIAL>;
1347 clock-names = "ipg", "per";
1348 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1349 dma-names = "rx", "tx";
1350 status = "disabled";
1354 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1355 reg = <0x022a4000 0x4000>;
1356 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&clks IMX6SX_CLK_PWM5>,
1358 <&clks IMX6SX_CLK_PWM5>;
1359 clock-names = "ipg", "per";
1364 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1365 reg = <0x022a8000 0x4000>;
1366 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1367 clocks = <&clks IMX6SX_CLK_PWM6>,
1368 <&clks IMX6SX_CLK_PWM6>;
1369 clock-names = "ipg", "per";
1374 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1375 reg = <0x022ac000 0x4000>;
1376 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1377 clocks = <&clks IMX6SX_CLK_PWM7>,
1378 <&clks IMX6SX_CLK_PWM7>;
1379 clock-names = "ipg", "per";
1384 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1385 reg = <0x0022b0000 0x4000>;
1386 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1387 clocks = <&clks IMX6SX_CLK_PWM8>,
1388 <&clks IMX6SX_CLK_PWM8>;
1389 clock-names = "ipg", "per";
1394 pcie: pcie@8ffc000 {
1395 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1396 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1397 reg-names = "dbi", "config";
1398 #address-cells = <3>;
1400 device_type = "pci";
1401 bus-range = <0x00 0xff>;
1402 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
1403 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1405 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1406 interrupt-names = "msi";
1407 #interrupt-cells = <1>;
1408 interrupt-map-mask = <0 0 0 0x7>;
1409 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1410 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1411 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1412 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1413 clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1414 <&clks IMX6SX_CLK_LVDS1_OUT>,
1415 <&clks IMX6SX_CLK_PCIE_REF_125M>,
1416 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1417 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1418 power-domains = <&pd_disp>, <&pd_pci>;
1419 power-domain-names = "pcie", "pcie_phy";
1420 status = "disabled";