arch/arm/boot/dts/imx6sx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2014 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/clock/imx6sx-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include "imx6sx-pinfunc.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         /*
  15          * The decompressor and also some bootloaders rely on a
  16          * pre-existing /chosen node to be available to insert the
  17          * command line and merge other ATAGS info.
  18          */
  19         chosen {};
  20
  21         aliases {
  22                 can0 = &flexcan1;
  23                 can1 = &flexcan2;
  24                 ethernet0 = &fec1;
  25                 ethernet1 = &fec2;
  26                 gpio0 = &gpio1;
  27                 gpio1 = &gpio2;
  28                 gpio2 = &gpio3;
  29                 gpio3 = &gpio4;
  30                 gpio4 = &gpio5;
  31                 gpio5 = &gpio6;
  32                 gpio6 = &gpio7;
  33                 i2c0 = &i2c1;
  34                 i2c1 = &i2c2;
  35                 i2c2 = &i2c3;
  36                 i2c3 = &i2c4;
  37                 mmc0 = &usdhc1;
  38                 mmc1 = &usdhc2;
  39                 mmc2 = &usdhc3;
  40                 mmc3 = &usdhc4;
  41                 serial0 = &uart1;
  42                 serial1 = &uart2;
  43                 serial2 = &uart3;
  44                 serial3 = &uart4;
  45                 serial4 = &uart5;
  46                 serial5 = &uart6;
  47                 spi0 = &ecspi1;
  48                 spi1 = &ecspi2;
  49                 spi2 = &ecspi3;
  50                 spi3 = &ecspi4;
  51                 spi4 = &ecspi5;
  52                 usbphy0 = &usbphy1;
  53                 usbphy1 = &usbphy2;
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@0 {
  61                         compatible = "arm,cortex-a9";
  62                         device_type = "cpu";
  63                         reg = <0>;
  64                         next-level-cache = <&L2>;
  65                         operating-points = <
  66                                 /* kHz    uV */
  67                                 996000  1250000
  68                                 792000  1175000
  69                                 396000  1075000
  70                                 198000  975000
  71                         >;
  72                         fsl,soc-operating-points = <
  73                                 /* ARM kHz  SOC uV */
  74                                 996000      1175000
  75                                 792000      1175000
  76                                 396000      1175000
  77                                 198000      1175000
  78                         >;
  79                         clock-latency = <61036>; /* two CLK32 periods */
  80                         #cooling-cells = <2>;
  81                         clocks = <&clks IMX6SX_CLK_ARM>,
  82                                  <&clks IMX6SX_CLK_PLL2_PFD2>,
  83                                  <&clks IMX6SX_CLK_STEP>,
  84                                  <&clks IMX6SX_CLK_PLL1_SW>,
  85                                  <&clks IMX6SX_CLK_PLL1_SYS>;
  86                         clock-names = "arm", "pll2_pfd2_396m", "step",
  87                                       "pll1_sw", "pll1_sys";
  88                         arm-supply = <&reg_arm>;
  89                         soc-supply = <&reg_soc>;
  90                         nvmem-cells = <&cpu_speed_grade>;
  91                         nvmem-cell-names = "speed_grade";
  92                 };
  93         };
  94
  95         ckil: clock-ckil {
  96                 compatible = "fixed-clock";
  97                 #clock-cells = <0>;
  98                 clock-frequency = <32768>;
  99                 clock-output-names = "ckil";
 100         };
 101
 102         osc: clock-osc {
 103                 compatible = "fixed-clock";
 104                 #clock-cells = <0>;
 105                 clock-frequency = <24000000>;
 106                 clock-output-names = "osc";
 107         };
 108
 109         ipp_di0: clock-ipp-di0 {
 110                 compatible = "fixed-clock";
 111                 #clock-cells = <0>;
 112                 clock-frequency = <0>;
 113                 clock-output-names = "ipp_di0";
 114         };
 115
 116         ipp_di1: clock-ipp-di1 {
 117                 compatible = "fixed-clock";
 118                 #clock-cells = <0>;
 119                 clock-frequency = <0>;
 120                 clock-output-names = "ipp_di1";
 121         };
 122
 123         anaclk1: clock-anaclk1 {
 124                 compatible = "fixed-clock";
 125                 #clock-cells = <0>;
 126                 clock-frequency = <0>;
 127                 clock-output-names = "anaclk1";
 128         };
 129
 130         anaclk2: clock-anaclk2 {
 131                 compatible = "fixed-clock";
 132                 #clock-cells = <0>;
 133                 clock-frequency = <0>;
 134                 clock-output-names = "anaclk2";
 135         };
 136
 137         tempmon: tempmon {
 138                 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
 139                 interrupt-parent = <&gpc>;
 140                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 141                 fsl,tempmon = <&anatop>;
 142                 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
 143                 nvmem-cell-names = "calib", "temp_grade";
 144                 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
 145         };
 146
 147         pmu {
 148                 compatible = "arm,cortex-a9-pmu";
 149                 interrupt-parent = <&gpc>;
 150                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 151         };
 152
 153         usbphynop1: usbphynop1 {
 154                 compatible = "usb-nop-xceiv";
 155                 #phy-cells = <0>;
 156         };
 157
 158         soc {
 159                 #address-cells = <1>;
 160                 #size-cells = <1>;
 161                 compatible = "simple-bus";
 162                 interrupt-parent = <&gpc>;
 163                 ranges;
 164
 165                 ocram_s: sram@8f8000 {
 166                         compatible = "mmio-sram";
 167                         reg = <0x008f8000 0x4000>;
 168                         clocks = <&clks IMX6SX_CLK_OCRAM_S>;
 169                 };
 170
 171                 ocram: sram@900000 {
 172                         compatible = "mmio-sram";
 173                         reg = <0x00900000 0x20000>;
 174                         clocks = <&clks IMX6SX_CLK_OCRAM>;
 175                 };
 176
 177                 intc: interrupt-controller@a01000 {
 178                         compatible = "arm,cortex-a9-gic";
 179                         #interrupt-cells = <3>;
 180                         interrupt-controller;
 181                         reg = <0x00a01000 0x1000>,
 182                               <0x00a00100 0x100>;
 183                         interrupt-parent = <&intc>;
 184                 };
 185
 186                 L2: l2-cache@a02000 {
 187                         compatible = "arm,pl310-cache";
 188                         reg = <0x00a02000 0x1000>;
 189                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 190                         cache-unified;
 191                         cache-level = <2>;
 192                         arm,tag-latency = <4 2 3>;
 193                         arm,data-latency = <4 2 3>;
 194                 };
 195
 196                 gpu: gpu@1800000 {
 197                         compatible = "vivante,gc";
 198                         reg = <0x01800000 0x4000>;
 199                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 200                         clocks = <&clks IMX6SX_CLK_GPU>,
 201                                  <&clks IMX6SX_CLK_GPU>,
 202                                  <&clks IMX6SX_CLK_GPU>;
 203                         clock-names = "bus", "core", "shader";
 204                         power-domains = <&pd_pu>;
 205                 };
 206
 207                 dma_apbh: dma-apbh@1804000 {
 208                         compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
 209                         reg = <0x01804000 0x2000>;
 210                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 214                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 215                         #dma-cells = <1>;
 216                         dma-channels = <4>;
 217                         clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 218                 };
 219
 220                 gpmi: gpmi-nand@1806000{
 221                         compatible = "fsl,imx6sx-gpmi-nand";
 222                         #address-cells = <1>;
 223                         #size-cells = <1>;
 224                         reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
 225                         reg-names = "gpmi-nand", "bch";
 226                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 227                         interrupt-names = "bch";
 228                         clocks = <&clks IMX6SX_CLK_GPMI_IO>,
 229                                  <&clks IMX6SX_CLK_GPMI_APB>,
 230                                  <&clks IMX6SX_CLK_GPMI_BCH>,
 231                                  <&clks IMX6SX_CLK_GPMI_BCH_APB>,
 232                                  <&clks IMX6SX_CLK_PER1_BCH>;
 233                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 234                                       "gpmi_bch_apb", "per1_bch";
 235                         dmas = <&dma_apbh 0>;
 236                         dma-names = "rx-tx";
 237                         status = "disabled";
 238                 };
 239
 240                 aips1: bus@2000000 {
 241                         compatible = "fsl,aips-bus", "simple-bus";
 242                         #address-cells = <1>;
 243                         #size-cells = <1>;
 244                         reg = <0x02000000 0x100000>;
 245                         ranges;
 246
 247                         spba-bus@2000000 {
 248                                 compatible = "fsl,spba-bus", "simple-bus";
 249                                 #address-cells = <1>;
 250                                 #size-cells = <1>;
 251                                 reg = <0x02000000 0x40000>;
 252                                 ranges;
 253
 254                                 spdif: spdif@2004000 {
 255                                         compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
 256                                         reg = <0x02004000 0x4000>;
 257                                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 258                                         dmas = <&sdma 14 18 0>,
 259                                                <&sdma 15 18 0>;
 260                                         dma-names = "rx", "tx";
 261                                         clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
 262                                                  <&clks IMX6SX_CLK_OSC>,
 263                                                  <&clks IMX6SX_CLK_SPDIF>,
 264                                                  <&clks 0>, <&clks 0>, <&clks 0>,
 265                                                  <&clks IMX6SX_CLK_IPG>,
 266                                                  <&clks 0>, <&clks 0>,
 267                                                  <&clks IMX6SX_CLK_SPBA>;
 268                                         clock-names = "core", "rxtx0",
 269                                                       "rxtx1", "rxtx2",
 270                                                       "rxtx3", "rxtx4",
 271                                                       "rxtx5", "rxtx6",
 272                                                       "rxtx7", "spba";
 273                                         status = "disabled";
 274                                 };
 275
 276                                 ecspi1: spi@2008000 {
 277                                         #address-cells = <1>;
 278                                         #size-cells = <0>;
 279                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 280                                         reg = <0x02008000 0x4000>;
 281                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 282                                         clocks = <&clks IMX6SX_CLK_ECSPI1>,
 283                                                  <&clks IMX6SX_CLK_ECSPI1>;
 284                                         clock-names = "ipg", "per";
 285                                         status = "disabled";
 286                                 };
 287
 288                                 ecspi2: spi@200c000 {
 289                                         #address-cells = <1>;
 290                                         #size-cells = <0>;
 291                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 292                                         reg = <0x0200c000 0x4000>;
 293                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 294                                         clocks = <&clks IMX6SX_CLK_ECSPI2>,
 295                                                  <&clks IMX6SX_CLK_ECSPI2>;
 296                                         clock-names = "ipg", "per";
 297                                         status = "disabled";
 298                                 };
 299
 300                                 ecspi3: spi@2010000 {
 301                                         #address-cells = <1>;
 302                                         #size-cells = <0>;
 303                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 304                                         reg = <0x02010000 0x4000>;
 305                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 306                                         clocks = <&clks IMX6SX_CLK_ECSPI3>,
 307                                                  <&clks IMX6SX_CLK_ECSPI3>;
 308                                         clock-names = "ipg", "per";
 309                                         status = "disabled";
 310                                 };
 311
 312                                 ecspi4: spi@2014000 {
 313                                         #address-cells = <1>;
 314                                         #size-cells = <0>;
 315                                         compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
 316                                         reg = <0x02014000 0x4000>;
 317                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 318                                         clocks = <&clks IMX6SX_CLK_ECSPI4>,
 319                                                  <&clks IMX6SX_CLK_ECSPI4>;
 320                                         clock-names = "ipg", "per";
 321                                         status = "disabled";
 322                                 };
 323
 324                                 uart1: serial@2020000 {
 325                                         compatible = "fsl,imx6sx-uart",
 326                                                      "fsl,imx6q-uart", "fsl,imx21-uart";
 327                                         reg = <0x02020000 0x4000>;
 328                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 329                                         clocks = <&clks IMX6SX_CLK_UART_IPG>,
 330                                                  <&clks IMX6SX_CLK_UART_SERIAL>;
 331                                         clock-names = "ipg", "per";
 332                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 333                                         dma-names = "rx", "tx";
 334                                         status = "disabled";
 335                                 };
 336
 337                                 esai: esai@2024000 {
 338                                         reg = <0x02024000 0x4000>;
 339                                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 340                                         clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
 341                                                  <&clks IMX6SX_CLK_ESAI_MEM>,
 342                                                  <&clks IMX6SX_CLK_ESAI_EXTAL>,
 343                                                  <&clks IMX6SX_CLK_ESAI_IPG>,
 344                                                  <&clks IMX6SX_CLK_SPBA>;
 345                                         clock-names = "core", "mem", "extal",
 346                                                       "fsys", "spba";
 347                                         status = "disabled";
 348                                 };
 349
 350                                 ssi1: ssi@2028000 {
 351                                         #sound-dai-cells = <0>;
 352                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 353                                         reg = <0x02028000 0x4000>;
 354                                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 355                                         clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
 356                                                  <&clks IMX6SX_CLK_SSI1>;
 357                                         clock-names = "ipg", "baud";
 358                                         dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
 359                                         dma-names = "rx", "tx";
 360                                         fsl,fifo-depth = <15>;
 361                                         status = "disabled";
 362                                 };
 363
 364                                 ssi2: ssi@202c000 {
 365                                         #sound-dai-cells = <0>;
 366                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 367                                         reg = <0x0202c000 0x4000>;
 368                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 369                                         clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
 370                                                  <&clks IMX6SX_CLK_SSI2>;
 371                                         clock-names = "ipg", "baud";
 372                                         dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
 373                                         dma-names = "rx", "tx";
 374                                         fsl,fifo-depth = <15>;
 375                                         status = "disabled";
 376                                 };
 377
 378                                 ssi3: ssi@2030000 {
 379                                         #sound-dai-cells = <0>;
 380                                         compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
 381                                         reg = <0x02030000 0x4000>;
 382                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 383                                         clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
 384                                                  <&clks IMX6SX_CLK_SSI3>;
 385                                         clock-names = "ipg", "baud";
 386                                         dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
 387                                         dma-names = "rx", "tx";
 388                                         fsl,fifo-depth = <15>;
 389                                         status = "disabled";
 390                                 };
 391
 392                                 asrc: asrc@2034000 {
 393                                         reg = <0x02034000 0x4000>;
 394                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 395                                         clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
 396                                                  <&clks IMX6SX_CLK_ASRC_IPG>,
 397                                                  <&clks IMX6SX_CLK_SPDIF>,
 398                                                  <&clks IMX6SX_CLK_SPBA>;
 399                                         clock-names = "mem", "ipg", "asrck", "spba";
 400                                         dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
 401                                                <&sdma 19 20 1>, <&sdma 20 20 1>,
 402                                                <&sdma 21 20 1>, <&sdma 22 20 1>;
 403                                         dma-names = "rxa", "rxb", "rxc",
 404                                                     "txa", "txb", "txc";
 405                                         status = "okay";
 406                                 };
 407                         };
 408
 409                         pwm1: pwm@2080000 {
 410                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 411                                 reg = <0x02080000 0x4000>;
 412                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 413                                 clocks = <&clks IMX6SX_CLK_PWM1>,
 414                                          <&clks IMX6SX_CLK_PWM1>;
 415                                 clock-names = "ipg", "per";
 416                                 #pwm-cells = <2>;
 417                         };
 418
 419                         pwm2: pwm@2084000 {
 420                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 421                                 reg = <0x02084000 0x4000>;
 422                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 423                                 clocks = <&clks IMX6SX_CLK_PWM2>,
 424                                          <&clks IMX6SX_CLK_PWM2>;
 425                                 clock-names = "ipg", "per";
 426                                 #pwm-cells = <2>;
 427                         };
 428
 429                         pwm3: pwm@2088000 {
 430                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 431                                 reg = <0x02088000 0x4000>;
 432                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 433                                 clocks = <&clks IMX6SX_CLK_PWM3>,
 434                                          <&clks IMX6SX_CLK_PWM3>;
 435                                 clock-names = "ipg", "per";
 436                                 #pwm-cells = <2>;
 437                         };
 438
 439                         pwm4: pwm@208c000 {
 440                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
 441                                 reg = <0x0208c000 0x4000>;
 442                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 443                                 clocks = <&clks IMX6SX_CLK_PWM4>,
 444                                          <&clks IMX6SX_CLK_PWM4>;
 445                                 clock-names = "ipg", "per";
 446                                 #pwm-cells = <2>;
 447                         };
 448
 449                         flexcan1: can@2090000 {
 450                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 451                                 reg = <0x02090000 0x4000>;
 452                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 453                                 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 454                                          <&clks IMX6SX_CLK_CAN1_SERIAL>;
 455                                 clock-names = "ipg", "per";
 456                                 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
 457                                 status = "disabled";
 458                         };
 459
 460                         flexcan2: can@2094000 {
 461                                 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
 462                                 reg = <0x02094000 0x4000>;
 463                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 464                                 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 465                                          <&clks IMX6SX_CLK_CAN2_SERIAL>;
 466                                 clock-names = "ipg", "per";
 467                                 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
 468                                 status = "disabled";
 469                         };
 470
 471                         gpt: timer@2098000 {
 472                                 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
 473                                 reg = <0x02098000 0x4000>;
 474                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 475                                 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
 476                                          <&clks IMX6SX_CLK_GPT_3M>;
 477                                 clock-names = "ipg", "per";
 478                         };
 479
 480                         gpio1: gpio@209c000 {
 481                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 482                                 reg = <0x0209c000 0x4000>;
 483                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 484                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 485                                 gpio-controller;
 486                                 #gpio-cells = <2>;
 487                                 interrupt-controller;
 488                                 #interrupt-cells = <2>;
 489                                 gpio-ranges = <&iomuxc 0 5 26>;
 490                         };
 491
 492                         gpio2: gpio@20a0000 {
 493                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 494                                 reg = <0x020a0000 0x4000>;
 495                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 496                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 497                                 gpio-controller;
 498                                 #gpio-cells = <2>;
 499                                 interrupt-controller;
 500                                 #interrupt-cells = <2>;
 501                                 gpio-ranges = <&iomuxc 0 31 20>;
 502                         };
 503
 504                         gpio3: gpio@20a4000 {
 505                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 506                                 reg = <0x020a4000 0x4000>;
 507                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 508                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 509                                 gpio-controller;
 510                                 #gpio-cells = <2>;
 511                                 interrupt-controller;
 512                                 #interrupt-cells = <2>;
 513                                 gpio-ranges = <&iomuxc 0 51 29>;
 514                         };
 515
 516                         gpio4: gpio@20a8000 {
 517                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 518                                 reg = <0x020a8000 0x4000>;
 519                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 520                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 521                                 gpio-controller;
 522                                 #gpio-cells = <2>;
 523                                 interrupt-controller;
 524                                 #interrupt-cells = <2>;
 525                                 gpio-ranges = <&iomuxc 0 80 32>;
 526                         };
 527
 528                         gpio5: gpio@20ac000 {
 529                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 530                                 reg = <0x020ac000 0x4000>;
 531                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 532                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 533                                 gpio-controller;
 534                                 #gpio-cells = <2>;
 535                                 interrupt-controller;
 536                                 #interrupt-cells = <2>;
 537                                 gpio-ranges = <&iomuxc 0 112 24>;
 538                         };
 539
 540                         gpio6: gpio@20b0000 {
 541                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 542                                 reg = <0x020b0000 0x4000>;
 543                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 544                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 545                                 gpio-controller;
 546                                 #gpio-cells = <2>;
 547                                 interrupt-controller;
 548                                 #interrupt-cells = <2>;
 549                                 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
 550                         };
 551
 552                         gpio7: gpio@20b4000 {
 553                                 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
 554                                 reg = <0x020b4000 0x4000>;
 555                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 556                                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 557                                 gpio-controller;
 558                                 #gpio-cells = <2>;
 559                                 interrupt-controller;
 560                                 #interrupt-cells = <2>;
 561                                 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
 562                         };
 563
 564                         kpp: keypad@20b8000 {
 565                                 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 566                                 reg = <0x020b8000 0x4000>;
 567                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 568                                 clocks = <&clks IMX6SX_CLK_IPG>;
 569                                 status = "disabled";
 570                         };
 571
 572                         wdog1: watchdog@20bc000 {
 573                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 574                                 reg = <0x020bc000 0x4000>;
 575                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 576                                 clocks = <&clks IMX6SX_CLK_IPG>;
 577                         };
 578
 579                         wdog2: watchdog@20c0000 {
 580                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 581                                 reg = <0x020c0000 0x4000>;
 582                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 583                                 clocks = <&clks IMX6SX_CLK_IPG>;
 584                                 status = "disabled";
 585                         };
 586
 587                         clks: clock-controller@20c4000 {
 588                                 compatible = "fsl,imx6sx-ccm";
 589                                 reg = <0x020c4000 0x4000>;
 590                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 591                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 592                                 #clock-cells = <1>;
 593                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
 594                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
 595                         };
 596
 597                         anatop: anatop@20c8000 {
 598                                 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
 599                                              "syscon", "simple-mfd";
 600                                 reg = <0x020c8000 0x1000>;
 601                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 602                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 603                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 604
 605                                 reg_vdd1p1: regulator-1p1 {
 606                                         compatible = "fsl,anatop-regulator";
 607                                         regulator-name = "vdd1p1";
 608                                         regulator-min-microvolt = <1000000>;
 609                                         regulator-max-microvolt = <1200000>;
 610                                         regulator-always-on;
 611                                         anatop-reg-offset = <0x110>;
 612                                         anatop-vol-bit-shift = <8>;
 613                                         anatop-vol-bit-width = <5>;
 614                                         anatop-min-bit-val = <4>;
 615                                         anatop-min-voltage = <800000>;
 616                                         anatop-max-voltage = <1375000>;
 617                                         anatop-enable-bit = <0>;
 618                                 };
 619
 620                                 reg_vdd3p0: regulator-3p0 {
 621                                         compatible = "fsl,anatop-regulator";
 622                                         regulator-name = "vdd3p0";
 623                                         regulator-min-microvolt = <2800000>;
 624                                         regulator-max-microvolt = <3150000>;
 625                                         regulator-always-on;
 626                                         anatop-reg-offset = <0x120>;
 627                                         anatop-vol-bit-shift = <8>;
 628                                         anatop-vol-bit-width = <5>;
 629                                         anatop-min-bit-val = <0>;
 630                                         anatop-min-voltage = <2625000>;
 631                                         anatop-max-voltage = <3400000>;
 632                                         anatop-enable-bit = <0>;
 633                                 };
 634
 635                                 reg_vdd2p5: regulator-2p5 {
 636                                         compatible = "fsl,anatop-regulator";
 637                                         regulator-name = "vdd2p5";
 638                                         regulator-min-microvolt = <2250000>;
 639                                         regulator-max-microvolt = <2750000>;
 640                                         regulator-always-on;
 641                                         anatop-reg-offset = <0x130>;
 642                                         anatop-vol-bit-shift = <8>;
 643                                         anatop-vol-bit-width = <5>;
 644                                         anatop-min-bit-val = <0>;
 645                                         anatop-min-voltage = <2100000>;
 646                                         anatop-max-voltage = <2875000>;
 647                                         anatop-enable-bit = <0>;
 648                                 };
 649
 650                                 reg_arm: regulator-vddcore {
 651                                         compatible = "fsl,anatop-regulator";
 652                                         regulator-name = "vddarm";
 653                                         regulator-min-microvolt = <725000>;
 654                                         regulator-max-microvolt = <1450000>;
 655                                         regulator-always-on;
 656                                         anatop-reg-offset = <0x140>;
 657                                         anatop-vol-bit-shift = <0>;
 658                                         anatop-vol-bit-width = <5>;
 659                                         anatop-delay-reg-offset = <0x170>;
 660                                         anatop-delay-bit-shift = <24>;
 661                                         anatop-delay-bit-width = <2>;
 662                                         anatop-min-bit-val = <1>;
 663                                         anatop-min-voltage = <725000>;
 664                                         anatop-max-voltage = <1450000>;
 665                                 };
 666
 667                                 reg_pcie: regulator-vddpcie {
 668                                         compatible = "fsl,anatop-regulator";
 669                                         regulator-name = "vddpcie";
 670                                         regulator-min-microvolt = <725000>;
 671                                         regulator-max-microvolt = <1450000>;
 672                                         anatop-reg-offset = <0x140>;
 673                                         anatop-vol-bit-shift = <9>;
 674                                         anatop-vol-bit-width = <5>;
 675                                         anatop-delay-reg-offset = <0x170>;
 676                                         anatop-delay-bit-shift = <26>;
 677                                         anatop-delay-bit-width = <2>;
 678                                         anatop-min-bit-val = <1>;
 679                                         anatop-min-voltage = <725000>;
 680                                         anatop-max-voltage = <1450000>;
 681                                 };
 682
 683                                 reg_soc: regulator-vddsoc {
 684                                         compatible = "fsl,anatop-regulator";
 685                                         regulator-name = "vddsoc";
 686                                         regulator-min-microvolt = <725000>;
 687                                         regulator-max-microvolt = <1450000>;
 688                                         regulator-always-on;
 689                                         anatop-reg-offset = <0x140>;
 690                                         anatop-vol-bit-shift = <18>;
 691                                         anatop-vol-bit-width = <5>;
 692                                         anatop-delay-reg-offset = <0x170>;
 693                                         anatop-delay-bit-shift = <28>;
 694                                         anatop-delay-bit-width = <2>;
 695                                         anatop-min-bit-val = <1>;
 696                                         anatop-min-voltage = <725000>;
 697                                         anatop-max-voltage = <1450000>;
 698                                 };
 699                         };
 700
 701                         usbphy1: usbphy@20c9000 {
 702                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 703                                 reg = <0x020c9000 0x1000>;
 704                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 705                                 clocks = <&clks IMX6SX_CLK_USBPHY1>;
 706                                 fsl,anatop = <&anatop>;
 707                         };
 708
 709                         usbphy2: usbphy@20ca000 {
 710                                 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
 711                                 reg = <0x020ca000 0x1000>;
 712                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 713                                 clocks = <&clks IMX6SX_CLK_USBPHY2>;
 714                                 fsl,anatop = <&anatop>;
 715                         };
 716
 717                         snvs: snvs@20cc000 {
 718                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 719                                 reg = <0x020cc000 0x4000>;
 720
 721                                 snvs_rtc: snvs-rtc-lp {
 722                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 723                                         regmap = <&snvs>;
 724                                         offset = <0x34>;
 725                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 726                                 };
 727
 728                                 snvs_poweroff: snvs-poweroff {
 729                                         compatible = "syscon-poweroff";
 730                                         regmap = <&snvs>;
 731                                         offset = <0x38>;
 732                                         value = <0x60>;
 733                                         mask = <0x60>;
 734                                         status = "disabled";
 735                                 };
 736
 737                                 snvs_pwrkey: snvs-powerkey {
 738                                         compatible = "fsl,sec-v4.0-pwrkey";
 739                                         regmap = <&snvs>;
 740                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 741                                         linux,keycode = <KEY_POWER>;
 742                                         wakeup-source;
 743                                         status = "disabled";
 744                                 };
 745                         };
 746
 747                         epit1: epit@20d0000 {
 748                                 reg = <0x020d0000 0x4000>;
 749                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 750                         };
 751
 752                         epit2: epit@20d4000 {
 753                                 reg = <0x020d4000 0x4000>;
 754                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 755                         };
 756
 757                         src: reset-controller@20d8000 {
 758                                 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 759                                 reg = <0x020d8000 0x4000>;
 760                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 761                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 762                                 #reset-cells = <1>;
 763                         };
 764
 765                         gpc: gpc@20dc000 {
 766                                 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
 767                                 reg = <0x020dc000 0x4000>;
 768                                 interrupt-controller;
 769                                 #interrupt-cells = <3>;
 770                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 771                                 interrupt-parent = <&intc>;
 772                                 clocks = <&clks IMX6SX_CLK_IPG>;
 773                                 clock-names = "ipg";
 774
 775                                 pgc {
 776                                         #address-cells = <1>;
 777                                         #size-cells = <0>;
 778
 779                                         power-domain@0 {
 780                                                 reg = <0>;
 781                                                 #power-domain-cells = <0>;
 782                                         };
 783
 784                                         pd_pu: power-domain@1 {
 785                                                 reg = <1>;
 786                                                 #power-domain-cells = <0>;
 787                                                 power-supply = <&reg_soc>;
 788                                                 clocks = <&clks IMX6SX_CLK_GPU>;
 789                                         };
 790
 791                                         pd_disp: power-domain@2 {
 792                                                 reg = <2>;
 793                                                 #power-domain-cells = <0>;
 794                                                 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
 795                                                          <&clks IMX6SX_CLK_DISPLAY_AXI>,
 796                                                          <&clks IMX6SX_CLK_LCDIF1_PIX>,
 797                                                          <&clks IMX6SX_CLK_LCDIF_APB>,
 798                                                          <&clks IMX6SX_CLK_LCDIF2_PIX>,
 799                                                          <&clks IMX6SX_CLK_CSI>,
 800                                                          <&clks IMX6SX_CLK_VADC>;
 801                                         };
 802
 803                                         pd_pci: power-domain@3 {
 804                                                 reg = <3>;
 805                                                 #power-domain-cells = <0>;
 806                                                 power-supply = <&reg_pcie>;
 807                                         };
 808                                 };
 809                         };
 810
 811                         iomuxc: pinctrl@20e0000 {
 812                                 compatible = "fsl,imx6sx-iomuxc";
 813                                 reg = <0x020e0000 0x4000>;
 814                         };
 815
 816                         gpr: iomuxc-gpr@20e4000 {
 817                                 compatible = "fsl,imx6sx-iomuxc-gpr",
 818                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 819                                 reg = <0x020e4000 0x4000>;
 820                         };
 821
 822                         sdma: sdma@20ec000 {
 823                                 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
 824                                 reg = <0x020ec000 0x4000>;
 825                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 826                                 clocks = <&clks IMX6SX_CLK_IPG>,
 827                                          <&clks IMX6SX_CLK_SDMA>;
 828                                 clock-names = "ipg", "ahb";
 829                                 #dma-cells = <3>;
 830                                 /* imx6sx reuses imx6q sdma firmware */
 831                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 832                         };
 833                 };
 834
 835                 aips2: bus@2100000 {
 836                         compatible = "fsl,aips-bus", "simple-bus";
 837                         #address-cells = <1>;
 838                         #size-cells = <1>;
 839                         reg = <0x02100000 0x100000>;
 840                         ranges;
 841
 842                         crypto: crypto@2100000 {
 843                                 compatible = "fsl,sec-v4.0";
 844                                 #address-cells = <1>;
 845                                 #size-cells = <1>;
 846                                 reg = <0x2100000 0x10000>;
 847                                 ranges = <0 0x2100000 0x10000>;
 848                                 interrupt-parent = <&intc>;
 849                                 clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
 850                                          <&clks IMX6SX_CLK_CAAM_ACLK>,
 851                                          <&clks IMX6SX_CLK_CAAM_IPG>,
 852                                          <&clks IMX6SX_CLK_EIM_SLOW>;
 853                                 clock-names = "mem", "aclk", "ipg", "emi_slow";
 854
 855                                 sec_jr0: jr@1000 {
 856                                         compatible = "fsl,sec-v4.0-job-ring";
 857                                         reg = <0x1000 0x1000>;
 858                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 859                                 };
 860
 861                                 sec_jr1: jr@2000 {
 862                                         compatible = "fsl,sec-v4.0-job-ring";
 863                                         reg = <0x2000 0x1000>;
 864                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 865                                 };
 866                         };
 867
 868                         usbotg1: usb@2184000 {
 869                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 870                                 reg = <0x02184000 0x200>;
 871                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 872                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 873                                 fsl,usbphy = <&usbphy1>;
 874                                 fsl,usbmisc = <&usbmisc 0>;
 875                                 fsl,anatop = <&anatop>;
 876                                 ahb-burst-config = <0x0>;
 877                                 tx-burst-size-dword = <0x10>;
 878                                 rx-burst-size-dword = <0x10>;
 879                                 status = "disabled";
 880                         };
 881
 882                         usbotg2: usb@2184200 {
 883                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 884                                 reg = <0x02184200 0x200>;
 885                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 886                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 887                                 fsl,usbphy = <&usbphy2>;
 888                                 fsl,usbmisc = <&usbmisc 1>;
 889                                 ahb-burst-config = <0x0>;
 890                                 tx-burst-size-dword = <0x10>;
 891                                 rx-burst-size-dword = <0x10>;
 892                                 status = "disabled";
 893                         };
 894
 895                         usbh: usb@2184400 {
 896                                 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 897                                 reg = <0x02184400 0x200>;
 898                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 899                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 900                                 fsl,usbphy = <&usbphynop1>;
 901                                 fsl,usbmisc = <&usbmisc 2>;
 902                                 phy_type = "hsic";
 903                                 fsl,anatop = <&anatop>;
 904                                 dr_mode = "host";
 905                                 ahb-burst-config = <0x0>;
 906                                 tx-burst-size-dword = <0x10>;
 907                                 rx-burst-size-dword = <0x10>;
 908                                 status = "disabled";
 909                         };
 910
 911                         usbmisc: usbmisc@2184800 {
 912                                 #index-cells = <1>;
 913                                 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
 914                                 reg = <0x02184800 0x200>;
 915                                 clocks = <&clks IMX6SX_CLK_USBOH3>;
 916                         };
 917
 918                         fec1: ethernet@2188000 {
 919                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
 920                                 reg = <0x02188000 0x4000>;
 921                                 interrupt-names = "int0", "pps";
 922                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 923                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 924                                 clocks = <&clks IMX6SX_CLK_ENET>,
 925                                          <&clks IMX6SX_CLK_ENET_AHB>,
 926                                          <&clks IMX6SX_CLK_ENET_PTP>,
 927                                          <&clks IMX6SX_CLK_ENET_REF>,
 928                                          <&clks IMX6SX_CLK_ENET_PTP>;
 929                                 clock-names = "ipg", "ahb", "ptp",
 930                                               "enet_clk_ref", "enet_out";
 931                                 fsl,num-tx-queues = <3>;
 932                                 fsl,num-rx-queues = <3>;
 933                                 fsl,stop-mode = <&gpr 0x10 3>;
 934                                 status = "disabled";
 935                         };
 936
 937                         mlb: mlb@218c000 {
 938                                 reg = <0x0218c000 0x4000>;
 939                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 940                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 941                                              <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 942                                 clocks = <&clks IMX6SX_CLK_MLB>;
 943                                 status = "disabled";
 944                         };
 945
 946                         usdhc1: usdhc@2190000 {
 947                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 948                                 reg = <0x02190000 0x4000>;
 949                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 950                                 clocks = <&clks IMX6SX_CLK_USDHC1>,
 951                                          <&clks IMX6SX_CLK_USDHC1>,
 952                                          <&clks IMX6SX_CLK_USDHC1>;
 953                                 clock-names = "ipg", "ahb", "per";
 954                                 bus-width = <4>;
 955                                 status = "disabled";
 956                         };
 957
 958                         usdhc2: usdhc@2194000 {
 959                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 960                                 reg = <0x02194000 0x4000>;
 961                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 962                                 clocks = <&clks IMX6SX_CLK_USDHC2>,
 963                                          <&clks IMX6SX_CLK_USDHC2>,
 964                                          <&clks IMX6SX_CLK_USDHC2>;
 965                                 clock-names = "ipg", "ahb", "per";
 966                                 bus-width = <4>;
 967                                 status = "disabled";
 968                         };
 969
 970                         usdhc3: usdhc@2198000 {
 971                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 972                                 reg = <0x02198000 0x4000>;
 973                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 974                                 clocks = <&clks IMX6SX_CLK_USDHC3>,
 975                                          <&clks IMX6SX_CLK_USDHC3>,
 976                                          <&clks IMX6SX_CLK_USDHC3>;
 977                                 clock-names = "ipg", "ahb", "per";
 978                                 bus-width = <4>;
 979                                 status = "disabled";
 980                         };
 981
 982                         usdhc4: usdhc@219c000 {
 983                                 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 984                                 reg = <0x0219c000 0x4000>;
 985                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 986                                 clocks = <&clks IMX6SX_CLK_USDHC4>,
 987                                          <&clks IMX6SX_CLK_USDHC4>,
 988                                          <&clks IMX6SX_CLK_USDHC4>;
 989                                 clock-names = "ipg", "ahb", "per";
 990                                 bus-width = <4>;
 991                                 status = "disabled";
 992                         };
 993
 994                         i2c1: i2c@21a0000 {
 995                                 #address-cells = <1>;
 996                                 #size-cells = <0>;
 997                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
 998                                 reg = <0x021a0000 0x4000>;
 999                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1000                                 clocks = <&clks IMX6SX_CLK_I2C1>;
1001                                 status = "disabled";
1002                         };
1003
1004                         i2c2: i2c@21a4000 {
1005                                 #address-cells = <1>;
1006                                 #size-cells = <0>;
1007                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1008                                 reg = <0x021a4000 0x4000>;
1009                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1010                                 clocks = <&clks IMX6SX_CLK_I2C2>;
1011                                 status = "disabled";
1012                         };
1013
1014                         i2c3: i2c@21a8000 {
1015                                 #address-cells = <1>;
1016                                 #size-cells = <0>;
1017                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1018                                 reg = <0x021a8000 0x4000>;
1019                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1020                                 clocks = <&clks IMX6SX_CLK_I2C3>;
1021                                 status = "disabled";
1022                         };
1023
1024                         memory-controller@21b0000 {
1025                                 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1026                                 reg = <0x021b0000 0x4000>;
1027                                 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
1028                         };
1029
1030                         fec2: ethernet@21b4000 {
1031                                 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1032                                 reg = <0x021b4000 0x4000>;
1033                                 interrupt-names = "int0", "pps";
1034                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1035                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1036                                 clocks = <&clks IMX6SX_CLK_ENET>,
1037                                          <&clks IMX6SX_CLK_ENET_AHB>,
1038                                          <&clks IMX6SX_CLK_ENET_PTP>,
1039                                          <&clks IMX6SX_CLK_ENET2_REF_125M>,
1040                                          <&clks IMX6SX_CLK_ENET_PTP>;
1041                                 clock-names = "ipg", "ahb", "ptp",
1042                                               "enet_clk_ref", "enet_out";
1043                                 fsl,stop-mode = <&gpr 0x10 4>;
1044                                 status = "disabled";
1045                         };
1046
1047                         weim: weim@21b8000 {
1048                                 #address-cells = <2>;
1049                                 #size-cells = <1>;
1050                                 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1051                                 reg = <0x021b8000 0x4000>;
1052                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1053                                 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
1054                                 fsl,weim-cs-gpr = <&gpr>;
1055                                 status = "disabled";
1056                         };
1057
1058                         ocotp: ocotp-ctrl@21bc000 {
1059                                 #address-cells = <1>;
1060                                 #size-cells = <1>;
1061                                 compatible = "fsl,imx6sx-ocotp", "syscon";
1062                                 reg = <0x021bc000 0x4000>;
1063                                 clocks = <&clks IMX6SX_CLK_OCOTP>;
1064
1065                                 cpu_speed_grade: speed-grade@10 {
1066                                         reg = <0x10 4>;
1067                                 };
1068
1069                                 tempmon_calib: calib@38 {
1070                                         reg = <0x38 4>;
1071                                 };
1072
1073                                 tempmon_temp_grade: temp-grade@20 {
1074                                         reg = <0x20 4>;
1075                                 };
1076                         };
1077
1078                         sai1: sai@21d4000 {
1079                                 compatible = "fsl,imx6sx-sai";
1080                                 reg = <0x021d4000 0x4000>;
1081                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1082                                 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
1083                                          <&clks IMX6SX_CLK_SAI1>,
1084                                          <&clks 0>, <&clks 0>;
1085                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1086                                 dma-names = "rx", "tx";
1087                                 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
1088                                 status = "disabled";
1089                         };
1090
1091                         audmux: audmux@21d8000 {
1092                                 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1093                                 reg = <0x021d8000 0x4000>;
1094                                 status = "disabled";
1095                         };
1096
1097                         sai2: sai@21dc000 {
1098                                 compatible = "fsl,imx6sx-sai";
1099                                 reg = <0x021dc000 0x4000>;
1100                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1101                                 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
1102                                          <&clks IMX6SX_CLK_SAI2>,
1103                                          <&clks 0>, <&clks 0>;
1104                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1105                                 dma-names = "rx", "tx";
1106                                 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
1107                                 status = "disabled";
1108                         };
1109
1110                         qspi1: spi@21e0000 {
1111                                 #address-cells = <1>;
1112                                 #size-cells = <0>;
1113                                 compatible = "fsl,imx6sx-qspi";
1114                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1115                                 reg-names = "QuadSPI", "QuadSPI-memory";
1116                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1117                                 clocks = <&clks IMX6SX_CLK_QSPI1>,
1118                                          <&clks IMX6SX_CLK_QSPI1>;
1119                                 clock-names = "qspi_en", "qspi";
1120                                 status = "disabled";
1121                         };
1122
1123                         qspi2: spi@21e4000 {
1124                                 #address-cells = <1>;
1125                                 #size-cells = <0>;
1126                                 compatible = "fsl,imx6sx-qspi";
1127                                 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
1128                                 reg-names = "QuadSPI", "QuadSPI-memory";
1129                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1130                                 clocks = <&clks IMX6SX_CLK_QSPI2>,
1131                                          <&clks IMX6SX_CLK_QSPI2>;
1132                                 clock-names = "qspi_en", "qspi";
1133                                 status = "disabled";
1134                         };
1135
1136                         uart2: serial@21e8000 {
1137                                 compatible = "fsl,imx6sx-uart",
1138                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1139                                 reg = <0x021e8000 0x4000>;
1140                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1141                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1142                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1143                                 clock-names = "ipg", "per";
1144                                 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1145                                 dma-names = "rx", "tx";
1146                                 status = "disabled";
1147                         };
1148
1149                         uart3: serial@21ec000 {
1150                                 compatible = "fsl,imx6sx-uart",
1151                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1152                                 reg = <0x021ec000 0x4000>;
1153                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1154                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1155                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1156                                 clock-names = "ipg", "per";
1157                                 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1158                                 dma-names = "rx", "tx";
1159                                 status = "disabled";
1160                         };
1161
1162                         uart4: serial@21f0000 {
1163                                 compatible = "fsl,imx6sx-uart",
1164                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1165                                 reg = <0x021f0000 0x4000>;
1166                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1167                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1168                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1169                                 clock-names = "ipg", "per";
1170                                 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1171                                 dma-names = "rx", "tx";
1172                                 status = "disabled";
1173                         };
1174
1175                         uart5: serial@21f4000 {
1176                                 compatible = "fsl,imx6sx-uart",
1177                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1178                                 reg = <0x021f4000 0x4000>;
1179                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1180                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1181                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1182                                 clock-names = "ipg", "per";
1183                                 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1184                                 dma-names = "rx", "tx";
1185                                 status = "disabled";
1186                         };
1187
1188                         i2c4: i2c@21f8000 {
1189                                 #address-cells = <1>;
1190                                 #size-cells = <0>;
1191                                 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1192                                 reg = <0x021f8000 0x4000>;
1193                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1194                                 clocks = <&clks IMX6SX_CLK_I2C4>;
1195                                 status = "disabled";
1196                         };
1197                 };
1198
1199                 aips3: bus@2200000 {
1200                         compatible = "fsl,aips-bus", "simple-bus";
1201                         #address-cells = <1>;
1202                         #size-cells = <1>;
1203                         reg = <0x02200000 0x100000>;
1204                         ranges;
1205
1206                         spba-bus@2240000 {
1207                                 compatible = "fsl,spba-bus", "simple-bus";
1208                                 #address-cells = <1>;
1209                                 #size-cells = <1>;
1210                                 reg = <0x02240000 0x40000>;
1211                                 ranges;
1212
1213                                 csi1: csi@2214000 {
1214                                         reg = <0x02214000 0x4000>;
1215                                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1216                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1217                                                  <&clks IMX6SX_CLK_CSI>,
1218                                                  <&clks IMX6SX_CLK_DCIC1>;
1219                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1220                                         status = "disabled";
1221                                 };
1222
1223                                 pxp: pxp@2218000 {
1224                                         compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1225                                         reg = <0x02218000 0x4000>;
1226                                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1227                                         clocks = <&clks IMX6SX_CLK_PXP_AXI>;
1228                                         clock-names = "axi";
1229                                         power-domains = <&pd_disp>;
1230                                         status = "disabled";
1231                                 };
1232
1233                                 csi2: csi@221c000 {
1234                                         reg = <0x0221c000 0x4000>;
1235                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1236                                         clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1237                                                  <&clks IMX6SX_CLK_CSI>,
1238                                                  <&clks IMX6SX_CLK_DCIC2>;
1239                                         clock-names = "disp-axi", "csi_mclk", "dcic";
1240                                         status = "disabled";
1241                                 };
1242
1243                                 lcdif1: lcdif@2220000 {
1244                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1245                                         reg = <0x02220000 0x4000>;
1246                                         interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
1247                                         clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1248                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1249                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1250                                         clock-names = "pix", "axi", "disp_axi";
1251                                         power-domains = <&pd_disp>;
1252                                         status = "disabled";
1253                                 };
1254
1255                                 lcdif2: lcdif@2224000 {
1256                                         compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1257                                         reg = <0x02224000 0x4000>;
1258                                         interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
1259                                         clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1260                                                  <&clks IMX6SX_CLK_LCDIF_APB>,
1261                                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1262                                         clock-names = "pix", "axi", "disp_axi";
1263                                         power-domains = <&pd_disp>;
1264                                         status = "disabled";
1265                                 };
1266
1267                                 vadc: vadc@2228000 {
1268                                         reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1269                                         reg-names = "vadc-vafe", "vadc-vdec";
1270                                         clocks = <&clks IMX6SX_CLK_VADC>,
1271                                                  <&clks IMX6SX_CLK_CSI>;
1272                                         clock-names = "vadc", "csi";
1273                                         power-domains = <&pd_disp>;
1274                                         status = "disabled";
1275                                 };
1276                         };
1277
1278                         adc1: adc@2280000 {
1279                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1280                                 reg = <0x02280000 0x4000>;
1281                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1282                                 clocks = <&clks IMX6SX_CLK_IPG>;
1283                                 clock-names = "adc";
1284                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1285                                                          <20000000>;
1286                                 status = "disabled";
1287                         };
1288
1289                         adc2: adc@2284000 {
1290                                 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1291                                 reg = <0x02284000 0x4000>;
1292                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1293                                 clocks = <&clks IMX6SX_CLK_IPG>;
1294                                 clock-names = "adc";
1295                                 fsl,adck-max-frequency = <30000000>, <40000000>,
1296                                                          <20000000>;
1297                                 status = "disabled";
1298                         };
1299
1300                         wdog3: watchdog@2288000 {
1301                                 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1302                                 reg = <0x02288000 0x4000>;
1303                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1304                                 clocks = <&clks IMX6SX_CLK_IPG>;
1305                                 status = "disabled";
1306                         };
1307
1308                         ecspi5: spi@228c000 {
1309                                 #address-cells = <1>;
1310                                 #size-cells = <0>;
1311                                 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1312                                 reg = <0x0228c000 0x4000>;
1313                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1314                                 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1315                                          <&clks IMX6SX_CLK_ECSPI5>;
1316                                 clock-names = "ipg", "per";
1317                                 status = "disabled";
1318                         };
1319
1320                         uart6: serial@22a0000 {
1321                                 compatible = "fsl,imx6sx-uart",
1322                                              "fsl,imx6q-uart", "fsl,imx21-uart";
1323                                 reg = <0x022a0000 0x4000>;
1324                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1325                                 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1326                                          <&clks IMX6SX_CLK_UART_SERIAL>;
1327                                 clock-names = "ipg", "per";
1328                                 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1329                                 dma-names = "rx", "tx";
1330                                 status = "disabled";
1331                         };
1332
1333                         pwm5: pwm@22a4000 {
1334                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1335                                 reg = <0x022a4000 0x4000>;
1336                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1337                                 clocks = <&clks IMX6SX_CLK_PWM5>,
1338                                          <&clks IMX6SX_CLK_PWM5>;
1339                                 clock-names = "ipg", "per";
1340                                 #pwm-cells = <2>;
1341                         };
1342
1343                         pwm6: pwm@22a8000 {
1344                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1345                                 reg = <0x022a8000 0x4000>;
1346                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1347                                 clocks = <&clks IMX6SX_CLK_PWM6>,
1348                                          <&clks IMX6SX_CLK_PWM6>;
1349                                 clock-names = "ipg", "per";
1350                                 #pwm-cells = <2>;
1351                         };
1352
1353                         pwm7: pwm@22ac000 {
1354                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1355                                 reg = <0x022ac000 0x4000>;
1356                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1357                                 clocks = <&clks IMX6SX_CLK_PWM7>,
1358                                          <&clks IMX6SX_CLK_PWM7>;
1359                                 clock-names = "ipg", "per";
1360                                 #pwm-cells = <2>;
1361                         };
1362
1363                         pwm8: pwm@22b0000 {
1364                                 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1365                                 reg = <0x0022b0000 0x4000>;
1366                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1367                                 clocks = <&clks IMX6SX_CLK_PWM8>,
1368                                          <&clks IMX6SX_CLK_PWM8>;
1369                                 clock-names = "ipg", "per";
1370                                 #pwm-cells = <2>;
1371                         };
1372                 };
1373
1374                 pcie: pcie@8ffc000 {
1375                         compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1376                         reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
1377                         reg-names = "dbi", "config";
1378                         #address-cells = <3>;
1379                         #size-cells = <2>;
1380                         device_type = "pci";
1381                         bus-range = <0x00 0xff>;
1382                         ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
1383                                   0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1384                         num-lanes = <1>;
1385                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1386                         interrupt-names = "msi";
1387                         #interrupt-cells = <1>;
1388                         interrupt-map-mask = <0 0 0 0x7>;
1389                         interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1390                                         <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1391                                         <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1392                                         <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1393                         clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
1394                                  <&clks IMX6SX_CLK_LVDS1_OUT>,
1395                                  <&clks IMX6SX_CLK_PCIE_REF_125M>,
1396                                  <&clks IMX6SX_CLK_DISPLAY_AXI>;
1397                         clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1398                         power-domains = <&pd_disp>, <&pd_pci>;
1399                         power-domain-names = "pcie", "pcie_phy";
1400                         status = "disabled";
1401                 };
1402         };
1403 };