2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "imx6sl-pinfunc.h"
12 #include <dt-bindings/clock/imx6sl-clock.h>
18 * The decompressor and also some bootloaders rely on a
19 * pre-existing /chosen node to be available to insert the
20 * command line and merge other ATAGS info.
21 * Also for U-Boot there must be a pre-existing /memory node.
24 memory { device_type = "memory"; };
51 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
61 fsl,soc-operating-points = <
62 /* ARM kHz SOC-PU uV */
67 clock-latency = <61036>; /* two CLK32 periods */
68 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
69 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
70 <&clks IMX6SL_CLK_PLL1_SYS>;
71 clock-names = "arm", "pll2_pfd2_396m", "step",
72 "pll1_sw", "pll1_sys";
73 arm-supply = <®_arm>;
74 pu-supply = <®_pu>;
75 soc-supply = <®_soc>;
79 intc: interrupt-controller@a01000 {
80 compatible = "arm,cortex-a9-gic";
81 #interrupt-cells = <3>;
83 reg = <0x00a01000 0x1000>,
85 interrupt-parent = <&intc>;
93 compatible = "fixed-clock";
95 clock-frequency = <32768>;
99 compatible = "fixed-clock";
101 clock-frequency = <24000000>;
106 compatible = "fsl,imx6q-tempmon";
107 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-parent = <&gpc>;
109 fsl,tempmon = <&anatop>;
110 fsl,tempmon-data = <&ocotp>;
111 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
115 compatible = "arm,cortex-a9-pmu";
116 interrupt-parent = <&gpc>;
117 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
121 #address-cells = <1>;
123 compatible = "simple-bus";
124 interrupt-parent = <&gpc>;
128 compatible = "mmio-sram";
129 reg = <0x00900000 0x20000>;
130 clocks = <&clks IMX6SL_CLK_OCRAM>;
133 L2: l2-cache@a02000 {
134 compatible = "arm,pl310-cache";
135 reg = <0x00a02000 0x1000>;
136 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
139 arm,tag-latency = <4 2 3>;
140 arm,data-latency = <4 2 3>;
143 aips1: aips-bus@2000000 {
144 compatible = "fsl,aips-bus", "simple-bus";
145 #address-cells = <1>;
147 reg = <0x02000000 0x100000>;
150 spba: spba-bus@2000000 {
151 compatible = "fsl,spba-bus", "simple-bus";
152 #address-cells = <1>;
154 reg = <0x02000000 0x40000>;
157 spdif: spdif@2004000 {
158 compatible = "fsl,imx6sl-spdif",
160 reg = <0x02004000 0x4000>;
161 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
162 dmas = <&sdma 14 18 0>,
164 dma-names = "rx", "tx";
165 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
166 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
167 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
168 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
169 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
170 clock-names = "core", "rxtx0",
178 ecspi1: ecspi@2008000 {
179 #address-cells = <1>;
181 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
182 reg = <0x02008000 0x4000>;
183 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&clks IMX6SL_CLK_ECSPI1>,
185 <&clks IMX6SL_CLK_ECSPI1>;
186 clock-names = "ipg", "per";
190 ecspi2: ecspi@200c000 {
191 #address-cells = <1>;
193 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
194 reg = <0x0200c000 0x4000>;
195 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&clks IMX6SL_CLK_ECSPI2>,
197 <&clks IMX6SL_CLK_ECSPI2>;
198 clock-names = "ipg", "per";
202 ecspi3: ecspi@2010000 {
203 #address-cells = <1>;
205 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
206 reg = <0x02010000 0x4000>;
207 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clks IMX6SL_CLK_ECSPI3>,
209 <&clks IMX6SL_CLK_ECSPI3>;
210 clock-names = "ipg", "per";
214 ecspi4: ecspi@2014000 {
215 #address-cells = <1>;
217 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
218 reg = <0x02014000 0x4000>;
219 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&clks IMX6SL_CLK_ECSPI4>,
221 <&clks IMX6SL_CLK_ECSPI4>;
222 clock-names = "ipg", "per";
226 uart5: serial@2018000 {
227 compatible = "fsl,imx6sl-uart",
228 "fsl,imx6q-uart", "fsl,imx21-uart";
229 reg = <0x02018000 0x4000>;
230 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clks IMX6SL_CLK_UART>,
232 <&clks IMX6SL_CLK_UART_SERIAL>;
233 clock-names = "ipg", "per";
234 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
235 dma-names = "rx", "tx";
239 uart1: serial@2020000 {
240 compatible = "fsl,imx6sl-uart",
241 "fsl,imx6q-uart", "fsl,imx21-uart";
242 reg = <0x02020000 0x4000>;
243 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clks IMX6SL_CLK_UART>,
245 <&clks IMX6SL_CLK_UART_SERIAL>;
246 clock-names = "ipg", "per";
247 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
248 dma-names = "rx", "tx";
252 uart2: serial@2024000 {
253 compatible = "fsl,imx6sl-uart",
254 "fsl,imx6q-uart", "fsl,imx21-uart";
255 reg = <0x02024000 0x4000>;
256 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SL_CLK_UART>,
258 <&clks IMX6SL_CLK_UART_SERIAL>;
259 clock-names = "ipg", "per";
260 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
261 dma-names = "rx", "tx";
266 #sound-dai-cells = <0>;
267 compatible = "fsl,imx6sl-ssi",
269 reg = <0x02028000 0x4000>;
270 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
272 <&clks IMX6SL_CLK_SSI1>;
273 clock-names = "ipg", "baud";
274 dmas = <&sdma 37 1 0>,
276 dma-names = "rx", "tx";
277 fsl,fifo-depth = <15>;
282 #sound-dai-cells = <0>;
283 compatible = "fsl,imx6sl-ssi",
285 reg = <0x0202c000 0x4000>;
286 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
288 <&clks IMX6SL_CLK_SSI2>;
289 clock-names = "ipg", "baud";
290 dmas = <&sdma 41 1 0>,
292 dma-names = "rx", "tx";
293 fsl,fifo-depth = <15>;
298 #sound-dai-cells = <0>;
299 compatible = "fsl,imx6sl-ssi",
301 reg = <0x02030000 0x4000>;
302 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
304 <&clks IMX6SL_CLK_SSI3>;
305 clock-names = "ipg", "baud";
306 dmas = <&sdma 45 1 0>,
308 dma-names = "rx", "tx";
309 fsl,fifo-depth = <15>;
313 uart3: serial@2034000 {
314 compatible = "fsl,imx6sl-uart",
315 "fsl,imx6q-uart", "fsl,imx21-uart";
316 reg = <0x02034000 0x4000>;
317 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&clks IMX6SL_CLK_UART>,
319 <&clks IMX6SL_CLK_UART_SERIAL>;
320 clock-names = "ipg", "per";
321 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
322 dma-names = "rx", "tx";
326 uart4: serial@2038000 {
327 compatible = "fsl,imx6sl-uart",
328 "fsl,imx6q-uart", "fsl,imx21-uart";
329 reg = <0x02038000 0x4000>;
330 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clks IMX6SL_CLK_UART>,
332 <&clks IMX6SL_CLK_UART_SERIAL>;
333 clock-names = "ipg", "per";
334 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
335 dma-names = "rx", "tx";
342 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
343 reg = <0x02080000 0x4000>;
344 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6SL_CLK_PWM1>,
346 <&clks IMX6SL_CLK_PWM1>;
347 clock-names = "ipg", "per";
352 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
353 reg = <0x02084000 0x4000>;
354 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6SL_CLK_PWM2>,
356 <&clks IMX6SL_CLK_PWM2>;
357 clock-names = "ipg", "per";
362 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
363 reg = <0x02088000 0x4000>;
364 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&clks IMX6SL_CLK_PWM3>,
366 <&clks IMX6SL_CLK_PWM3>;
367 clock-names = "ipg", "per";
372 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
373 reg = <0x0208c000 0x4000>;
374 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clks IMX6SL_CLK_PWM4>,
376 <&clks IMX6SL_CLK_PWM4>;
377 clock-names = "ipg", "per";
381 compatible = "fsl,imx6sl-gpt";
382 reg = <0x02098000 0x4000>;
383 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&clks IMX6SL_CLK_GPT>,
385 <&clks IMX6SL_CLK_GPT_SERIAL>;
386 clock-names = "ipg", "per";
389 gpio1: gpio@209c000 {
390 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
391 reg = <0x0209c000 0x4000>;
392 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
393 <0 67 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
399 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
400 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
401 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
402 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
403 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
406 gpio2: gpio@20a0000 {
407 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
408 reg = <0x020a0000 0x4000>;
409 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
410 <0 69 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
416 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
417 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
418 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
419 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
420 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
421 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
424 gpio3: gpio@20a4000 {
425 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
426 reg = <0x020a4000 0x4000>;
427 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
428 <0 71 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
434 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
435 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
436 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
437 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
438 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
439 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
443 gpio4: gpio@20a8000 {
444 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
445 reg = <0x020a8000 0x4000>;
446 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
447 <0 73 IRQ_TYPE_LEVEL_HIGH>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
453 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
454 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
455 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
456 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
457 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
458 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
459 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
460 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
461 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
462 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
463 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
464 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
465 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
466 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
469 gpio5: gpio@20ac000 {
470 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
471 reg = <0x020ac000 0x4000>;
472 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
473 <0 75 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
479 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
480 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
481 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
482 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
483 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
484 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
485 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
486 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
487 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
492 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
493 reg = <0x020b8000 0x4000>;
494 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clks IMX6SL_CLK_DUMMY>;
499 wdog1: wdog@20bc000 {
500 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
501 reg = <0x020bc000 0x4000>;
502 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6SL_CLK_DUMMY>;
506 wdog2: wdog@20c0000 {
507 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
508 reg = <0x020c0000 0x4000>;
509 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clks IMX6SL_CLK_DUMMY>;
515 compatible = "fsl,imx6sl-ccm";
516 reg = <0x020c4000 0x4000>;
517 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
518 <0 88 IRQ_TYPE_LEVEL_HIGH>;
522 anatop: anatop@20c8000 {
523 compatible = "fsl,imx6sl-anatop",
525 "syscon", "simple-bus";
526 reg = <0x020c8000 0x1000>;
527 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
528 <0 54 IRQ_TYPE_LEVEL_HIGH>,
529 <0 127 IRQ_TYPE_LEVEL_HIGH>;
530 #address-cells = <1>;
533 regulator-1p1@20c8110 {
535 compatible = "fsl,anatop-regulator";
536 regulator-name = "vdd1p1";
537 regulator-min-microvolt = <800000>;
538 regulator-max-microvolt = <1375000>;
540 anatop-reg-offset = <0x110>;
541 anatop-vol-bit-shift = <8>;
542 anatop-vol-bit-width = <5>;
543 anatop-min-bit-val = <4>;
544 anatop-min-voltage = <800000>;
545 anatop-max-voltage = <1375000>;
546 anatop-enable-bit = <0>;
549 regulator-3p0@20c8120 {
551 compatible = "fsl,anatop-regulator";
552 regulator-name = "vdd3p0";
553 regulator-min-microvolt = <2800000>;
554 regulator-max-microvolt = <3150000>;
556 anatop-reg-offset = <0x120>;
557 anatop-vol-bit-shift = <8>;
558 anatop-vol-bit-width = <5>;
559 anatop-min-bit-val = <0>;
560 anatop-min-voltage = <2625000>;
561 anatop-max-voltage = <3400000>;
562 anatop-enable-bit = <0>;
565 regulator-2p5@20c8130 {
567 compatible = "fsl,anatop-regulator";
568 regulator-name = "vdd2p5";
569 regulator-min-microvolt = <2100000>;
570 regulator-max-microvolt = <2850000>;
572 anatop-reg-offset = <0x130>;
573 anatop-vol-bit-shift = <8>;
574 anatop-vol-bit-width = <5>;
575 anatop-min-bit-val = <0>;
576 anatop-min-voltage = <2100000>;
577 anatop-max-voltage = <2850000>;
578 anatop-enable-bit = <0>;
581 reg_arm: regulator-vddcore@20c8140 {
583 compatible = "fsl,anatop-regulator";
584 regulator-name = "vddarm";
585 regulator-min-microvolt = <725000>;
586 regulator-max-microvolt = <1450000>;
588 anatop-reg-offset = <0x140>;
589 anatop-vol-bit-shift = <0>;
590 anatop-vol-bit-width = <5>;
591 anatop-delay-reg-offset = <0x170>;
592 anatop-delay-bit-shift = <24>;
593 anatop-delay-bit-width = <2>;
594 anatop-min-bit-val = <1>;
595 anatop-min-voltage = <725000>;
596 anatop-max-voltage = <1450000>;
599 reg_pu: regulator-vddpu@20c8140 {
601 compatible = "fsl,anatop-regulator";
602 regulator-name = "vddpu";
603 regulator-min-microvolt = <725000>;
604 regulator-max-microvolt = <1450000>;
606 anatop-reg-offset = <0x140>;
607 anatop-vol-bit-shift = <9>;
608 anatop-vol-bit-width = <5>;
609 anatop-delay-reg-offset = <0x170>;
610 anatop-delay-bit-shift = <26>;
611 anatop-delay-bit-width = <2>;
612 anatop-min-bit-val = <1>;
613 anatop-min-voltage = <725000>;
614 anatop-max-voltage = <1450000>;
617 reg_soc: regulator-vddsoc@20c8140 {
619 compatible = "fsl,anatop-regulator";
620 regulator-name = "vddsoc";
621 regulator-min-microvolt = <725000>;
622 regulator-max-microvolt = <1450000>;
624 anatop-reg-offset = <0x140>;
625 anatop-vol-bit-shift = <18>;
626 anatop-vol-bit-width = <5>;
627 anatop-delay-reg-offset = <0x170>;
628 anatop-delay-bit-shift = <28>;
629 anatop-delay-bit-width = <2>;
630 anatop-min-bit-val = <1>;
631 anatop-min-voltage = <725000>;
632 anatop-max-voltage = <1450000>;
636 usbphy1: usbphy@20c9000 {
637 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
638 reg = <0x020c9000 0x1000>;
639 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&clks IMX6SL_CLK_USBPHY1>;
641 fsl,anatop = <&anatop>;
644 usbphy2: usbphy@20ca000 {
645 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
646 reg = <0x020ca000 0x1000>;
647 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clks IMX6SL_CLK_USBPHY2>;
649 fsl,anatop = <&anatop>;
653 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
654 reg = <0x020cc000 0x4000>;
656 snvs_rtc: snvs-rtc-lp {
657 compatible = "fsl,sec-v4.0-mon-rtc-lp";
660 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
661 <0 20 IRQ_TYPE_LEVEL_HIGH>;
664 snvs_poweroff: snvs-poweroff {
665 compatible = "syscon-poweroff";
674 epit1: epit@20d0000 {
675 reg = <0x020d0000 0x4000>;
676 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
679 epit2: epit@20d4000 {
680 reg = <0x020d4000 0x4000>;
681 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
685 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
686 reg = <0x020d8000 0x4000>;
687 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
688 <0 96 IRQ_TYPE_LEVEL_HIGH>;
693 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
694 reg = <0x020dc000 0x4000>;
695 interrupt-controller;
696 #interrupt-cells = <3>;
697 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
698 interrupt-parent = <&intc>;
699 pu-supply = <®_pu>;
700 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
701 <&clks IMX6SL_CLK_GPU2D_PODF>;
702 #power-domain-cells = <1>;
705 gpr: iomuxc-gpr@20e0000 {
706 compatible = "fsl,imx6sl-iomuxc-gpr",
707 "fsl,imx6q-iomuxc-gpr", "syscon";
708 reg = <0x020e0000 0x38>;
711 iomuxc: iomuxc@20e0000 {
712 compatible = "fsl,imx6sl-iomuxc";
713 reg = <0x020e0000 0x4000>;
717 reg = <0x020e4000 0x4000>;
718 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
722 reg = <0x020e8000 0x4000>;
723 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
727 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
728 reg = <0x020ec000 0x4000>;
729 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&clks IMX6SL_CLK_SDMA>,
731 <&clks IMX6SL_CLK_SDMA>;
732 clock-names = "ipg", "ahb";
734 /* imx6sl reuses imx6q sdma firmware */
735 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
739 reg = <0x020f0000 0x4000>;
740 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
744 reg = <0x020f4000 0x4000>;
745 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
748 lcdif: lcdif@20f8000 {
749 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
750 reg = <0x020f8000 0x4000>;
751 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
753 <&clks IMX6SL_CLK_LCDIF_AXI>,
754 <&clks IMX6SL_CLK_DUMMY>;
755 clock-names = "pix", "axi", "disp_axi";
760 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
761 reg = <0x020fc000 0x4000>;
762 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
763 <0 100 IRQ_TYPE_LEVEL_HIGH>,
764 <0 101 IRQ_TYPE_LEVEL_HIGH>;
768 aips2: aips-bus@2100000 {
769 compatible = "fsl,aips-bus", "simple-bus";
770 #address-cells = <1>;
772 reg = <0x02100000 0x100000>;
775 usbotg1: usb@2184000 {
776 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
777 reg = <0x02184000 0x200>;
778 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clks IMX6SL_CLK_USBOH3>;
780 fsl,usbphy = <&usbphy1>;
781 fsl,usbmisc = <&usbmisc 0>;
782 ahb-burst-config = <0x0>;
783 tx-burst-size-dword = <0x10>;
784 rx-burst-size-dword = <0x10>;
788 usbotg2: usb@2184200 {
789 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
790 reg = <0x02184200 0x200>;
791 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clks IMX6SL_CLK_USBOH3>;
793 fsl,usbphy = <&usbphy2>;
794 fsl,usbmisc = <&usbmisc 1>;
795 ahb-burst-config = <0x0>;
796 tx-burst-size-dword = <0x10>;
797 rx-burst-size-dword = <0x10>;
802 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
803 reg = <0x02184400 0x200>;
804 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clks IMX6SL_CLK_USBOH3>;
806 fsl,usbmisc = <&usbmisc 2>;
808 ahb-burst-config = <0x0>;
809 tx-burst-size-dword = <0x10>;
810 rx-burst-size-dword = <0x10>;
814 usbmisc: usbmisc@2184800 {
816 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
817 reg = <0x02184800 0x200>;
818 clocks = <&clks IMX6SL_CLK_USBOH3>;
821 fec: ethernet@2188000 {
822 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
823 reg = <0x02188000 0x4000>;
824 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clks IMX6SL_CLK_ENET>,
826 <&clks IMX6SL_CLK_ENET_REF>;
827 clock-names = "ipg", "ahb";
831 usdhc1: usdhc@2190000 {
832 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
833 reg = <0x02190000 0x4000>;
834 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clks IMX6SL_CLK_USDHC1>,
836 <&clks IMX6SL_CLK_USDHC1>,
837 <&clks IMX6SL_CLK_USDHC1>;
838 clock-names = "ipg", "ahb", "per";
843 usdhc2: usdhc@2194000 {
844 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
845 reg = <0x02194000 0x4000>;
846 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&clks IMX6SL_CLK_USDHC2>,
848 <&clks IMX6SL_CLK_USDHC2>,
849 <&clks IMX6SL_CLK_USDHC2>;
850 clock-names = "ipg", "ahb", "per";
855 usdhc3: usdhc@2198000 {
856 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
857 reg = <0x02198000 0x4000>;
858 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&clks IMX6SL_CLK_USDHC3>,
860 <&clks IMX6SL_CLK_USDHC3>,
861 <&clks IMX6SL_CLK_USDHC3>;
862 clock-names = "ipg", "ahb", "per";
867 usdhc4: usdhc@219c000 {
868 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
869 reg = <0x0219c000 0x4000>;
870 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX6SL_CLK_USDHC4>,
872 <&clks IMX6SL_CLK_USDHC4>,
873 <&clks IMX6SL_CLK_USDHC4>;
874 clock-names = "ipg", "ahb", "per";
880 #address-cells = <1>;
882 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
883 reg = <0x021a0000 0x4000>;
884 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6SL_CLK_I2C1>;
890 #address-cells = <1>;
892 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
893 reg = <0x021a4000 0x4000>;
894 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&clks IMX6SL_CLK_I2C2>;
900 #address-cells = <1>;
902 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
903 reg = <0x021a8000 0x4000>;
904 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&clks IMX6SL_CLK_I2C3>;
910 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
911 reg = <0x021b0000 0x4000>;
915 reg = <0x021b4000 0x4000>;
916 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
920 #address-cells = <2>;
922 reg = <0x021b8000 0x4000>;
923 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
924 fsl,weim-cs-gpr = <&gpr>;
928 ocotp: ocotp@21bc000 {
929 compatible = "fsl,imx6sl-ocotp", "syscon";
930 reg = <0x021bc000 0x4000>;
931 clocks = <&clks IMX6SL_CLK_OCOTP>;
934 audmux: audmux@21d8000 {
935 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
936 reg = <0x021d8000 0x4000>;