1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2018 Protonic Holland
4 * Copyright (c) 2020 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
8 #include <dt-bindings/gpio/gpio.h>
12 model = "Protonic WD3 board";
13 compatible = "prt,prtwd3", "fsl,imx6qp";
20 device_type = "memory";
21 reg = <0x10000000 0x20000000>;
25 device_type = "memory";
26 reg = <0x80000000 0x20000000>;
29 clock_ksz8081: clock-ksz8081 {
30 compatible = "fixed-clock";
32 clock-frequency = <50000000>;
35 clock_ksz9031: clock-ksz9031 {
36 compatible = "fixed-clock";
38 clock-frequency = <25000000>;
41 clock_mcp251xfd: clock-mcp251xfd {
42 compatible = "fixed-clock";
44 clock-frequency = <20000000>;
47 clock_sja1105: clock-sja1105 {
48 compatible = "fixed-clock";
50 clock-frequency = <25000000>;
54 compatible = "virtual,mdio-gpio";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_mdio>;
60 gpios = <&gpio5 6 GPIO_ACTIVE_HIGH
61 &gpio5 7 GPIO_ACTIVE_HIGH>;
63 /* Microchip KSZ8081 */
64 usbeth_phy: ethernet-phy@3 {
67 interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>;
68 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
69 reset-assert-us = <500>;
70 reset-deassert-us = <1000>;
71 clocks = <&clock_ksz8081>;
72 clock-names = "rmii-ref";
73 micrel,led-mode = <0>;
76 tja1102_phy0: ethernet-phy@4 {
79 interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
80 reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
81 reset-assert-us = <20>;
82 reset-deassert-us = <2000>;
86 tja1102_phy1: ethernet-phy@5 {
89 interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
94 reg_5v0: regulator-5v0 {
95 compatible = "regulator-fixed";
96 regulator-name = "5v0";
97 regulator-min-microvolt = <5000000>;
98 regulator-max-microvolt = <5000000>;
101 reg_otg_vbus: regulator-otg-vbus {
102 compatible = "regulator-fixed";
103 regulator-name = "otg-vbus";
104 regulator-min-microvolt = <5000000>;
105 regulator-max-microvolt = <5000000>;
106 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
110 usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq {
111 compatible = "mmc-pwrseq-simple";
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_wifi_npd>;
114 reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_can1>;
121 xceiver-supply = <®_5v0>;
126 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_ecspi2>;
132 compatible = "nxp,sja1105q";
134 spi-max-frequency = <4000000>;
135 spi-rx-delay-us = <1>;
136 spi-tx-delay-us = <1>;
139 reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
141 clocks = <&clock_sja1105>;
144 #address-cells = <1>;
150 phy-handle = <&usbeth_phy>;
157 phy-handle = <&tja1102_phy1>;
164 phy-handle = <&tja1102_phy0>;
172 phy-handle = <&rgmii_phy>;
173 phy-mode = "rgmii-id";
180 phy-mode = "rgmii-id";
192 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_ecspi3>;
198 compatible = "microchip,mcp251xfd";
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_can2>;
202 clocks = <&clock_mcp251xfd>;
203 spi-max-frequency = <10000000>;
204 interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_enet>;
211 assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>;
212 assigned-clock-rates = <125000000>;
223 #address-cells = <1>;
226 /* Microchip KSZ9031 */
227 rgmii_phy: ethernet-phy@2 {
230 interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>;
231 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
232 reset-assert-us = <10000>;
233 reset-deassert-us = <1000>;
235 clocks = <&clock_ksz9031>;
242 "", "SD1_CD", "", "", "", "", "", "",
243 "", "", "", "", "", "", "", "",
244 "", "", "", "", "", "", "", "",
245 "", "PHY3_RESET", "", "", "PHY3_INT", "", "", "";
250 "", "", "", "", "", "", "", "",
251 "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3",
252 "BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
253 "", "", "", "", "", "", "", "",
254 "", "", "ECSPI2_SS0", "", "", "", "", "";
259 "", "", "", "", "", "", "", "",
260 "", "", "", "", "", "", "", "",
261 "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "",
262 "", "", "", "", "", "", "", "";
267 "", "", "", "", "", "", "", "",
268 "", "", "", "", "CAN1_SR", "CAN2_SR", "", "",
269 "", "", "", "", "", "", "", "",
270 "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", "";
275 "", "", "", "", "", "SW_RESET", "", "",
276 "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET",
277 "PHY0_INT", "", "", "",
278 "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD",
280 "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ",
281 "DISP0_EN", "CAM_GPIO0";
286 "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD",
287 "CAM_LOCK", "", "POWER_TG",
288 "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "",
289 "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1",
290 "USB_ETH_CHG_ID2", "", "", "", "", "", "", "",
291 "", "", "", "", "", "", "", "";
295 clock-frequency = <100000>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pinctrl_i2c1>;
300 /* additional i2c devices are added automatically by the boot loader */
305 compatible = "ti,ads1015";
307 #address-cells = <1>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_uart4>;
346 vbus-supply = <®_otg_vbus>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_usbotg>;
351 disable-over-current;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_usdhc1>;
366 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_usdhc2>;
380 mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
382 #address-cells = <1>;
387 compatible = "brcm,bcm4329-fmac";
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_usdhc3>;
403 pinctrl_can1: can1grp {
405 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000
406 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008
408 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008
412 pinctrl_can2: can2grp {
415 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
417 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070
421 pinctrl_ecspi2: ecspi2grp {
423 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
424 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
425 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
426 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
430 pinctrl_ecspi3: ecspi3grp {
432 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
433 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
434 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
436 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
440 pinctrl_enet: enetgrp {
442 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
443 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
444 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
445 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
446 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
447 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
448 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
449 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
450 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
451 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
452 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
453 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
455 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
456 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
458 /* Configure clock provider for RGMII ref clock */
459 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
460 /* Configure clock consumer for RGMII ref clock */
461 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
463 /* SJA1105Q switch reset */
464 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030
466 /* phy3/rgmii_phy reset */
467 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030
468 /* phy3/rgmii_phy int */
469 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000
473 pinctrl_i2c1: i2c1grp {
475 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1
476 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1
480 pinctrl_mdio: mdiogrp {
482 /* phy0/usbeth_phy reset */
483 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030
484 /* phy0/usbeth_phy int */
485 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
487 /* phy12/tja1102_phy0 reset */
488 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030
489 /* phy12/tja1102_phy0 int */
490 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1
491 /* phy12/tja1102_phy0 enable. Set 100K pull-up */
492 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030
496 pinctrl_uart4: uart4grp {
498 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
499 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
503 pinctrl_usbotg: usbotggrp {
505 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
506 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
510 pinctrl_usdhc1: usdhc1grp {
512 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
513 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
514 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
515 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
516 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
517 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
518 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0
522 pinctrl_usdhc2: usdhc2grp {
524 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
525 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
526 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
527 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
528 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
529 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
533 pinctrl_usdhc3: usdhc3grp {
535 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099
536 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099
537 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099
538 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099
539 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099
540 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099
541 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099
542 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099
543 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099
544 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099
545 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1
549 pinctrl_wifi_npd: wifinpd {
552 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069