1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
54 compatible = "fsl,imx-ckil", "fixed-clock";
56 clock-frequency = <32768>;
60 compatible = "fsl,imx-ckih1", "fixed-clock";
62 clock-frequency = <0>;
66 compatible = "fsl,imx-osc", "fixed-clock";
68 clock-frequency = <24000000>;
73 compatible = "fsl,imx6q-tempmon";
74 interrupt-parent = <&gpc>;
75 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
76 fsl,tempmon = <&anatop>;
77 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
78 nvmem-cell-names = "calib", "temp_grade";
79 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
80 #thermal-sensor-cells = <0>;
86 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
99 lvds0_mux_0: endpoint {
100 remote-endpoint = <&ipu1_di0_lvds0>;
107 lvds0_mux_1: endpoint {
108 remote-endpoint = <&ipu1_di1_lvds0>;
114 #address-cells = <1>;
122 lvds1_mux_0: endpoint {
123 remote-endpoint = <&ipu1_di0_lvds1>;
130 lvds1_mux_1: endpoint {
131 remote-endpoint = <&ipu1_di1_lvds1>;
138 compatible = "arm,cortex-a9-pmu";
139 interrupt-parent = <&gpc>;
140 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
143 usbphynop1: usbphynop1 {
144 compatible = "usb-nop-xceiv";
148 usbphynop2: usbphynop2 {
149 compatible = "usb-nop-xceiv";
154 #address-cells = <1>;
156 compatible = "simple-bus";
157 interrupt-parent = <&gpc>;
160 dma_apbh: dma-apbh@110000 {
161 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
162 reg = <0x00110000 0x2000>;
163 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
164 <0 13 IRQ_TYPE_LEVEL_HIGH>,
165 <0 13 IRQ_TYPE_LEVEL_HIGH>,
166 <0 13 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
170 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
173 gpmi: gpmi-nand@112000 {
174 compatible = "fsl,imx6q-gpmi-nand";
175 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
176 reg-names = "gpmi-nand", "bch";
177 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "bch";
179 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
180 <&clks IMX6QDL_CLK_GPMI_APB>,
181 <&clks IMX6QDL_CLK_GPMI_BCH>,
182 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
183 <&clks IMX6QDL_CLK_PER1_BCH>;
184 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
185 "gpmi_bch_apb", "per1_bch";
186 dmas = <&dma_apbh 0>;
192 #address-cells = <1>;
194 reg = <0x00120000 0x9000>;
195 interrupts = <0 115 0x04>;
197 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
198 <&clks IMX6QDL_CLK_HDMI_ISFR>;
199 clock-names = "iahb", "isfr";
205 hdmi_mux_0: endpoint {
206 remote-endpoint = <&ipu1_di0_hdmi>;
213 hdmi_mux_1: endpoint {
214 remote-endpoint = <&ipu1_di1_hdmi>;
220 compatible = "vivante,gc";
221 reg = <0x00130000 0x4000>;
222 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
224 <&clks IMX6QDL_CLK_GPU3D_CORE>,
225 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
226 clock-names = "bus", "core", "shader";
227 power-domains = <&pd_pu>;
228 #cooling-cells = <2>;
232 compatible = "vivante,gc";
233 reg = <0x00134000 0x4000>;
234 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
236 <&clks IMX6QDL_CLK_GPU2D_CORE>;
237 clock-names = "bus", "core";
238 power-domains = <&pd_pu>;
239 #cooling-cells = <2>;
243 compatible = "arm,cortex-a9-twd-timer";
244 reg = <0x00a00600 0x20>;
245 interrupts = <1 13 0xf01>;
246 interrupt-parent = <&intc>;
247 clocks = <&clks IMX6QDL_CLK_TWD>;
250 intc: interrupt-controller@a01000 {
251 compatible = "arm,cortex-a9-gic";
252 #interrupt-cells = <3>;
253 interrupt-controller;
254 reg = <0x00a01000 0x1000>,
256 interrupt-parent = <&intc>;
259 L2: l2-cache@a02000 {
260 compatible = "arm,pl310-cache";
261 reg = <0x00a02000 0x1000>;
262 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
265 arm,tag-latency = <4 2 3>;
266 arm,data-latency = <4 2 3>;
271 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
272 reg = <0x01ffc000 0x04000>,
273 <0x01f00000 0x80000>;
274 reg-names = "dbi", "config";
275 #address-cells = <3>;
278 bus-range = <0x00 0xff>;
279 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
280 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
283 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
284 interrupt-names = "msi";
285 #interrupt-cells = <1>;
286 interrupt-map-mask = <0 0 0 0x7>;
287 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
288 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
289 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
290 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
292 <&clks IMX6QDL_CLK_LVDS1_GATE>,
293 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
294 clock-names = "pcie", "pcie_bus", "pcie_phy";
298 bus@2000000 { /* AIPS1 */
299 compatible = "fsl,aips-bus", "simple-bus";
300 #address-cells = <1>;
302 reg = <0x02000000 0x100000>;
306 compatible = "fsl,spba-bus", "simple-bus";
307 #address-cells = <1>;
309 reg = <0x02000000 0x40000>;
312 spdif: spdif@2004000 {
313 compatible = "fsl,imx35-spdif";
314 reg = <0x02004000 0x4000>;
315 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
316 dmas = <&sdma 14 18 0>,
318 dma-names = "rx", "tx";
319 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
320 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
321 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
322 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
323 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
324 clock-names = "core", "rxtx0",
332 ecspi1: spi@2008000 {
333 #address-cells = <1>;
335 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
336 reg = <0x02008000 0x4000>;
337 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
339 <&clks IMX6QDL_CLK_ECSPI1>;
340 clock-names = "ipg", "per";
341 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
342 dma-names = "rx", "tx";
346 ecspi2: spi@200c000 {
347 #address-cells = <1>;
349 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
350 reg = <0x0200c000 0x4000>;
351 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
353 <&clks IMX6QDL_CLK_ECSPI2>;
354 clock-names = "ipg", "per";
355 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
356 dma-names = "rx", "tx";
360 ecspi3: spi@2010000 {
361 #address-cells = <1>;
363 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
364 reg = <0x02010000 0x4000>;
365 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
367 <&clks IMX6QDL_CLK_ECSPI3>;
368 clock-names = "ipg", "per";
369 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
370 dma-names = "rx", "tx";
374 ecspi4: spi@2014000 {
375 #address-cells = <1>;
377 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
378 reg = <0x02014000 0x4000>;
379 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
381 <&clks IMX6QDL_CLK_ECSPI4>;
382 clock-names = "ipg", "per";
383 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
384 dma-names = "rx", "tx";
388 uart1: serial@2020000 {
389 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
390 reg = <0x02020000 0x4000>;
391 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
393 <&clks IMX6QDL_CLK_UART_SERIAL>;
394 clock-names = "ipg", "per";
395 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
396 dma-names = "rx", "tx";
401 #sound-dai-cells = <0>;
402 compatible = "fsl,imx35-esai";
403 reg = <0x02024000 0x4000>;
404 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
406 <&clks IMX6QDL_CLK_ESAI_MEM>,
407 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
408 <&clks IMX6QDL_CLK_ESAI_IPG>,
409 <&clks IMX6QDL_CLK_SPBA>;
410 clock-names = "core", "mem", "extal", "fsys", "spba";
411 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
412 dma-names = "rx", "tx";
417 #sound-dai-cells = <0>;
418 compatible = "fsl,imx6q-ssi",
420 reg = <0x02028000 0x4000>;
421 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
423 <&clks IMX6QDL_CLK_SSI1>;
424 clock-names = "ipg", "baud";
425 dmas = <&sdma 37 1 0>,
427 dma-names = "rx", "tx";
428 fsl,fifo-depth = <15>;
433 #sound-dai-cells = <0>;
434 compatible = "fsl,imx6q-ssi",
436 reg = <0x0202c000 0x4000>;
437 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
439 <&clks IMX6QDL_CLK_SSI2>;
440 clock-names = "ipg", "baud";
441 dmas = <&sdma 41 1 0>,
443 dma-names = "rx", "tx";
444 fsl,fifo-depth = <15>;
449 #sound-dai-cells = <0>;
450 compatible = "fsl,imx6q-ssi",
452 reg = <0x02030000 0x4000>;
453 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
455 <&clks IMX6QDL_CLK_SSI3>;
456 clock-names = "ipg", "baud";
457 dmas = <&sdma 45 1 0>,
459 dma-names = "rx", "tx";
460 fsl,fifo-depth = <15>;
465 compatible = "fsl,imx53-asrc";
466 reg = <0x02034000 0x4000>;
467 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
469 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
470 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
471 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
472 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
473 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
474 <&clks IMX6QDL_CLK_SPBA>;
475 clock-names = "mem", "ipg", "asrck_0",
476 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
477 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
478 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
479 "asrck_d", "asrck_e", "asrck_f", "spba";
480 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
481 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
482 dma-names = "rxa", "rxb", "rxc",
484 fsl,asrc-rate = <48000>;
485 fsl,asrc-width = <16>;
490 reg = <0x0203c000 0x4000>;
495 compatible = "cnm,coda960";
496 reg = <0x02040000 0x3c000>;
497 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
498 <0 3 IRQ_TYPE_LEVEL_HIGH>;
499 interrupt-names = "bit", "jpeg";
500 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
501 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
502 clock-names = "per", "ahb";
503 power-domains = <&pd_pu>;
508 aipstz@207c000 { /* AIPSTZ1 */
509 reg = <0x0207c000 0x4000>;
514 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
515 reg = <0x02080000 0x4000>;
516 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clks IMX6QDL_CLK_IPG>,
518 <&clks IMX6QDL_CLK_PWM1>;
519 clock-names = "ipg", "per";
525 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
526 reg = <0x02084000 0x4000>;
527 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&clks IMX6QDL_CLK_IPG>,
529 <&clks IMX6QDL_CLK_PWM2>;
530 clock-names = "ipg", "per";
536 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
537 reg = <0x02088000 0x4000>;
538 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&clks IMX6QDL_CLK_IPG>,
540 <&clks IMX6QDL_CLK_PWM3>;
541 clock-names = "ipg", "per";
547 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
548 reg = <0x0208c000 0x4000>;
549 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&clks IMX6QDL_CLK_IPG>,
551 <&clks IMX6QDL_CLK_PWM4>;
552 clock-names = "ipg", "per";
556 can1: flexcan@2090000 {
557 compatible = "fsl,imx6q-flexcan";
558 reg = <0x02090000 0x4000>;
559 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
561 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
562 clock-names = "ipg", "per";
563 fsl,stop-mode = <&gpr 0x34 28 0x10 17>;
567 can2: flexcan@2094000 {
568 compatible = "fsl,imx6q-flexcan";
569 reg = <0x02094000 0x4000>;
570 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
572 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
573 clock-names = "ipg", "per";
574 fsl,stop-mode = <&gpr 0x34 29 0x10 18>;
579 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
580 reg = <0x02098000 0x4000>;
581 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
583 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
584 <&clks IMX6QDL_CLK_GPT_3M>;
585 clock-names = "ipg", "per", "osc_per";
588 gpio1: gpio@209c000 {
589 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
590 reg = <0x0209c000 0x4000>;
591 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
592 <0 67 IRQ_TYPE_LEVEL_HIGH>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
599 gpio2: gpio@20a0000 {
600 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
601 reg = <0x020a0000 0x4000>;
602 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
603 <0 69 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
610 gpio3: gpio@20a4000 {
611 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
612 reg = <0x020a4000 0x4000>;
613 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
614 <0 71 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
621 gpio4: gpio@20a8000 {
622 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
623 reg = <0x020a8000 0x4000>;
624 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
625 <0 73 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-controller;
629 #interrupt-cells = <2>;
632 gpio5: gpio@20ac000 {
633 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
634 reg = <0x020ac000 0x4000>;
635 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
636 <0 75 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-controller;
640 #interrupt-cells = <2>;
643 gpio6: gpio@20b0000 {
644 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
645 reg = <0x020b0000 0x4000>;
646 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
647 <0 77 IRQ_TYPE_LEVEL_HIGH>;
650 interrupt-controller;
651 #interrupt-cells = <2>;
654 gpio7: gpio@20b4000 {
655 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
656 reg = <0x020b4000 0x4000>;
657 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
658 <0 79 IRQ_TYPE_LEVEL_HIGH>;
661 interrupt-controller;
662 #interrupt-cells = <2>;
665 kpp: keypad@20b8000 {
666 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
667 reg = <0x020b8000 0x4000>;
668 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&clks IMX6QDL_CLK_IPG>;
673 wdog1: watchdog@20bc000 {
674 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
675 reg = <0x020bc000 0x4000>;
676 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&clks IMX6QDL_CLK_IPG>;
680 wdog2: watchdog@20c0000 {
681 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
682 reg = <0x020c0000 0x4000>;
683 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&clks IMX6QDL_CLK_IPG>;
688 clks: clock-controller@20c4000 {
689 compatible = "fsl,imx6q-ccm";
690 reg = <0x020c4000 0x4000>;
691 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
692 <0 88 IRQ_TYPE_LEVEL_HIGH>;
696 anatop: anatop@20c8000 {
697 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
698 reg = <0x020c8000 0x1000>;
699 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
700 <0 54 IRQ_TYPE_LEVEL_HIGH>,
701 <0 127 IRQ_TYPE_LEVEL_HIGH>;
703 reg_vdd1p1: regulator-1p1 {
704 compatible = "fsl,anatop-regulator";
705 regulator-name = "vdd1p1";
706 regulator-min-microvolt = <1000000>;
707 regulator-max-microvolt = <1200000>;
709 anatop-reg-offset = <0x110>;
710 anatop-vol-bit-shift = <8>;
711 anatop-vol-bit-width = <5>;
712 anatop-min-bit-val = <4>;
713 anatop-min-voltage = <800000>;
714 anatop-max-voltage = <1375000>;
715 anatop-enable-bit = <0>;
718 reg_vdd3p0: regulator-3p0 {
719 compatible = "fsl,anatop-regulator";
720 regulator-name = "vdd3p0";
721 regulator-min-microvolt = <2800000>;
722 regulator-max-microvolt = <3150000>;
724 anatop-reg-offset = <0x120>;
725 anatop-vol-bit-shift = <8>;
726 anatop-vol-bit-width = <5>;
727 anatop-min-bit-val = <0>;
728 anatop-min-voltage = <2625000>;
729 anatop-max-voltage = <3400000>;
730 anatop-enable-bit = <0>;
733 reg_vdd2p5: regulator-2p5 {
734 compatible = "fsl,anatop-regulator";
735 regulator-name = "vdd2p5";
736 regulator-min-microvolt = <2250000>;
737 regulator-max-microvolt = <2750000>;
739 anatop-reg-offset = <0x130>;
740 anatop-vol-bit-shift = <8>;
741 anatop-vol-bit-width = <5>;
742 anatop-min-bit-val = <0>;
743 anatop-min-voltage = <2100000>;
744 anatop-max-voltage = <2875000>;
745 anatop-enable-bit = <0>;
748 reg_arm: regulator-vddcore {
749 compatible = "fsl,anatop-regulator";
750 regulator-name = "vddarm";
751 regulator-min-microvolt = <725000>;
752 regulator-max-microvolt = <1450000>;
754 anatop-reg-offset = <0x140>;
755 anatop-vol-bit-shift = <0>;
756 anatop-vol-bit-width = <5>;
757 anatop-delay-reg-offset = <0x170>;
758 anatop-delay-bit-shift = <24>;
759 anatop-delay-bit-width = <2>;
760 anatop-min-bit-val = <1>;
761 anatop-min-voltage = <725000>;
762 anatop-max-voltage = <1450000>;
765 reg_pu: regulator-vddpu {
766 compatible = "fsl,anatop-regulator";
767 regulator-name = "vddpu";
768 regulator-min-microvolt = <725000>;
769 regulator-max-microvolt = <1450000>;
770 regulator-enable-ramp-delay = <150>;
771 anatop-reg-offset = <0x140>;
772 anatop-vol-bit-shift = <9>;
773 anatop-vol-bit-width = <5>;
774 anatop-delay-reg-offset = <0x170>;
775 anatop-delay-bit-shift = <26>;
776 anatop-delay-bit-width = <2>;
777 anatop-min-bit-val = <1>;
778 anatop-min-voltage = <725000>;
779 anatop-max-voltage = <1450000>;
782 reg_soc: regulator-vddsoc {
783 compatible = "fsl,anatop-regulator";
784 regulator-name = "vddsoc";
785 regulator-min-microvolt = <725000>;
786 regulator-max-microvolt = <1450000>;
788 anatop-reg-offset = <0x140>;
789 anatop-vol-bit-shift = <18>;
790 anatop-vol-bit-width = <5>;
791 anatop-delay-reg-offset = <0x170>;
792 anatop-delay-bit-shift = <28>;
793 anatop-delay-bit-width = <2>;
794 anatop-min-bit-val = <1>;
795 anatop-min-voltage = <725000>;
796 anatop-max-voltage = <1450000>;
800 usbphy1: usbphy@20c9000 {
801 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
802 reg = <0x020c9000 0x1000>;
803 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
805 fsl,anatop = <&anatop>;
808 usbphy2: usbphy@20ca000 {
809 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
810 reg = <0x020ca000 0x1000>;
811 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
813 fsl,anatop = <&anatop>;
817 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
818 reg = <0x020cc000 0x4000>;
820 snvs_rtc: snvs-rtc-lp {
821 compatible = "fsl,sec-v4.0-mon-rtc-lp";
824 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
825 <0 20 IRQ_TYPE_LEVEL_HIGH>;
828 snvs_poweroff: snvs-poweroff {
829 compatible = "syscon-poweroff";
837 snvs_pwrkey: snvs-powerkey {
838 compatible = "fsl,sec-v4.0-pwrkey";
840 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
841 linux,keycode = <KEY_POWER>;
846 snvs_lpgpr: snvs-lpgpr {
847 compatible = "fsl,imx6q-snvs-lpgpr";
851 epit1: epit@20d0000 { /* EPIT1 */
852 reg = <0x020d0000 0x4000>;
853 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
856 epit2: epit@20d4000 { /* EPIT2 */
857 reg = <0x020d4000 0x4000>;
858 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
861 src: reset-controller@20d8000 {
862 compatible = "fsl,imx6q-src", "fsl,imx51-src";
863 reg = <0x020d8000 0x4000>;
864 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
865 <0 96 IRQ_TYPE_LEVEL_HIGH>;
870 compatible = "fsl,imx6q-gpc";
871 reg = <0x020dc000 0x4000>;
872 interrupt-controller;
873 #interrupt-cells = <3>;
874 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
875 <0 90 IRQ_TYPE_LEVEL_HIGH>;
876 interrupt-parent = <&intc>;
877 clocks = <&clks IMX6QDL_CLK_IPG>;
881 #address-cells = <1>;
886 #power-domain-cells = <0>;
888 pd_pu: power-domain@1 {
890 #power-domain-cells = <0>;
891 power-supply = <®_pu>;
892 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
893 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
894 <&clks IMX6QDL_CLK_GPU2D_CORE>,
895 <&clks IMX6QDL_CLK_GPU2D_AXI>,
896 <&clks IMX6QDL_CLK_OPENVG_AXI>,
897 <&clks IMX6QDL_CLK_VPU_AXI>;
902 gpr: iomuxc-gpr@20e0000 {
903 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
904 reg = <0x20e0000 0x38>;
906 mux: mux-controller {
907 compatible = "mmio-mux";
908 #mux-control-cells = <1>;
912 iomuxc: pinctrl@20e0000 {
913 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
914 reg = <0x20e0000 0x4000>;
917 dcic1: dcic@20e4000 {
918 reg = <0x020e4000 0x4000>;
919 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
922 dcic2: dcic@20e8000 {
923 reg = <0x020e8000 0x4000>;
924 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
928 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
929 reg = <0x020ec000 0x4000>;
930 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6QDL_CLK_IPG>,
932 <&clks IMX6QDL_CLK_SDMA>;
933 clock-names = "ipg", "ahb";
935 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
939 bus@2100000 { /* AIPS2 */
940 compatible = "fsl,aips-bus", "simple-bus";
941 #address-cells = <1>;
943 reg = <0x02100000 0x100000>;
946 crypto: crypto@2100000 {
947 compatible = "fsl,sec-v4.0";
948 #address-cells = <1>;
950 reg = <0x2100000 0x10000>;
951 ranges = <0 0x2100000 0x10000>;
952 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
953 <&clks IMX6QDL_CLK_CAAM_ACLK>,
954 <&clks IMX6QDL_CLK_CAAM_IPG>,
955 <&clks IMX6QDL_CLK_EIM_SLOW>;
956 clock-names = "mem", "aclk", "ipg", "emi_slow";
959 compatible = "fsl,sec-v4.0-job-ring";
960 reg = <0x1000 0x1000>;
961 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
965 compatible = "fsl,sec-v4.0-job-ring";
966 reg = <0x2000 0x1000>;
967 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
971 aipstz@217c000 { /* AIPSTZ2 */
972 reg = <0x0217c000 0x4000>;
975 usbotg: usb@2184000 {
976 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
977 reg = <0x02184000 0x200>;
978 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&clks IMX6QDL_CLK_USBOH3>;
980 fsl,usbphy = <&usbphy1>;
981 fsl,usbmisc = <&usbmisc 0>;
982 ahb-burst-config = <0x0>;
983 tx-burst-size-dword = <0x10>;
984 rx-burst-size-dword = <0x10>;
989 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
990 reg = <0x02184200 0x200>;
991 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&clks IMX6QDL_CLK_USBOH3>;
993 fsl,usbphy = <&usbphy2>;
994 fsl,usbmisc = <&usbmisc 1>;
996 ahb-burst-config = <0x0>;
997 tx-burst-size-dword = <0x10>;
998 rx-burst-size-dword = <0x10>;
1002 usbh2: usb@2184400 {
1003 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1004 reg = <0x02184400 0x200>;
1005 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1007 fsl,usbphy = <&usbphynop1>;
1009 fsl,usbmisc = <&usbmisc 2>;
1011 ahb-burst-config = <0x0>;
1012 tx-burst-size-dword = <0x10>;
1013 rx-burst-size-dword = <0x10>;
1014 status = "disabled";
1017 usbh3: usb@2184600 {
1018 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1019 reg = <0x02184600 0x200>;
1020 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1022 fsl,usbphy = <&usbphynop2>;
1024 fsl,usbmisc = <&usbmisc 3>;
1026 ahb-burst-config = <0x0>;
1027 tx-burst-size-dword = <0x10>;
1028 rx-burst-size-dword = <0x10>;
1029 status = "disabled";
1032 usbmisc: usbmisc@2184800 {
1034 compatible = "fsl,imx6q-usbmisc";
1035 reg = <0x02184800 0x200>;
1036 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1039 fec: ethernet@2188000 {
1040 compatible = "fsl,imx6q-fec";
1041 reg = <0x02188000 0x4000>;
1042 interrupt-names = "int0", "pps";
1043 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1044 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&clks IMX6QDL_CLK_ENET>,
1046 <&clks IMX6QDL_CLK_ENET>,
1047 <&clks IMX6QDL_CLK_ENET_REF>;
1048 clock-names = "ipg", "ahb", "ptp";
1049 fsl,stop-mode = <&gpr 0x34 27>;
1050 status = "disabled";
1054 reg = <0x0218c000 0x4000>;
1055 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1056 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1057 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1060 usdhc1: usdhc@2190000 {
1061 compatible = "fsl,imx6q-usdhc";
1062 reg = <0x02190000 0x4000>;
1063 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1065 <&clks IMX6QDL_CLK_USDHC1>,
1066 <&clks IMX6QDL_CLK_USDHC1>;
1067 clock-names = "ipg", "ahb", "per";
1069 status = "disabled";
1072 usdhc2: usdhc@2194000 {
1073 compatible = "fsl,imx6q-usdhc";
1074 reg = <0x02194000 0x4000>;
1075 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1077 <&clks IMX6QDL_CLK_USDHC2>,
1078 <&clks IMX6QDL_CLK_USDHC2>;
1079 clock-names = "ipg", "ahb", "per";
1081 status = "disabled";
1084 usdhc3: usdhc@2198000 {
1085 compatible = "fsl,imx6q-usdhc";
1086 reg = <0x02198000 0x4000>;
1087 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1089 <&clks IMX6QDL_CLK_USDHC3>,
1090 <&clks IMX6QDL_CLK_USDHC3>;
1091 clock-names = "ipg", "ahb", "per";
1093 status = "disabled";
1096 usdhc4: usdhc@219c000 {
1097 compatible = "fsl,imx6q-usdhc";
1098 reg = <0x0219c000 0x4000>;
1099 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1101 <&clks IMX6QDL_CLK_USDHC4>,
1102 <&clks IMX6QDL_CLK_USDHC4>;
1103 clock-names = "ipg", "ahb", "per";
1105 status = "disabled";
1109 #address-cells = <1>;
1111 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1112 reg = <0x021a0000 0x4000>;
1113 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&clks IMX6QDL_CLK_I2C1>;
1115 status = "disabled";
1119 #address-cells = <1>;
1121 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1122 reg = <0x021a4000 0x4000>;
1123 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&clks IMX6QDL_CLK_I2C2>;
1125 status = "disabled";
1129 #address-cells = <1>;
1131 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1132 reg = <0x021a8000 0x4000>;
1133 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&clks IMX6QDL_CLK_I2C3>;
1135 status = "disabled";
1139 reg = <0x021ac000 0x4000>;
1142 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1143 compatible = "fsl,imx6q-mmdc";
1144 reg = <0x021b0000 0x4000>;
1145 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1148 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1149 compatible = "fsl,imx6q-mmdc";
1150 reg = <0x021b4000 0x4000>;
1151 status = "disabled";
1154 weim: weim@21b8000 {
1155 #address-cells = <2>;
1157 compatible = "fsl,imx6q-weim";
1158 reg = <0x021b8000 0x4000>;
1159 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1161 fsl,weim-cs-gpr = <&gpr>;
1162 status = "disabled";
1165 ocotp: ocotp-ctrl@21bc000 {
1166 compatible = "fsl,imx6q-ocotp", "syscon";
1167 reg = <0x021bc000 0x4000>;
1168 clocks = <&clks IMX6QDL_CLK_IIM>;
1169 #address-cells = <1>;
1172 cpu_speed_grade: speed-grade@10 {
1176 tempmon_calib: calib@38 {
1180 tempmon_temp_grade: temp-grade@20 {
1185 tzasc@21d0000 { /* TZASC1 */
1186 reg = <0x021d0000 0x4000>;
1187 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1190 tzasc@21d4000 { /* TZASC2 */
1191 reg = <0x021d4000 0x4000>;
1192 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1195 audmux: audmux@21d8000 {
1196 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1197 reg = <0x021d8000 0x4000>;
1198 status = "disabled";
1201 mipi_csi: mipi@21dc000 {
1202 compatible = "fsl,imx6-mipi-csi2";
1203 reg = <0x021dc000 0x4000>;
1204 #address-cells = <1>;
1206 interrupts = <0 100 0x04>, <0 101 0x04>;
1207 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1208 <&clks IMX6QDL_CLK_VIDEO_27M>,
1209 <&clks IMX6QDL_CLK_EIM_PODF>;
1210 clock-names = "dphy", "ref", "pix";
1211 status = "disabled";
1214 mipi_dsi: mipi@21e0000 {
1215 reg = <0x021e0000 0x4000>;
1216 status = "disabled";
1219 #address-cells = <1>;
1225 mipi_mux_0: endpoint {
1226 remote-endpoint = <&ipu1_di0_mipi>;
1233 mipi_mux_1: endpoint {
1234 remote-endpoint = <&ipu1_di1_mipi>;
1241 compatible = "fsl,imx6q-vdoa";
1242 reg = <0x021e4000 0x4000>;
1243 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&clks IMX6QDL_CLK_VDOA>;
1247 uart2: serial@21e8000 {
1248 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1249 reg = <0x021e8000 0x4000>;
1250 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1252 <&clks IMX6QDL_CLK_UART_SERIAL>;
1253 clock-names = "ipg", "per";
1254 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1255 dma-names = "rx", "tx";
1256 status = "disabled";
1259 uart3: serial@21ec000 {
1260 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1261 reg = <0x021ec000 0x4000>;
1262 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1263 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1264 <&clks IMX6QDL_CLK_UART_SERIAL>;
1265 clock-names = "ipg", "per";
1266 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1267 dma-names = "rx", "tx";
1268 status = "disabled";
1271 uart4: serial@21f0000 {
1272 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1273 reg = <0x021f0000 0x4000>;
1274 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1275 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1276 <&clks IMX6QDL_CLK_UART_SERIAL>;
1277 clock-names = "ipg", "per";
1278 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1279 dma-names = "rx", "tx";
1280 status = "disabled";
1283 uart5: serial@21f4000 {
1284 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1285 reg = <0x021f4000 0x4000>;
1286 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1287 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1288 <&clks IMX6QDL_CLK_UART_SERIAL>;
1289 clock-names = "ipg", "per";
1290 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1291 dma-names = "rx", "tx";
1292 status = "disabled";
1297 #address-cells = <1>;
1299 compatible = "fsl,imx6q-ipu";
1300 reg = <0x02400000 0x400000>;
1301 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1302 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1303 clocks = <&clks IMX6QDL_CLK_IPU1>,
1304 <&clks IMX6QDL_CLK_IPU1_DI0>,
1305 <&clks IMX6QDL_CLK_IPU1_DI1>;
1306 clock-names = "bus", "di0", "di1";
1312 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1313 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1322 #address-cells = <1>;
1326 ipu1_di0_disp0: endpoint@0 {
1330 ipu1_di0_hdmi: endpoint@1 {
1332 remote-endpoint = <&hdmi_mux_0>;
1335 ipu1_di0_mipi: endpoint@2 {
1337 remote-endpoint = <&mipi_mux_0>;
1340 ipu1_di0_lvds0: endpoint@3 {
1342 remote-endpoint = <&lvds0_mux_0>;
1345 ipu1_di0_lvds1: endpoint@4 {
1347 remote-endpoint = <&lvds1_mux_0>;
1352 #address-cells = <1>;
1356 ipu1_di1_disp1: endpoint@0 {
1360 ipu1_di1_hdmi: endpoint@1 {
1362 remote-endpoint = <&hdmi_mux_1>;
1365 ipu1_di1_mipi: endpoint@2 {
1367 remote-endpoint = <&mipi_mux_1>;
1370 ipu1_di1_lvds0: endpoint@3 {
1372 remote-endpoint = <&lvds0_mux_1>;
1375 ipu1_di1_lvds1: endpoint@4 {
1377 remote-endpoint = <&lvds1_mux_1>;