1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright 2011 Freescale Semiconductor, Inc.
4 // Copyright 2011 Linaro Ltd.
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 * The decompressor and also some bootloaders rely on a
15 * pre-existing /chosen node to be available to insert the
16 * command line and merge other ATAGS info.
54 compatible = "fsl,imx-ckil", "fixed-clock";
56 clock-frequency = <32768>;
60 compatible = "fsl,imx-ckih1", "fixed-clock";
62 clock-frequency = <0>;
66 compatible = "fsl,imx-osc", "fixed-clock";
68 clock-frequency = <24000000>;
75 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
88 lvds0_mux_0: endpoint {
89 remote-endpoint = <&ipu1_di0_lvds0>;
96 lvds0_mux_1: endpoint {
97 remote-endpoint = <&ipu1_di1_lvds0>;
103 #address-cells = <1>;
111 lvds1_mux_0: endpoint {
112 remote-endpoint = <&ipu1_di0_lvds1>;
119 lvds1_mux_1: endpoint {
120 remote-endpoint = <&ipu1_di1_lvds1>;
127 compatible = "arm,cortex-a9-pmu";
128 interrupt-parent = <&gpc>;
129 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
132 usbphynop1: usbphynop1 {
133 compatible = "usb-nop-xceiv";
137 usbphynop2: usbphynop2 {
138 compatible = "usb-nop-xceiv";
143 #address-cells = <1>;
145 compatible = "simple-bus";
146 interrupt-parent = <&gpc>;
149 dma_apbh: dma-apbh@110000 {
150 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
151 reg = <0x00110000 0x2000>;
152 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
153 <0 13 IRQ_TYPE_LEVEL_HIGH>,
154 <0 13 IRQ_TYPE_LEVEL_HIGH>,
155 <0 13 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
159 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
162 gpmi: nand-controller@112000 {
163 compatible = "fsl,imx6q-gpmi-nand";
164 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
165 reg-names = "gpmi-nand", "bch";
166 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-names = "bch";
168 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
169 <&clks IMX6QDL_CLK_GPMI_APB>,
170 <&clks IMX6QDL_CLK_GPMI_BCH>,
171 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
172 <&clks IMX6QDL_CLK_PER1_BCH>;
173 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
174 "gpmi_bch_apb", "per1_bch";
175 dmas = <&dma_apbh 0>;
181 #address-cells = <1>;
183 reg = <0x00120000 0x9000>;
184 interrupts = <0 115 0x04>;
186 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
187 <&clks IMX6QDL_CLK_HDMI_ISFR>;
188 clock-names = "iahb", "isfr";
194 hdmi_mux_0: endpoint {
195 remote-endpoint = <&ipu1_di0_hdmi>;
202 hdmi_mux_1: endpoint {
203 remote-endpoint = <&ipu1_di1_hdmi>;
209 compatible = "vivante,gc";
210 reg = <0x00130000 0x4000>;
211 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
213 <&clks IMX6QDL_CLK_GPU3D_CORE>,
214 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
215 clock-names = "bus", "core", "shader";
216 power-domains = <&pd_pu>;
217 #cooling-cells = <2>;
221 compatible = "vivante,gc";
222 reg = <0x00134000 0x4000>;
223 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
225 <&clks IMX6QDL_CLK_GPU2D_CORE>;
226 clock-names = "bus", "core";
227 power-domains = <&pd_pu>;
228 #cooling-cells = <2>;
232 compatible = "arm,cortex-a9-twd-timer";
233 reg = <0x00a00600 0x20>;
234 interrupts = <1 13 0xf01>;
235 interrupt-parent = <&intc>;
236 clocks = <&clks IMX6QDL_CLK_TWD>;
239 intc: interrupt-controller@a01000 {
240 compatible = "arm,cortex-a9-gic";
241 #interrupt-cells = <3>;
242 interrupt-controller;
243 reg = <0x00a01000 0x1000>,
245 interrupt-parent = <&intc>;
248 L2: cache-controller@a02000 {
249 compatible = "arm,pl310-cache";
250 reg = <0x00a02000 0x1000>;
251 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
254 arm,tag-latency = <4 2 3>;
255 arm,data-latency = <4 2 3>;
260 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
261 reg = <0x01ffc000 0x04000>,
262 <0x01f00000 0x80000>;
263 reg-names = "dbi", "config";
264 #address-cells = <3>;
267 bus-range = <0x00 0xff>;
268 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
269 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
272 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "msi";
274 #interrupt-cells = <1>;
275 interrupt-map-mask = <0 0 0 0x7>;
276 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
277 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
278 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
279 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
281 <&clks IMX6QDL_CLK_LVDS1_GATE>,
282 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
283 clock-names = "pcie", "pcie_bus", "pcie_phy";
287 bus@2000000 { /* AIPS1 */
288 compatible = "fsl,aips-bus", "simple-bus";
289 #address-cells = <1>;
291 reg = <0x02000000 0x100000>;
295 compatible = "fsl,spba-bus", "simple-bus";
296 #address-cells = <1>;
298 reg = <0x02000000 0x40000>;
301 spdif: spdif@2004000 {
302 compatible = "fsl,imx35-spdif";
303 reg = <0x02004000 0x4000>;
304 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
305 dmas = <&sdma 14 18 0>,
307 dma-names = "rx", "tx";
308 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
309 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
310 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
311 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
312 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
313 clock-names = "core", "rxtx0",
321 ecspi1: spi@2008000 {
322 #address-cells = <1>;
324 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
325 reg = <0x02008000 0x4000>;
326 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
328 <&clks IMX6QDL_CLK_ECSPI1>;
329 clock-names = "ipg", "per";
330 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
331 dma-names = "rx", "tx";
335 ecspi2: spi@200c000 {
336 #address-cells = <1>;
338 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
339 reg = <0x0200c000 0x4000>;
340 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
342 <&clks IMX6QDL_CLK_ECSPI2>;
343 clock-names = "ipg", "per";
344 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
345 dma-names = "rx", "tx";
349 ecspi3: spi@2010000 {
350 #address-cells = <1>;
352 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
353 reg = <0x02010000 0x4000>;
354 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
356 <&clks IMX6QDL_CLK_ECSPI3>;
357 clock-names = "ipg", "per";
358 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
359 dma-names = "rx", "tx";
363 ecspi4: spi@2014000 {
364 #address-cells = <1>;
366 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
367 reg = <0x02014000 0x4000>;
368 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
370 <&clks IMX6QDL_CLK_ECSPI4>;
371 clock-names = "ipg", "per";
372 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
373 dma-names = "rx", "tx";
377 uart1: serial@2020000 {
378 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
379 reg = <0x02020000 0x4000>;
380 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
382 <&clks IMX6QDL_CLK_UART_SERIAL>;
383 clock-names = "ipg", "per";
384 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
385 dma-names = "rx", "tx";
390 #sound-dai-cells = <0>;
391 compatible = "fsl,imx35-esai";
392 reg = <0x02024000 0x4000>;
393 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
395 <&clks IMX6QDL_CLK_ESAI_MEM>,
396 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
397 <&clks IMX6QDL_CLK_ESAI_IPG>,
398 <&clks IMX6QDL_CLK_SPBA>;
399 clock-names = "core", "mem", "extal", "fsys", "spba";
400 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
401 dma-names = "rx", "tx";
406 #sound-dai-cells = <0>;
407 compatible = "fsl,imx6q-ssi",
409 reg = <0x02028000 0x4000>;
410 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
412 <&clks IMX6QDL_CLK_SSI1>;
413 clock-names = "ipg", "baud";
414 dmas = <&sdma 37 1 0>,
416 dma-names = "rx", "tx";
417 fsl,fifo-depth = <15>;
422 #sound-dai-cells = <0>;
423 compatible = "fsl,imx6q-ssi",
425 reg = <0x0202c000 0x4000>;
426 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
428 <&clks IMX6QDL_CLK_SSI2>;
429 clock-names = "ipg", "baud";
430 dmas = <&sdma 41 1 0>,
432 dma-names = "rx", "tx";
433 fsl,fifo-depth = <15>;
438 #sound-dai-cells = <0>;
439 compatible = "fsl,imx6q-ssi",
441 reg = <0x02030000 0x4000>;
442 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
444 <&clks IMX6QDL_CLK_SSI3>;
445 clock-names = "ipg", "baud";
446 dmas = <&sdma 45 1 0>,
448 dma-names = "rx", "tx";
449 fsl,fifo-depth = <15>;
454 compatible = "fsl,imx53-asrc";
455 reg = <0x02034000 0x4000>;
456 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
458 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
459 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
460 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
461 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
462 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
463 <&clks IMX6QDL_CLK_SPBA>;
464 clock-names = "mem", "ipg", "asrck_0",
465 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
466 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
467 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
468 "asrck_d", "asrck_e", "asrck_f", "spba";
469 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
470 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
471 dma-names = "rxa", "rxb", "rxc",
473 fsl,asrc-rate = <48000>;
474 fsl,asrc-width = <16>;
479 reg = <0x0203c000 0x4000>;
484 compatible = "cnm,coda960";
485 reg = <0x02040000 0x3c000>;
486 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
487 <0 3 IRQ_TYPE_LEVEL_HIGH>;
488 interrupt-names = "bit", "jpeg";
489 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
490 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
491 clock-names = "per", "ahb";
492 power-domains = <&pd_pu>;
497 aipstz@207c000 { /* AIPSTZ1 */
498 reg = <0x0207c000 0x4000>;
503 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
504 reg = <0x02080000 0x4000>;
505 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6QDL_CLK_IPG>,
507 <&clks IMX6QDL_CLK_PWM1>;
508 clock-names = "ipg", "per";
514 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
515 reg = <0x02084000 0x4000>;
516 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clks IMX6QDL_CLK_IPG>,
518 <&clks IMX6QDL_CLK_PWM2>;
519 clock-names = "ipg", "per";
525 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
526 reg = <0x02088000 0x4000>;
527 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&clks IMX6QDL_CLK_IPG>,
529 <&clks IMX6QDL_CLK_PWM3>;
530 clock-names = "ipg", "per";
536 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
537 reg = <0x0208c000 0x4000>;
538 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&clks IMX6QDL_CLK_IPG>,
540 <&clks IMX6QDL_CLK_PWM4>;
541 clock-names = "ipg", "per";
545 can1: flexcan@2090000 {
546 compatible = "fsl,imx6q-flexcan";
547 reg = <0x02090000 0x4000>;
548 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
550 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
551 clock-names = "ipg", "per";
552 fsl,stop-mode = <&gpr 0x34 28 0x10 17>;
556 can2: flexcan@2094000 {
557 compatible = "fsl,imx6q-flexcan";
558 reg = <0x02094000 0x4000>;
559 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
561 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
562 clock-names = "ipg", "per";
563 fsl,stop-mode = <&gpr 0x34 29 0x10 18>;
568 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
569 reg = <0x02098000 0x4000>;
570 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
572 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
573 <&clks IMX6QDL_CLK_GPT_3M>;
574 clock-names = "ipg", "per", "osc_per";
577 gpio1: gpio@209c000 {
578 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
579 reg = <0x0209c000 0x4000>;
580 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
581 <0 67 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
588 gpio2: gpio@20a0000 {
589 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
590 reg = <0x020a0000 0x4000>;
591 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
592 <0 69 IRQ_TYPE_LEVEL_HIGH>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
599 gpio3: gpio@20a4000 {
600 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
601 reg = <0x020a4000 0x4000>;
602 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
603 <0 71 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
610 gpio4: gpio@20a8000 {
611 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
612 reg = <0x020a8000 0x4000>;
613 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
614 <0 73 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
621 gpio5: gpio@20ac000 {
622 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
623 reg = <0x020ac000 0x4000>;
624 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
625 <0 75 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-controller;
629 #interrupt-cells = <2>;
632 gpio6: gpio@20b0000 {
633 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
634 reg = <0x020b0000 0x4000>;
635 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
636 <0 77 IRQ_TYPE_LEVEL_HIGH>;
639 interrupt-controller;
640 #interrupt-cells = <2>;
643 gpio7: gpio@20b4000 {
644 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
645 reg = <0x020b4000 0x4000>;
646 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
647 <0 79 IRQ_TYPE_LEVEL_HIGH>;
650 interrupt-controller;
651 #interrupt-cells = <2>;
654 kpp: keypad@20b8000 {
655 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
656 reg = <0x020b8000 0x4000>;
657 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&clks IMX6QDL_CLK_IPG>;
662 wdog1: watchdog@20bc000 {
663 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
664 reg = <0x020bc000 0x4000>;
665 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clks IMX6QDL_CLK_IPG>;
669 wdog2: watchdog@20c0000 {
670 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
671 reg = <0x020c0000 0x4000>;
672 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clks IMX6QDL_CLK_IPG>;
677 clks: clock-controller@20c4000 {
678 compatible = "fsl,imx6q-ccm";
679 reg = <0x020c4000 0x4000>;
680 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
681 <0 88 IRQ_TYPE_LEVEL_HIGH>;
685 anatop: anatop@20c8000 {
686 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
687 reg = <0x020c8000 0x1000>;
688 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
689 <0 54 IRQ_TYPE_LEVEL_HIGH>,
690 <0 127 IRQ_TYPE_LEVEL_HIGH>;
692 reg_vdd1p1: regulator-1p1 {
693 compatible = "fsl,anatop-regulator";
694 regulator-name = "vdd1p1";
695 regulator-min-microvolt = <1000000>;
696 regulator-max-microvolt = <1200000>;
698 anatop-reg-offset = <0x110>;
699 anatop-vol-bit-shift = <8>;
700 anatop-vol-bit-width = <5>;
701 anatop-min-bit-val = <4>;
702 anatop-min-voltage = <800000>;
703 anatop-max-voltage = <1375000>;
704 anatop-enable-bit = <0>;
707 reg_vdd3p0: regulator-3p0 {
708 compatible = "fsl,anatop-regulator";
709 regulator-name = "vdd3p0";
710 regulator-min-microvolt = <2800000>;
711 regulator-max-microvolt = <3150000>;
713 anatop-reg-offset = <0x120>;
714 anatop-vol-bit-shift = <8>;
715 anatop-vol-bit-width = <5>;
716 anatop-min-bit-val = <0>;
717 anatop-min-voltage = <2625000>;
718 anatop-max-voltage = <3400000>;
719 anatop-enable-bit = <0>;
722 reg_vdd2p5: regulator-2p5 {
723 compatible = "fsl,anatop-regulator";
724 regulator-name = "vdd2p5";
725 regulator-min-microvolt = <2250000>;
726 regulator-max-microvolt = <2750000>;
728 anatop-reg-offset = <0x130>;
729 anatop-vol-bit-shift = <8>;
730 anatop-vol-bit-width = <5>;
731 anatop-min-bit-val = <0>;
732 anatop-min-voltage = <2100000>;
733 anatop-max-voltage = <2875000>;
734 anatop-enable-bit = <0>;
737 reg_arm: regulator-vddcore {
738 compatible = "fsl,anatop-regulator";
739 regulator-name = "vddarm";
740 regulator-min-microvolt = <725000>;
741 regulator-max-microvolt = <1450000>;
743 anatop-reg-offset = <0x140>;
744 anatop-vol-bit-shift = <0>;
745 anatop-vol-bit-width = <5>;
746 anatop-delay-reg-offset = <0x170>;
747 anatop-delay-bit-shift = <24>;
748 anatop-delay-bit-width = <2>;
749 anatop-min-bit-val = <1>;
750 anatop-min-voltage = <725000>;
751 anatop-max-voltage = <1450000>;
754 reg_pu: regulator-vddpu {
755 compatible = "fsl,anatop-regulator";
756 regulator-name = "vddpu";
757 regulator-min-microvolt = <725000>;
758 regulator-max-microvolt = <1450000>;
759 regulator-enable-ramp-delay = <150>;
760 anatop-reg-offset = <0x140>;
761 anatop-vol-bit-shift = <9>;
762 anatop-vol-bit-width = <5>;
763 anatop-delay-reg-offset = <0x170>;
764 anatop-delay-bit-shift = <26>;
765 anatop-delay-bit-width = <2>;
766 anatop-min-bit-val = <1>;
767 anatop-min-voltage = <725000>;
768 anatop-max-voltage = <1450000>;
771 reg_soc: regulator-vddsoc {
772 compatible = "fsl,anatop-regulator";
773 regulator-name = "vddsoc";
774 regulator-min-microvolt = <725000>;
775 regulator-max-microvolt = <1450000>;
777 anatop-reg-offset = <0x140>;
778 anatop-vol-bit-shift = <18>;
779 anatop-vol-bit-width = <5>;
780 anatop-delay-reg-offset = <0x170>;
781 anatop-delay-bit-shift = <28>;
782 anatop-delay-bit-width = <2>;
783 anatop-min-bit-val = <1>;
784 anatop-min-voltage = <725000>;
785 anatop-max-voltage = <1450000>;
789 compatible = "fsl,imx6q-tempmon";
790 interrupt-parent = <&gpc>;
791 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
792 fsl,tempmon = <&anatop>;
793 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
794 nvmem-cell-names = "calib", "temp_grade";
795 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
796 #thermal-sensor-cells = <0>;
800 usbphy1: usbphy@20c9000 {
801 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
802 reg = <0x020c9000 0x1000>;
803 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
804 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
805 fsl,anatop = <&anatop>;
808 usbphy2: usbphy@20ca000 {
809 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
810 reg = <0x020ca000 0x1000>;
811 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
813 fsl,anatop = <&anatop>;
817 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
818 reg = <0x020cc000 0x4000>;
820 snvs_rtc: snvs-rtc-lp {
821 compatible = "fsl,sec-v4.0-mon-rtc-lp";
824 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
825 <0 20 IRQ_TYPE_LEVEL_HIGH>;
828 snvs_poweroff: snvs-poweroff {
829 compatible = "syscon-poweroff";
837 snvs_pwrkey: snvs-powerkey {
838 compatible = "fsl,sec-v4.0-pwrkey";
840 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
841 linux,keycode = <KEY_POWER>;
846 snvs_lpgpr: snvs-lpgpr {
847 compatible = "fsl,imx6q-snvs-lpgpr";
851 epit1: epit@20d0000 { /* EPIT1 */
852 reg = <0x020d0000 0x4000>;
853 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
856 epit2: epit@20d4000 { /* EPIT2 */
857 reg = <0x020d4000 0x4000>;
858 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
861 src: reset-controller@20d8000 {
862 compatible = "fsl,imx6q-src", "fsl,imx51-src";
863 reg = <0x020d8000 0x4000>;
864 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
865 <0 96 IRQ_TYPE_LEVEL_HIGH>;
870 compatible = "fsl,imx6q-gpc";
871 reg = <0x020dc000 0x4000>;
872 interrupt-controller;
873 #interrupt-cells = <3>;
874 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
875 interrupt-parent = <&intc>;
876 clocks = <&clks IMX6QDL_CLK_IPG>;
880 #address-cells = <1>;
885 #power-domain-cells = <0>;
887 pd_pu: power-domain@1 {
889 #power-domain-cells = <0>;
890 power-supply = <®_pu>;
891 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
892 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
893 <&clks IMX6QDL_CLK_GPU2D_CORE>,
894 <&clks IMX6QDL_CLK_GPU2D_AXI>,
895 <&clks IMX6QDL_CLK_OPENVG_AXI>,
896 <&clks IMX6QDL_CLK_VPU_AXI>;
901 gpr: iomuxc-gpr@20e0000 {
902 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
903 reg = <0x20e0000 0x38>;
905 mux: mux-controller {
906 compatible = "mmio-mux";
907 #mux-control-cells = <1>;
911 iomuxc: pinctrl@20e0000 {
912 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
913 reg = <0x20e0000 0x4000>;
916 dcic1: dcic@20e4000 {
917 reg = <0x020e4000 0x4000>;
918 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
921 dcic2: dcic@20e8000 {
922 reg = <0x020e8000 0x4000>;
923 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
927 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
928 reg = <0x020ec000 0x4000>;
929 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&clks IMX6QDL_CLK_IPG>,
931 <&clks IMX6QDL_CLK_SDMA>;
932 clock-names = "ipg", "ahb";
934 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
938 bus@2100000 { /* AIPS2 */
939 compatible = "fsl,aips-bus", "simple-bus";
940 #address-cells = <1>;
942 reg = <0x02100000 0x100000>;
945 crypto: crypto@2100000 {
946 compatible = "fsl,sec-v4.0";
947 #address-cells = <1>;
949 reg = <0x2100000 0x10000>;
950 ranges = <0 0x2100000 0x10000>;
951 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
952 <&clks IMX6QDL_CLK_CAAM_ACLK>,
953 <&clks IMX6QDL_CLK_CAAM_IPG>,
954 <&clks IMX6QDL_CLK_EIM_SLOW>;
955 clock-names = "mem", "aclk", "ipg", "emi_slow";
958 compatible = "fsl,sec-v4.0-job-ring";
959 reg = <0x1000 0x1000>;
960 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
964 compatible = "fsl,sec-v4.0-job-ring";
965 reg = <0x2000 0x1000>;
966 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
970 aipstz@217c000 { /* AIPSTZ2 */
971 reg = <0x0217c000 0x4000>;
974 usbotg: usb@2184000 {
975 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
976 reg = <0x02184000 0x200>;
977 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clks IMX6QDL_CLK_USBOH3>;
979 fsl,usbphy = <&usbphy1>;
980 fsl,usbmisc = <&usbmisc 0>;
981 ahb-burst-config = <0x0>;
982 tx-burst-size-dword = <0x10>;
983 rx-burst-size-dword = <0x10>;
988 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
989 reg = <0x02184200 0x200>;
990 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&clks IMX6QDL_CLK_USBOH3>;
992 fsl,usbphy = <&usbphy2>;
993 fsl,usbmisc = <&usbmisc 1>;
995 ahb-burst-config = <0x0>;
996 tx-burst-size-dword = <0x10>;
997 rx-burst-size-dword = <0x10>;
1001 usbh2: usb@2184400 {
1002 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1003 reg = <0x02184400 0x200>;
1004 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1006 fsl,usbphy = <&usbphynop1>;
1008 fsl,usbmisc = <&usbmisc 2>;
1010 ahb-burst-config = <0x0>;
1011 tx-burst-size-dword = <0x10>;
1012 rx-burst-size-dword = <0x10>;
1013 status = "disabled";
1016 usbh3: usb@2184600 {
1017 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1018 reg = <0x02184600 0x200>;
1019 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1021 fsl,usbphy = <&usbphynop2>;
1023 fsl,usbmisc = <&usbmisc 3>;
1025 ahb-burst-config = <0x0>;
1026 tx-burst-size-dword = <0x10>;
1027 rx-burst-size-dword = <0x10>;
1028 status = "disabled";
1031 usbmisc: usbmisc@2184800 {
1033 compatible = "fsl,imx6q-usbmisc";
1034 reg = <0x02184800 0x200>;
1035 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1038 fec: ethernet@2188000 {
1039 compatible = "fsl,imx6q-fec";
1040 reg = <0x02188000 0x4000>;
1041 interrupt-names = "int0", "pps";
1042 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1043 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&clks IMX6QDL_CLK_ENET>,
1045 <&clks IMX6QDL_CLK_ENET>,
1046 <&clks IMX6QDL_CLK_ENET_REF>,
1047 <&clks IMX6QDL_CLK_ENET_REF>;
1048 clock-names = "ipg", "ahb", "ptp", "enet_out";
1049 fsl,stop-mode = <&gpr 0x34 27>;
1050 status = "disabled";
1054 reg = <0x0218c000 0x4000>;
1055 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1056 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1057 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1060 usdhc1: mmc@2190000 {
1061 compatible = "fsl,imx6q-usdhc";
1062 reg = <0x02190000 0x4000>;
1063 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1065 <&clks IMX6QDL_CLK_USDHC1>,
1066 <&clks IMX6QDL_CLK_USDHC1>;
1067 clock-names = "ipg", "ahb", "per";
1069 status = "disabled";
1072 usdhc2: mmc@2194000 {
1073 compatible = "fsl,imx6q-usdhc";
1074 reg = <0x02194000 0x4000>;
1075 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1077 <&clks IMX6QDL_CLK_USDHC2>,
1078 <&clks IMX6QDL_CLK_USDHC2>;
1079 clock-names = "ipg", "ahb", "per";
1081 status = "disabled";
1084 usdhc3: mmc@2198000 {
1085 compatible = "fsl,imx6q-usdhc";
1086 reg = <0x02198000 0x4000>;
1087 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1089 <&clks IMX6QDL_CLK_USDHC3>,
1090 <&clks IMX6QDL_CLK_USDHC3>;
1091 clock-names = "ipg", "ahb", "per";
1093 status = "disabled";
1096 usdhc4: mmc@219c000 {
1097 compatible = "fsl,imx6q-usdhc";
1098 reg = <0x0219c000 0x4000>;
1099 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1101 <&clks IMX6QDL_CLK_USDHC4>,
1102 <&clks IMX6QDL_CLK_USDHC4>;
1103 clock-names = "ipg", "ahb", "per";
1105 status = "disabled";
1109 #address-cells = <1>;
1111 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1112 reg = <0x021a0000 0x4000>;
1113 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&clks IMX6QDL_CLK_I2C1>;
1115 status = "disabled";
1119 #address-cells = <1>;
1121 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1122 reg = <0x021a4000 0x4000>;
1123 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&clks IMX6QDL_CLK_I2C2>;
1125 status = "disabled";
1129 #address-cells = <1>;
1131 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1132 reg = <0x021a8000 0x4000>;
1133 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&clks IMX6QDL_CLK_I2C3>;
1135 status = "disabled";
1139 reg = <0x021ac000 0x4000>;
1142 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1143 compatible = "fsl,imx6q-mmdc";
1144 reg = <0x021b0000 0x4000>;
1145 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
1148 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1149 compatible = "fsl,imx6q-mmdc";
1150 reg = <0x021b4000 0x4000>;
1151 status = "disabled";
1154 weim: weim@21b8000 {
1155 #address-cells = <2>;
1157 compatible = "fsl,imx6q-weim";
1158 reg = <0x021b8000 0x4000>;
1159 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1161 fsl,weim-cs-gpr = <&gpr>;
1162 status = "disabled";
1165 ocotp: efuse@21bc000 {
1166 compatible = "fsl,imx6q-ocotp", "syscon";
1167 reg = <0x021bc000 0x4000>;
1168 clocks = <&clks IMX6QDL_CLK_IIM>;
1169 #address-cells = <1>;
1172 cpu_speed_grade: speed-grade@10 {
1176 tempmon_calib: calib@38 {
1180 tempmon_temp_grade: temp-grade@20 {
1185 tzasc@21d0000 { /* TZASC1 */
1186 reg = <0x021d0000 0x4000>;
1187 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1190 tzasc@21d4000 { /* TZASC2 */
1191 reg = <0x021d4000 0x4000>;
1192 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1195 audmux: audmux@21d8000 {
1196 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1197 reg = <0x021d8000 0x4000>;
1198 status = "disabled";
1201 mipi_csi: mipi@21dc000 {
1202 compatible = "fsl,imx6-mipi-csi2";
1203 reg = <0x021dc000 0x4000>;
1204 #address-cells = <1>;
1206 interrupts = <0 100 0x04>, <0 101 0x04>;
1207 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1208 <&clks IMX6QDL_CLK_VIDEO_27M>,
1209 <&clks IMX6QDL_CLK_EIM_PODF>;
1210 clock-names = "dphy", "ref", "pix";
1211 status = "disabled";
1214 mipi_dsi: mipi@21e0000 {
1215 reg = <0x021e0000 0x4000>;
1216 status = "disabled";
1219 #address-cells = <1>;
1225 mipi_mux_0: endpoint {
1226 remote-endpoint = <&ipu1_di0_mipi>;
1233 mipi_mux_1: endpoint {
1234 remote-endpoint = <&ipu1_di1_mipi>;
1241 compatible = "fsl,imx6q-vdoa";
1242 reg = <0x021e4000 0x4000>;
1243 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&clks IMX6QDL_CLK_VDOA>;
1247 uart2: serial@21e8000 {
1248 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1249 reg = <0x021e8000 0x4000>;
1250 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1252 <&clks IMX6QDL_CLK_UART_SERIAL>;
1253 clock-names = "ipg", "per";
1254 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1255 dma-names = "rx", "tx";
1256 status = "disabled";
1259 uart3: serial@21ec000 {
1260 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1261 reg = <0x021ec000 0x4000>;
1262 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1263 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1264 <&clks IMX6QDL_CLK_UART_SERIAL>;
1265 clock-names = "ipg", "per";
1266 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1267 dma-names = "rx", "tx";
1268 status = "disabled";
1271 uart4: serial@21f0000 {
1272 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1273 reg = <0x021f0000 0x4000>;
1274 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1275 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1276 <&clks IMX6QDL_CLK_UART_SERIAL>;
1277 clock-names = "ipg", "per";
1278 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1279 dma-names = "rx", "tx";
1280 status = "disabled";
1283 uart5: serial@21f4000 {
1284 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1285 reg = <0x021f4000 0x4000>;
1286 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1287 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1288 <&clks IMX6QDL_CLK_UART_SERIAL>;
1289 clock-names = "ipg", "per";
1290 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1291 dma-names = "rx", "tx";
1292 status = "disabled";
1297 #address-cells = <1>;
1299 compatible = "fsl,imx6q-ipu";
1300 reg = <0x02400000 0x400000>;
1301 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1302 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1303 clocks = <&clks IMX6QDL_CLK_IPU1>,
1304 <&clks IMX6QDL_CLK_IPU1_DI0>,
1305 <&clks IMX6QDL_CLK_IPU1_DI1>;
1306 clock-names = "bus", "di0", "di1";
1312 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1313 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1322 #address-cells = <1>;
1326 ipu1_di0_disp0: endpoint@0 {
1330 ipu1_di0_hdmi: endpoint@1 {
1332 remote-endpoint = <&hdmi_mux_0>;
1335 ipu1_di0_mipi: endpoint@2 {
1337 remote-endpoint = <&mipi_mux_0>;
1340 ipu1_di0_lvds0: endpoint@3 {
1342 remote-endpoint = <&lvds0_mux_0>;
1345 ipu1_di0_lvds1: endpoint@4 {
1347 remote-endpoint = <&lvds1_mux_0>;
1352 #address-cells = <1>;
1356 ipu1_di1_disp1: endpoint@0 {
1360 ipu1_di1_hdmi: endpoint@1 {
1362 remote-endpoint = <&hdmi_mux_1>;
1365 ipu1_di1_mipi: endpoint@2 {
1367 remote-endpoint = <&mipi_mux_1>;
1370 ipu1_di1_lvds0: endpoint@3 {
1372 remote-endpoint = <&lvds0_mux_1>;
1375 ipu1_di1_lvds1: endpoint@4 {
1377 remote-endpoint = <&lvds1_mux_1>;