1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Copyright (C) 2020 Pengutronix, Ulrich Oelmann <kernel@pengutronix.de>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
25 compatible = "iio-hwmon";
26 io-channels = <&adc 0>, /* 24V */
27 <&adc 1>; /* temperature */
31 compatible = "gpio-leds";
35 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
36 function = LED_FUNCTION_STATUS;
38 linux,default-trigger = "heartbeat";
43 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
44 default-state = "off";
49 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
55 compatible = "microchip,mdio-smi0";
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_mdio>;
60 gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>,
61 <&gpio1 22 GPIO_ACTIVE_HIGH>;
64 compatible = "microchip,ksz8873";
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_switch>;
67 interrupt-parent = <&gpio3>;
68 interrupt = <30 IRQ_TYPE_LEVEL_HIGH>;
69 reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
78 phy-mode = "internal";
84 phy-mode = "internal";
104 clk50m_phy: phy-clock {
105 compatible = "fixed-clock";
107 clock-frequency = <50000000>;
110 reg_3v3: regulator-3v3 {
111 compatible = "regulator-fixed";
112 vin-supply = <®_5v0>;
113 regulator-name = "3v3";
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
118 reg_5v0: regulator-5v0 {
119 compatible = "regulator-fixed";
120 regulator-name = "5v0";
121 regulator-min-microvolt = <5000000>;
122 regulator-max-microvolt = <5000000>;
125 reg_24v0: regulator-24v0 {
126 compatible = "regulator-fixed";
127 regulator-name = "24v0";
128 regulator-min-microvolt = <24000000>;
129 regulator-max-microvolt = <24000000>;
132 reg_can1_stby: regulator-can1-stby {
133 compatible = "regulator-fixed";
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_can1_stby>;
136 regulator-name = "can1-3v3";
137 regulator-min-microvolt = <3300000>;
138 regulator-max-microvolt = <3300000>;
139 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
142 reg_can2_stby: regulator-can2-stby {
143 compatible = "regulator-fixed";
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_can2_stby>;
146 regulator-name = "can2-3v3";
147 regulator-min-microvolt = <3300000>;
148 regulator-max-microvolt = <3300000>;
149 gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
152 reg_vcc_mmc: regulator-vcc-mmc {
153 compatible = "regulator-fixed";
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_vcc_mmc>;
156 vin-supply = <®_3v3>;
157 regulator-name = "mmc_vcc_supply";
158 regulator-min-microvolt = <3300000>;
159 regulator-max-microvolt = <3300000>;
162 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
164 startup-delay-us = <100>;
167 reg_vcc_mmc_io: regulator-vcc-mmc-io {
168 compatible = "regulator-gpio";
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_vcc_mmc_io>;
171 vin-supply = <®_5v0>;
172 regulator-name = "mmc_io_supply";
173 regulator-type = "voltage";
174 regulator-min-microvolt = <1800000>;
175 regulator-max-microvolt = <3300000>;
176 gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
178 states = <1800000 0x1>, <3300000 0x0>;
179 startup-delay-us = <100>;
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_can1>;
186 xceiver-supply = <®_can1_stby>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_can2>;
193 xceiver-supply = <®_can2_stby>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&pinctrl_ecspi1>;
200 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
204 compatible = "jedec,spi-nor";
205 spi-max-frequency = <54000000>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_ecspi2>;
213 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
217 compatible = "microchip,mcp3002";
219 vref-supply = <®_3v3>;
220 spi-max-frequency = <1000000>;
221 #io-channel-cells = <1>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_enet>;
228 clocks = <&clks IMX6QDL_CLK_ENET>,
229 <&clks IMX6QDL_CLK_ENET>,
231 clock-names = "ipg", "ahb", "ptp";
233 phy-supply = <®_3v3>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_gpmi_nand>;
246 #address-cells = <1>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_i2c3>;
254 clock-frequency = <400000>;
258 compatible = "nxp,pcf85063";
260 quartz-load-femtofarads = <12500>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_pwm2>;
272 /* used for LCD contrast control */
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_pwm3>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_uart2>;
285 vbus-supply = <®_5v0>;
286 disable-over-current;
301 vbus-supply = <®_5v0>;
302 disable-over-current;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_usdhc3>;
309 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
310 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
314 max-frequency = <50000000>;
321 vmmc-supply = <®_vcc_mmc>;
322 vqmmc-supply = <®_vcc_mmc_io>;
327 pinctrl_can1: can1grp {
329 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x3008
330 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b000
334 pinctrl_can1_stby: can1stbygrp {
336 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x13008
340 pinctrl_can2: can2grp {
342 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008
343 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000
347 pinctrl_can2_stby: can2stbygrp {
349 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x13008
353 pinctrl_ecspi1: ecspi1grp {
355 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
356 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb1
357 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb1
358 /* *no* external pull up */
359 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x58
363 pinctrl_ecspi2: ecspi2grp {
365 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
366 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0xb1
367 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0xb1
368 /* external pull up */
369 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x58
373 pinctrl_enet: enetgrp {
376 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x100f5
377 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x100f5
378 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x100c0
379 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x100c0
380 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x100f5
381 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x100f5
382 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0
383 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x58
384 /* GPIO for "link active" */
385 MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x3038
389 pinctrl_gpmi_nand: gpminandgrp {
391 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
392 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
393 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
394 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
395 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
396 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
397 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
398 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
399 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
400 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
401 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
402 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
403 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
404 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
405 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
409 pinctrl_i2c3: i2c3grp {
411 /* external 10 k pull up */
412 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x40010878
413 /* external 10 k pull up */
414 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x40010878
418 pinctrl_mdio: mdiogrp {
420 MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x100b1
421 MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0xb1
425 pinctrl_pwm2: pwm2grp {
427 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x58
431 pinctrl_pwm3: pwm3grp {
433 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x58
437 pinctrl_switch: switchgrp {
439 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0xb0
443 pinctrl_uart2: uart2grp {
445 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
446 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
450 pinctrl_usdhc3: usdhc3grp {
452 /* SoC internal pull up required */
453 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
454 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
455 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
456 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
457 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
458 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
459 /* SoC internal pull up required */
460 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b040
461 /* SoC internal pull up required */
462 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b040
466 pinctrl_vcc_mmc: vccmmcgrp {
468 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x58
472 pinctrl_vcc_mmc_io: vccmmciogrp {
474 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x58