arch/arm/boot/dts/imx6qdl-sabresd.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2012 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include <dt-bindings/clock/imx6qdl-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9
  10 / {
  11         chosen {
  12                 stdout-path = &uart1;
  13         };
  14
  15         memory@10000000 {
  16                 device_type = "memory";
  17                 reg = <0x10000000 0x40000000>;
  18         };
  19
  20         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  21                 compatible = "regulator-fixed";
  22                 regulator-name = "usb_otg_vbus";
  23                 regulator-min-microvolt = <5000000>;
  24                 regulator-max-microvolt = <5000000>;
  25                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  26                 enable-active-high;
  27                 vin-supply = <&swbst_reg>;
  28         };
  29
  30         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "usb_h1_vbus";
  33                 regulator-min-microvolt = <5000000>;
  34                 regulator-max-microvolt = <5000000>;
  35                 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  36                 enable-active-high;
  37                 vin-supply = <&swbst_reg>;
  38         };
  39
  40         reg_audio: regulator-audio {
  41                 compatible = "regulator-fixed";
  42                 regulator-name = "wm8962-supply";
  43                 gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
  44                 enable-active-high;
  45         };
  46
  47         reg_pcie: regulator-pcie {
  48                 compatible = "regulator-fixed";
  49                 pinctrl-names = "default";
  50                 pinctrl-0 = <&pinctrl_pcie_reg>;
  51                 regulator-name = "MPCIE_3V3";
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  55                 enable-active-high;
  56         };
  57
  58         reg_sensors: regulator-sensors {
  59                 compatible = "regulator-fixed";
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pinctrl_sensors_reg>;
  62                 regulator-name = "sensors-supply";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
  66                 enable-active-high;
  67         };
  68
  69         gpio-keys {
  70                 compatible = "gpio-keys";
  71                 pinctrl-names = "default";
  72                 pinctrl-0 = <&pinctrl_gpio_keys>;
  73
  74                 power {
  75                         label = "Power Button";
  76                         gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
  77                         wakeup-source;
  78                         linux,code = <KEY_POWER>;
  79                 };
  80
  81                 volume-up {
  82                         label = "Volume Up";
  83                         gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
  84                         wakeup-source;
  85                         linux,code = <KEY_VOLUMEUP>;
  86                 };
  87
  88                 volume-down {
  89                         label = "Volume Down";
  90                         gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
  91                         wakeup-source;
  92                         linux,code = <KEY_VOLUMEDOWN>;
  93                 };
  94         };
  95
  96         sound {
  97                 compatible = "fsl,imx6q-sabresd-wm8962",
  98                            "fsl,imx-audio-wm8962";
  99                 model = "wm8962-audio";
 100                 ssi-controller = <&ssi2>;
 101                 audio-codec = <&codec>;
 102                 audio-routing =
 103                         "Headphone Jack", "HPOUTL",
 104                         "Headphone Jack", "HPOUTR",
 105                         "Ext Spk", "SPKOUTL",
 106                         "Ext Spk", "SPKOUTR",
 107                         "AMIC", "MICBIAS",
 108                         "IN3R", "AMIC";
 109                 mux-int-port = <2>;
 110                 mux-ext-port = <3>;
 111         };
 112
 113         backlight_lvds: backlight-lvds {
 114                 compatible = "pwm-backlight";
 115                 pwms = <&pwm1 0 5000000>;
 116                 brightness-levels = <0 4 8 16 32 64 128 255>;
 117                 default-brightness-level = <7>;
 118                 status = "okay";
 119         };
 120
 121         leds {
 122                 compatible = "gpio-leds";
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&pinctrl_gpio_leds>;
 125
 126                 red {
 127                         gpios = <&gpio1 2 0>;
 128                         default-state = "on";
 129                 };
 130         };
 131
 132         panel {
 133                 compatible = "hannstar,hsd100pxn1";
 134                 backlight = <&backlight_lvds>;
 135
 136                 port {
 137                         panel_in: endpoint {
 138                                 remote-endpoint = <&lvds0_out>;
 139                         };
 140                 };
 141         };
 142 };
 143
 144 &ipu1_csi0_from_ipu1_csi0_mux {
 145         bus-width = <8>;
 146         data-shift = <12>; /* Lines 19:12 used */
 147         hsync-active = <1>;
 148         vsync-active = <1>;
 149 };
 150
 151 &ipu1_csi0_mux_from_parallel_sensor {
 152         remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
 153 };
 154
 155 &ipu1_csi0 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 158 };
 159
 160 &mipi_csi {
 161         status = "okay";
 162
 163         port@0 {
 164                 reg = <0>;
 165
 166                 mipi_csi2_in: endpoint {
 167                         remote-endpoint = <&ov5640_to_mipi_csi2>;
 168                         clock-lanes = <0>;
 169                         data-lanes = <1 2>;
 170                 };
 171         };
 172 };
 173
 174 &audmux {
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_audmux>;
 177         status = "okay";
 178 };
 179
 180 &clks {
 181         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 182                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 183         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 184                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 185 };
 186
 187 &ecspi1 {
 188         cs-gpios = <&gpio4 9 0>;
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_ecspi1>;
 191         status = "okay";
 192
 193         flash: m25p80@0 {
 194                 #address-cells = <1>;
 195                 #size-cells = <1>;
 196                 compatible = "st,m25p32", "jedec,spi-nor";
 197                 spi-max-frequency = <20000000>;
 198                 reg = <0>;
 199         };
 200 };
 201
 202 &fec {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_enet>;
 205         phy-mode = "rgmii-id";
 206         phy-handle = <&phy>;
 207         fsl,magic-packet;
 208         status = "okay";
 209
 210         mdio {
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213
 214                 phy: ethernet-phy@1 {
 215                         reg = <1>;
 216                         qca,clk-out-frequency = <125000000>;
 217                         reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 218                         reset-assert-us = <10000>;
 219                 };
 220         };
 221 };
 222
 223 &hdmi {
 224         pinctrl-names = "default";
 225         pinctrl-0 = <&pinctrl_hdmi_cec>;
 226         ddc-i2c-bus = <&i2c2>;
 227         status = "okay";
 228 };
 229
 230 &i2c1 {
 231         clock-frequency = <100000>;
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_i2c1>;
 234         status = "okay";
 235
 236         codec: wm8962@1a {
 237                 compatible = "wlf,wm8962";
 238                 reg = <0x1a>;
 239                 clocks = <&clks IMX6QDL_CLK_CKO>;
 240                 DCVDD-supply = <&reg_audio>;
 241                 DBVDD-supply = <&reg_audio>;
 242                 AVDD-supply = <&reg_audio>;
 243                 CPVDD-supply = <&reg_audio>;
 244                 MICVDD-supply = <&reg_audio>;
 245                 PLLVDD-supply = <&reg_audio>;
 246                 SPKVDD1-supply = <&reg_audio>;
 247                 SPKVDD2-supply = <&reg_audio>;
 248                 gpio-cfg = <
 249                         0x0000 /* 0:Default */
 250                         0x0000 /* 1:Default */
 251                         0x0013 /* 2:FN_DMICCLK */
 252                         0x0000 /* 3:Default */
 253                         0x8014 /* 4:FN_DMICCDAT */
 254                         0x0000 /* 5:Default */
 255                 >;
 256         };
 257
 258         accelerometer@1c {
 259                 compatible = "fsl,mma8451";
 260                 reg = <0x1c>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&pinctrl_i2c1_mma8451_int>;
 263                 interrupt-parent = <&gpio1>;
 264                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 265                 vdd-supply = <&reg_sensors>;
 266                 vddio-supply = <&reg_sensors>;
 267         };
 268
 269         ov5642: camera@3c {
 270                 compatible = "ovti,ov5642";
 271                 pinctrl-names = "default";
 272                 pinctrl-0 = <&pinctrl_ov5642>;
 273                 clocks = <&clks IMX6QDL_CLK_CKO>;
 274                 clock-names = "xclk";
 275                 reg = <0x3c>;
 276                 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
 277                 AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
 278                                                 rev B board is VGEN5 */
 279                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 280                 powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
 281                 reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
 282                 status = "disabled";
 283
 284                 port {
 285                         ov5642_to_ipu1_csi0_mux: endpoint {
 286                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 287                                 bus-width = <8>;
 288                                 hsync-active = <1>;
 289                                 vsync-active = <1>;
 290                         };
 291                 };
 292         };
 293 };
 294
 295 &i2c2 {
 296         clock-frequency = <100000>;
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_i2c2>;
 299         status = "okay";
 300
 301         touchscreen@4 {
 302                 compatible = "eeti,egalax_ts";
 303                 reg = <0x04>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
 306                 interrupt-parent = <&gpio6>;
 307                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 308                 wakeup-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
 309         };
 310
 311         ov5640: camera@3c {
 312                 compatible = "ovti,ov5640";
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&pinctrl_ov5640>;
 315                 reg = <0x3c>;
 316                 clocks = <&clks IMX6QDL_CLK_CKO>;
 317                 clock-names = "xclk";
 318                 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
 319                 AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
 320                                                 rev B board is VGEN5 */
 321                 DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
 322                 powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
 323                 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
 324
 325                 port {
 326                         ov5640_to_mipi_csi2: endpoint {
 327                                 remote-endpoint = <&mipi_csi2_in>;
 328                                 clock-lanes = <0>;
 329                                 data-lanes = <1 2>;
 330                         };
 331                 };
 332         };
 333
 334         pmic: pfuze100@8 {
 335                 compatible = "fsl,pfuze100";
 336                 reg = <0x08>;
 337
 338                 regulators {
 339                         sw1a_reg: sw1ab {
 340                                 regulator-min-microvolt = <300000>;
 341                                 regulator-max-microvolt = <1875000>;
 342                                 regulator-boot-on;
 343                                 regulator-always-on;
 344                                 regulator-ramp-delay = <6250>;
 345                         };
 346
 347                         sw1c_reg: sw1c {
 348                                 regulator-min-microvolt = <300000>;
 349                                 regulator-max-microvolt = <1875000>;
 350                                 regulator-boot-on;
 351                                 regulator-always-on;
 352                                 regulator-ramp-delay = <6250>;
 353                         };
 354
 355                         sw2_reg: sw2 {
 356                                 regulator-min-microvolt = <800000>;
 357                                 regulator-max-microvolt = <3300000>;
 358                                 regulator-boot-on;
 359                                 regulator-always-on;
 360                                 regulator-ramp-delay = <6250>;
 361                         };
 362
 363                         sw3a_reg: sw3a {
 364                                 regulator-min-microvolt = <400000>;
 365                                 regulator-max-microvolt = <1975000>;
 366                                 regulator-boot-on;
 367                                 regulator-always-on;
 368                         };
 369
 370                         sw3b_reg: sw3b {
 371                                 regulator-min-microvolt = <400000>;
 372                                 regulator-max-microvolt = <1975000>;
 373                                 regulator-boot-on;
 374                                 regulator-always-on;
 375                         };
 376
 377                         sw4_reg: sw4 {
 378                                 regulator-min-microvolt = <800000>;
 379                                 regulator-max-microvolt = <3300000>;
 380                                 regulator-always-on;
 381                         };
 382
 383                         swbst_reg: swbst {
 384                                 regulator-min-microvolt = <5000000>;
 385                                 regulator-max-microvolt = <5150000>;
 386                         };
 387
 388                         snvs_reg: vsnvs {
 389                                 regulator-min-microvolt = <1000000>;
 390                                 regulator-max-microvolt = <3000000>;
 391                                 regulator-boot-on;
 392                                 regulator-always-on;
 393                         };
 394
 395                         vref_reg: vrefddr {
 396                                 regulator-boot-on;
 397                                 regulator-always-on;
 398                         };
 399
 400                         vgen1_reg: vgen1 {
 401                                 regulator-min-microvolt = <800000>;
 402                                 regulator-max-microvolt = <1550000>;
 403                         };
 404
 405                         vgen2_reg: vgen2 {
 406                                 regulator-min-microvolt = <800000>;
 407                                 regulator-max-microvolt = <1550000>;
 408                         };
 409
 410                         vgen3_reg: vgen3 {
 411                                 regulator-min-microvolt = <1800000>;
 412                                 regulator-max-microvolt = <3300000>;
 413                         };
 414
 415                         vgen4_reg: vgen4 {
 416                                 regulator-min-microvolt = <1800000>;
 417                                 regulator-max-microvolt = <3300000>;
 418                                 regulator-always-on;
 419                         };
 420
 421                         vgen5_reg: vgen5 {
 422                                 regulator-min-microvolt = <1800000>;
 423                                 regulator-max-microvolt = <3300000>;
 424                                 regulator-always-on;
 425                         };
 426
 427                         vgen6_reg: vgen6 {
 428                                 regulator-min-microvolt = <1800000>;
 429                                 regulator-max-microvolt = <3300000>;
 430                                 regulator-always-on;
 431                         };
 432                 };
 433         };
 434 };
 435
 436 &i2c3 {
 437         clock-frequency = <100000>;
 438         pinctrl-names = "default";
 439         pinctrl-0 = <&pinctrl_i2c3>;
 440         status = "okay";
 441
 442         egalax_ts@4 {
 443                 compatible = "eeti,egalax_ts";
 444                 reg = <0x04>;
 445                 interrupt-parent = <&gpio6>;
 446                 interrupts = <7 2>;
 447                 wakeup-gpios = <&gpio6 7 0>;
 448         };
 449
 450         magnetometer@e {
 451                 compatible = "fsl,mag3110";
 452                 reg = <0x0e>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&pinctrl_i2c3_mag3110_int>;
 455                 interrupt-parent = <&gpio3>;
 456                 interrupts = <16 IRQ_TYPE_EDGE_RISING>;
 457                 vdd-supply = <&reg_sensors>;
 458                 vddio-supply = <&reg_sensors>;
 459         };
 460
 461         light-sensor@44 {
 462                 compatible = "isil,isl29023";
 463                 reg = <0x44>;
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&pinctrl_i2c3_isl29023_int>;
 466                 interrupt-parent = <&gpio3>;
 467                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 468                 vcc-supply = <&reg_sensors>;
 469         };
 470 };
 471
 472 &iomuxc {
 473         pinctrl-names = "default";
 474         pinctrl-0 = <&pinctrl_hog>;
 475
 476         imx6qdl-sabresd {
 477                 pinctrl_hog: hoggrp {
 478                         fsl,pins = <
 479                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
 480                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
 481                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
 482                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
 483                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
 484                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
 485                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
 486                                 MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
 487                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
 488                         >;
 489                 };
 490
 491                 pinctrl_audmux: audmuxgrp {
 492                         fsl,pins = <
 493                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 494                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 495                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 496                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 497                         >;
 498                 };
 499
 500                 pinctrl_ecspi1: ecspi1grp {
 501                         fsl,pins = <
 502                                 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 503                                 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 504                                 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 505                                 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
 506                         >;
 507                 };
 508
 509                 pinctrl_enet: enetgrp {
 510                         fsl,pins = <
 511                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 512                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 513                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 514                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 515                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 516                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 517                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 518                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 519                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 520                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 521                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 522                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 523                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 524                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 525                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 526                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 527                         >;
 528                 };
 529
 530                 pinctrl_gpio_keys: gpio_keysgrp {
 531                         fsl,pins = <
 532                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
 533                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04  0x1b0b0
 534                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05  0x1b0b0
 535                         >;
 536                 };
 537
 538                 pinctrl_hdmi_cec: hdmicecgrp {
 539                         fsl,pins = <
 540                                 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE   0x1f8b0
 541                         >;
 542                 };
 543
 544                 pinctrl_i2c1: i2c1grp {
 545                         fsl,pins = <
 546                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 547                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 548                         >;
 549                 };
 550
 551                 pinctrl_i2c1_mma8451_int: i2c1mma8451intgrp {
 552                         fsl,pins = <
 553                                 MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0xb0b1
 554                         >;
 555                 };
 556
 557                 pinctrl_i2c2: i2c2grp {
 558                         fsl,pins = <
 559                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 560                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 561                         >;
 562                 };
 563
 564                 pinctrl_i2c2_egalax_int: i2c2egalaxintgrp {
 565                         fsl,pins = <
 566                                 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b0
 567                         >;
 568                 };
 569
 570                 pinctrl_i2c3: i2c3grp {
 571                         fsl,pins = <
 572                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 573                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 574                         >;
 575                 };
 576
 577                 pinctrl_i2c3_isl29023_int: i2c3isl29023intgrp {
 578                         fsl,pins = <
 579                                 MX6QDL_PAD_EIM_DA9__GPIO3_IO09          0xb0b1
 580                         >;
 581                 };
 582
 583                 pinctrl_i2c3_mag3110_int: i2c3mag3110intgrp {
 584                         fsl,pins = <
 585                                 MX6QDL_PAD_EIM_D16__GPIO3_IO16          0xb0b1
 586                         >;
 587                 };
 588
 589                 pinctrl_ipu1_csi0: ipu1csi0grp {
 590                         fsl,pins = <
 591                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
 592                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
 593                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
 594                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
 595                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
 596                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
 597                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
 598                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
 599                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
 600                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
 601                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
 602                         >;
 603                 };
 604
 605                 pinctrl_ov5640: ov5640grp {
 606                         fsl,pins = <
 607                                 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
 608                                 MX6QDL_PAD_SD1_CLK__GPIO1_IO20  0x1b0b0
 609                         >;
 610                 };
 611
 612                 pinctrl_ov5642: ov5642grp {
 613                         fsl,pins = <
 614                                 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
 615                                 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
 616                         >;
 617                 };
 618
 619                 pinctrl_pcie: pciegrp {
 620                         fsl,pins = <
 621                                 MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b0
 622                         >;
 623                 };
 624
 625                 pinctrl_pcie_reg: pciereggrp {
 626                         fsl,pins = <
 627                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x1b0b0
 628                         >;
 629                 };
 630
 631                 pinctrl_pwm1: pwm1grp {
 632                         fsl,pins = <
 633                                 MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
 634                         >;
 635                 };
 636
 637                 pinctrl_sensors_reg: sensorsreggrp {
 638                         fsl,pins = <
 639                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31          0x1b0b0
 640                         >;
 641                 };
 642
 643                 pinctrl_uart1: uart1grp {
 644                         fsl,pins = <
 645                                 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 646                                 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 647                         >;
 648                 };
 649
 650                 pinctrl_usbotg: usbotggrp {
 651                         fsl,pins = <
 652                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
 653                         >;
 654                 };
 655
 656                 pinctrl_usdhc2: usdhc2grp {
 657                         fsl,pins = <
 658                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 659                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 660                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 661                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 662                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 663                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 664                                 MX6QDL_PAD_NANDF_D4__SD2_DATA4          0x17059
 665                                 MX6QDL_PAD_NANDF_D5__SD2_DATA5          0x17059
 666                                 MX6QDL_PAD_NANDF_D6__SD2_DATA6          0x17059
 667                                 MX6QDL_PAD_NANDF_D7__SD2_DATA7          0x17059
 668                         >;
 669                 };
 670
 671                 pinctrl_usdhc3: usdhc3grp {
 672                         fsl,pins = <
 673                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 674                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 675                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 676                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 677                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 678                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 679                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 680                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 681                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 682                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 683                         >;
 684                 };
 685
 686                 pinctrl_usdhc4: usdhc4grp {
 687                         fsl,pins = <
 688                                 MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
 689                                 MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
 690                                 MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
 691                                 MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
 692                                 MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
 693                                 MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
 694                                 MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
 695                                 MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
 696                                 MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
 697                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
 698                         >;
 699                 };
 700
 701                 pinctrl_wdog: wdoggrp {
 702                         fsl,pins = <
 703                                 MX6QDL_PAD_GPIO_1__WDOG2_B              0x1b0b0
 704                         >;
 705                 };
 706         };
 707
 708         gpio_leds {
 709                 pinctrl_gpio_leds: gpioledsgrp {
 710                         fsl,pins = <
 711                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
 712                         >;
 713                 };
 714         };
 715 };
 716
 717 &ldb {
 718         status = "okay";
 719
 720         lvds-channel@1 {
 721                 fsl,data-mapping = "spwg";
 722                 fsl,data-width = <18>;
 723                 status = "okay";
 724
 725                 port@4 {
 726                         reg = <4>;
 727
 728                         lvds0_out: endpoint {
 729                                 remote-endpoint = <&panel_in>;
 730                         };
 731                 };
 732         };
 733 };
 734
 735 &pcie {
 736         pinctrl-names = "default";
 737         pinctrl-0 = <&pinctrl_pcie>;
 738         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 739         vpcie-supply = <&reg_pcie>;
 740         status = "okay";
 741 };
 742
 743 &pwm1 {
 744         #pwm-cells = <2>;
 745         pinctrl-names = "default";
 746         pinctrl-0 = <&pinctrl_pwm1>;
 747         status = "okay";
 748 };
 749
 750 &reg_arm {
 751        vin-supply = <&sw1a_reg>;
 752 };
 753
 754 &reg_pu {
 755        vin-supply = <&sw1c_reg>;
 756 };
 757
 758 &reg_soc {
 759        vin-supply = <&sw1c_reg>;
 760 };
 761
 762 &reg_vdd1p1 {
 763         vin-supply = <&vgen5_reg>;
 764 };
 765
 766 &reg_vdd2p5 {
 767         vin-supply = <&vgen5_reg>;
 768 };
 769
 770 &snvs_poweroff {
 771         status = "okay";
 772 };
 773
 774 &snvs_pwrkey {
 775         status = "okay";
 776 };
 777
 778 &ssi2 {
 779         status = "okay";
 780 };
 781
 782 &uart1 {
 783         pinctrl-names = "default";
 784         pinctrl-0 = <&pinctrl_uart1>;
 785         status = "okay";
 786 };
 787
 788 &usbh1 {
 789         vbus-supply = <&reg_usb_h1_vbus>;
 790         status = "okay";
 791 };
 792
 793 &usbotg {
 794         vbus-supply = <&reg_usb_otg_vbus>;
 795         pinctrl-names = "default";
 796         pinctrl-0 = <&pinctrl_usbotg>;
 797         disable-over-current;
 798         status = "okay";
 799 };
 800
 801 &usdhc2 {
 802         pinctrl-names = "default";
 803         pinctrl-0 = <&pinctrl_usdhc2>;
 804         bus-width = <8>;
 805         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 806         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 807         status = "okay";
 808 };
 809
 810 &usdhc3 {
 811         pinctrl-names = "default";
 812         pinctrl-0 = <&pinctrl_usdhc3>;
 813         bus-width = <8>;
 814         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 815         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 816         status = "okay";
 817 };
 818
 819 &usdhc4 {
 820         pinctrl-names = "default";
 821         pinctrl-0 = <&pinctrl_usdhc4>;
 822         bus-width = <8>;
 823         non-removable;
 824         no-1-8-v;
 825         status = "okay";
 826 };
 827
 828 &wdog1 {
 829         status = "disabled";
 830 };
 831
 832 &wdog2 {
 833         pinctrl-names = "default";
 834         pinctrl-0 = <&pinctrl_wdog>;
 835         fsl,ext-reset-output;
 836         status = "okay";
 837 };