arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2012 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8
   9 / {
  10         chosen {
  11                 stdout-path = &uart4;
  12         };
  13
  14         memory@10000000 {
  15                 reg = <0x10000000 0x80000000>;
  16         };
  17
  18         leds {
  19                 compatible = "gpio-leds";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_gpio_leds>;
  22
  23                 user {
  24                         label = "debug";
  25                         gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
  26                 };
  27         };
  28
  29         gpio-keys {
  30                 compatible = "gpio-keys";
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_gpio_keys>;
  33
  34                 home {
  35                         label = "Home";
  36                         gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_HOME>;
  38                         wakeup-source;
  39                 };
  40
  41                 back {
  42                         label = "Back";
  43                         gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
  44                         linux,code = <KEY_BACK>;
  45                         wakeup-source;
  46                 };
  47
  48                 program {
  49                         label = "Program";
  50                         gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  51                         linux,code = <KEY_PROGRAM>;
  52                         wakeup-source;
  53                 };
  54
  55                 volume-up {
  56                         label = "Volume Up";
  57                         gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
  58                         linux,code = <KEY_VOLUMEUP>;
  59                         wakeup-source;
  60                 };
  61
  62                 volume-down {
  63                         label = "Volume Down";
  64                         gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
  65                         linux,code = <KEY_VOLUMEDOWN>;
  66                         wakeup-source;
  67                 };
  68         };
  69
  70         clocks {
  71                 codec_osc: anaclk2 {
  72                         compatible = "fixed-clock";
  73                         #clock-cells = <0>;
  74                         clock-frequency = <24576000>;
  75                 };
  76         };
  77
  78         regulators {
  79                 compatible = "simple-bus";
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 reg_audio: regulator@0 {
  84                         compatible = "regulator-fixed";
  85                         reg = <0>;
  86                         regulator-name = "cs42888_supply";
  87                         regulator-min-microvolt = <3300000>;
  88                         regulator-max-microvolt = <3300000>;
  89                         regulator-always-on;
  90                 };
  91
  92                 reg_usb_h1_vbus: regulator@1 {
  93                         compatible = "regulator-fixed";
  94                         reg = <1>;
  95                         regulator-name = "usb_h1_vbus";
  96                         regulator-min-microvolt = <5000000>;
  97                         regulator-max-microvolt = <5000000>;
  98                         gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
  99                         enable-active-high;
 100                 };
 101
 102                 reg_usb_otg_vbus: regulator@2 {
 103                         compatible = "regulator-fixed";
 104                         reg = <2>;
 105                         regulator-name = "usb_otg_vbus";
 106                         regulator-min-microvolt = <5000000>;
 107                         regulator-max-microvolt = <5000000>;
 108                         gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
 109                         enable-active-high;
 110                 };
 111         };
 112
 113         sound-cs42888 {
 114                 compatible = "fsl,imx6-sabreauto-cs42888",
 115                         "fsl,imx-audio-cs42888";
 116                 model = "imx-cs42888";
 117                 audio-cpu = <&esai>;
 118                 audio-asrc = <&asrc>;
 119                 audio-codec = <&codec>;
 120                 audio-routing =
 121                         "Line Out Jack", "AOUT1L",
 122                         "Line Out Jack", "AOUT1R",
 123                         "Line Out Jack", "AOUT2L",
 124                         "Line Out Jack", "AOUT2R",
 125                         "Line Out Jack", "AOUT3L",
 126                         "Line Out Jack", "AOUT3R",
 127                         "Line Out Jack", "AOUT4L",
 128                         "Line Out Jack", "AOUT4R",
 129                         "AIN1L", "Line In Jack",
 130                         "AIN1R", "Line In Jack",
 131                         "AIN2L", "Line In Jack",
 132                         "AIN2R", "Line In Jack";
 133         };
 134
 135         sound-spdif {
 136                 compatible = "fsl,imx-audio-spdif",
 137                            "fsl,imx-sabreauto-spdif";
 138                 model = "imx-spdif";
 139                 spdif-controller = <&spdif>;
 140                 spdif-in;
 141         };
 142
 143         backlight {
 144                 compatible = "pwm-backlight";
 145                 pwms = <&pwm3 0 5000000>;
 146                 brightness-levels = <0 4 8 16 32 64 128 255>;
 147                 default-brightness-level = <7>;
 148                 status = "okay";
 149         };
 150
 151         i2cmux {
 152                 compatible = "i2c-mux-gpio";
 153                 #address-cells = <1>;
 154                 #size-cells = <0>;
 155                 pinctrl-names = "default";
 156                 pinctrl-0 = <&pinctrl_i2c3mux>;
 157                 mux-gpios = <&gpio5 4 0>;
 158                 i2c-parent = <&i2c3>;
 159                 idle-state = <0>;
 160
 161                 i2c@1 {
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         reg = <1>;
 165
 166                         adv7180: camera@21 {
 167                                 compatible = "adi,adv7180";
 168                                 reg = <0x21>;
 169                                 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
 170                                 interrupt-parent = <&gpio1>;
 171                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
 172
 173                                 port {
 174                                         adv7180_to_ipu1_csi0_mux: endpoint {
 175                                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 176                                                 bus-width = <8>;
 177                                         };
 178                                 };
 179                         };
 180
 181                         max7310_a: gpio@30 {
 182                                 compatible = "maxim,max7310";
 183                                 reg = <0x30>;
 184                                 gpio-controller;
 185                                 #gpio-cells = <2>;
 186                         };
 187
 188                         max7310_b: gpio@32 {
 189                                 compatible = "maxim,max7310";
 190                                 reg = <0x32>;
 191                                 gpio-controller;
 192                                 #gpio-cells = <2>;
 193                                 pinctrl-names = "default";
 194                                 pinctrl-0 = <&pinctrl_max7310>;
 195                                 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 196                         };
 197
 198                         max7310_c: gpio@34 {
 199                                 compatible = "maxim,max7310";
 200                                 reg = <0x34>;
 201                                 gpio-controller;
 202                                 #gpio-cells = <2>;
 203                         };
 204
 205                         light-sensor@44 {
 206                                 compatible = "isil,isl29023";
 207                                 reg = <0x44>;
 208                                 interrupt-parent = <&gpio5>;
 209                                 interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
 210                         };
 211
 212                         magnetometer@e {
 213                                 compatible = "fsl,mag3110";
 214                                 reg = <0x0e>;
 215                                 interrupt-parent = <&gpio2>;
 216                                 interrupts = <29 IRQ_TYPE_EDGE_RISING>;
 217                         };
 218
 219                         accelerometer@1c {
 220                                 compatible = "fsl,mma8451";
 221                                 reg = <0x1c>;
 222                                 interrupt-parent = <&gpio6>;
 223                                 interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
 224                         };
 225                 };
 226         };
 227 };
 228
 229 &ipu1_csi0_from_ipu1_csi0_mux {
 230         bus-width = <8>;
 231 };
 232
 233 &ipu1_csi0_mux_from_parallel_sensor {
 234         remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
 235         bus-width = <8>;
 236 };
 237
 238 &ipu1_csi0 {
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 241 };
 242
 243 &clks {
 244         assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 245                           <&clks IMX6QDL_PLL4_BYPASS>,
 246                           <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 247                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 248                           <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
 249         assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
 250                                  <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 251                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 252                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 253         assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
 254 };
 255
 256 &ecspi1 {
 257         cs-gpios = <&gpio3 19 0>;
 258         pinctrl-names = "default";
 259         pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
 260         status = "disabled"; /* pin conflict with WEIM NOR */
 261
 262         flash: m25p80@0 {
 263                 #address-cells = <1>;
 264                 #size-cells = <1>;
 265                 compatible = "st,m25p32", "jedec,spi-nor";
 266                 spi-max-frequency = <20000000>;
 267                 reg = <0>;
 268         };
 269 };
 270
 271 &esai {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_esai>;
 274         assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
 275                           <&clks IMX6QDL_CLK_ESAI_EXTAL>;
 276         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
 277         assigned-clock-rates = <0>, <24576000>;
 278         status = "okay";
 279 };
 280
 281 &fec {
 282         pinctrl-names = "default";
 283         pinctrl-0 = <&pinctrl_enet>;
 284         phy-mode = "rgmii";
 285         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 286                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 287         fsl,err006687-workaround-present;
 288         status = "okay";
 289 };
 290
 291 &gpmi {
 292         pinctrl-names = "default";
 293         pinctrl-0 = <&pinctrl_gpmi_nand>;
 294         status = "okay";
 295 };
 296
 297 &hdmi {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&pinctrl_hdmi_cec>;
 300         ddc-i2c-bus = <&i2c2>;
 301         status = "okay";
 302 };
 303
 304 &i2c2 {
 305         clock-frequency = <100000>;
 306         pinctrl-names = "default";
 307         pinctrl-0 = <&pinctrl_i2c2>;
 308         status = "okay";
 309
 310         pmic: pfuze100@8 {
 311                 compatible = "fsl,pfuze100";
 312                 reg = <0x08>;
 313
 314                 regulators {
 315                         sw1a_reg: sw1ab {
 316                                 regulator-min-microvolt = <300000>;
 317                                 regulator-max-microvolt = <1875000>;
 318                                 regulator-boot-on;
 319                                 regulator-always-on;
 320                                 regulator-ramp-delay = <6250>;
 321                         };
 322
 323                         sw1c_reg: sw1c {
 324                                 regulator-min-microvolt = <300000>;
 325                                 regulator-max-microvolt = <1875000>;
 326                                 regulator-boot-on;
 327                                 regulator-always-on;
 328                                 regulator-ramp-delay = <6250>;
 329                         };
 330
 331                         sw2_reg: sw2 {
 332                                 regulator-min-microvolt = <800000>;
 333                                 regulator-max-microvolt = <3300000>;
 334                                 regulator-boot-on;
 335                                 regulator-always-on;
 336                         };
 337
 338                         sw3a_reg: sw3a {
 339                                 regulator-min-microvolt = <400000>;
 340                                 regulator-max-microvolt = <1975000>;
 341                                 regulator-boot-on;
 342                                 regulator-always-on;
 343                         };
 344
 345                         sw3b_reg: sw3b {
 346                                 regulator-min-microvolt = <400000>;
 347                                 regulator-max-microvolt = <1975000>;
 348                                 regulator-boot-on;
 349                                 regulator-always-on;
 350                         };
 351
 352                         sw4_reg: sw4 {
 353                                 regulator-min-microvolt = <800000>;
 354                                 regulator-max-microvolt = <3300000>;
 355                         };
 356
 357                         swbst_reg: swbst {
 358                                 regulator-min-microvolt = <5000000>;
 359                                 regulator-max-microvolt = <5150000>;
 360                         };
 361
 362                         snvs_reg: vsnvs {
 363                                 regulator-min-microvolt = <1000000>;
 364                                 regulator-max-microvolt = <3000000>;
 365                                 regulator-boot-on;
 366                                 regulator-always-on;
 367                         };
 368
 369                         vref_reg: vrefddr {
 370                                 regulator-boot-on;
 371                                 regulator-always-on;
 372                         };
 373
 374                         vgen1_reg: vgen1 {
 375                                 regulator-min-microvolt = <800000>;
 376                                 regulator-max-microvolt = <1550000>;
 377                         };
 378
 379                         vgen2_reg: vgen2 {
 380                                 regulator-min-microvolt = <800000>;
 381                                 regulator-max-microvolt = <1550000>;
 382                         };
 383
 384                         vgen3_reg: vgen3 {
 385                                 regulator-min-microvolt = <1800000>;
 386                                 regulator-max-microvolt = <3300000>;
 387                         };
 388
 389                         vgen4_reg: vgen4 {
 390                                 regulator-min-microvolt = <1800000>;
 391                                 regulator-max-microvolt = <3300000>;
 392                                 regulator-always-on;
 393                         };
 394
 395                         vgen5_reg: vgen5 {
 396                                 regulator-min-microvolt = <1800000>;
 397                                 regulator-max-microvolt = <3300000>;
 398                                 regulator-always-on;
 399                         };
 400
 401                         vgen6_reg: vgen6 {
 402                                 regulator-min-microvolt = <1800000>;
 403                                 regulator-max-microvolt = <3300000>;
 404                                 regulator-always-on;
 405                         };
 406                 };
 407         };
 408
 409         codec: cs42888@48 {
 410                 compatible = "cirrus,cs42888";
 411                 reg = <0x48>;
 412                 clocks = <&codec_osc>;
 413                 clock-names = "mclk";
 414                 VA-supply = <&reg_audio>;
 415                 VD-supply = <&reg_audio>;
 416                 VLS-supply = <&reg_audio>;
 417                 VLC-supply = <&reg_audio>;
 418         };
 419
 420 };
 421
 422 &i2c3 {
 423         pinctrl-names = "default";
 424         pinctrl-0 = <&pinctrl_i2c3>;
 425         status = "okay";
 426 };
 427
 428 &iomuxc {
 429         pinctrl-names = "default";
 430         pinctrl-0 = <&pinctrl_hog>;
 431
 432         imx6qdl-sabreauto {
 433                 pinctrl_hog: hoggrp {
 434                         fsl,pins = <
 435                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
 436                                 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 437                                 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
 438                         >;
 439                 };
 440
 441                 pinctrl_ecspi1: ecspi1grp {
 442                         fsl,pins = <
 443                                 MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 444                                 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 445                                 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 446                         >;
 447                 };
 448
 449                 pinctrl_ecspi1_cs: ecspi1cs {
 450                         fsl,pins = <
 451                                 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
 452                         >;
 453                 };
 454
 455                 pinctrl_enet: enetgrp {
 456                         fsl,pins = <
 457                                 MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
 458                                 MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
 459                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 460                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 461                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 462                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 463                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 464                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 465                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 466                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 467                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 468                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 469                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 470                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 471                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 472                                 MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
 473                         >;
 474                 };
 475
 476                 pinctrl_esai: esaigrp {
 477                         fsl,pins = <
 478                                 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
 479                                 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
 480                                 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
 481                                 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
 482                                 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
 483                                 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
 484                                 MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
 485                                 MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
 486                                 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
 487                                 MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
 488                         >;
 489                 };
 490
 491                 pinctrl_gpio_keys: gpiokeysgrp {
 492                         fsl,pins = <
 493                                 MX6QDL_PAD_SD2_CMD__GPIO1_IO11          0x1b0b0
 494                                 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x1b0b0
 495                                 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12         0x1b0b0
 496                                 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15         0x1b0b0
 497                                 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 498                         >;
 499                 };
 500
 501                 pinctrl_gpio_leds: gpioledsgrp {
 502                         fsl,pins = <
 503                                 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x80000000
 504                         >;
 505                 };
 506
 507                 pinctrl_gpmi_nand: gpminandgrp {
 508                         fsl,pins = <
 509                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 510                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 511                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 512                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 513                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 514                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 515                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 516                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 517                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 518                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 519                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 520                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 521                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 522                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 523                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 524                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 525                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 526                         >;
 527                 };
 528
 529                 pinctrl_hdmi_cec: hdmicecgrp {
 530                         fsl,pins = <
 531                                 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE    0x1f8b0
 532                         >;
 533                 };
 534
 535                 pinctrl_i2c2: i2c2grp {
 536                         fsl,pins = <
 537                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
 538                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 539                         >;
 540                 };
 541
 542                 pinctrl_i2c3: i2c3grp {
 543                         fsl,pins = <
 544                                 MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
 545                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 546                         >;
 547                 };
 548
 549                 pinctrl_i2c3mux: i2c3muxgrp {
 550                         fsl,pins = <
 551                                 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
 552                         >;
 553                 };
 554
 555                 pinctrl_ipu1_csi0: ipu1csi0grp {
 556                         fsl,pins = <
 557                                 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x1b0b0
 558                                 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x1b0b0
 559                                 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x1b0b0
 560                                 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x1b0b0
 561                                 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x1b0b0
 562                                 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x1b0b0
 563                                 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x1b0b0
 564                                 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x1b0b0
 565                                 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
 566                                 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x1b0b0
 567                                 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x1b0b0
 568                         >;
 569                 };
 570
 571                 pinctrl_max7310: max7310grp {
 572                         fsl,pins = <
 573                                 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
 574                         >;
 575                 };
 576
 577                 pinctrl_pwm3: pwm1grp {
 578                         fsl,pins = <
 579                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 580                         >;
 581                 };
 582
 583                 pinctrl_gpt_input_capture0: gptinputcapture0grp {
 584                         fsl,pins = <
 585                                 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1       0x1b0b0
 586                         >;
 587                 };
 588
 589                 pinctrl_gpt_input_capture1: gptinputcapture1grp {
 590                         fsl,pins = <
 591                                 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2       0x1b0b0
 592                         >;
 593                 };
 594
 595                 pinctrl_spdif: spdifgrp {
 596                         fsl,pins = <
 597                                 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
 598                         >;
 599                 };
 600
 601                 pinctrl_uart4: uart4grp {
 602                         fsl,pins = <
 603                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 604                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 605                         >;
 606                 };
 607
 608                 pinctrl_usbotg: usbotggrp {
 609                         fsl,pins = <
 610                                 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 611                         >;
 612                 };
 613
 614                 pinctrl_usdhc3: usdhc3grp {
 615                         fsl,pins = <
 616                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 617                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 618                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 619                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 620                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 621                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 622                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 623                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 624                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 625                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 626                         >;
 627                 };
 628
 629                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 630                         fsl,pins = <
 631                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 632                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 633                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 634                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 635                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 636                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 637                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 638                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 639                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 640                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 641                         >;
 642                 };
 643
 644                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 645                         fsl,pins = <
 646                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 647                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 648                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 649                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 650                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 651                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 652                                 MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 653                                 MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 654                                 MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 655                                 MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 656                         >;
 657                 };
 658
 659                 pinctrl_weim_cs0: weimcs0grp {
 660                         fsl,pins = <
 661                                 MX6QDL_PAD_EIM_CS0__EIM_CS0_B           0xb0b1
 662                         >;
 663                 };
 664
 665                 pinctrl_weim_nor: weimnorgrp {
 666                         fsl,pins = <
 667                                 MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 668                                 MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 669                                 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B         0xb060
 670                                 MX6QDL_PAD_EIM_D16__EIM_DATA16          0x1b0b0
 671                                 MX6QDL_PAD_EIM_D17__EIM_DATA17          0x1b0b0
 672                                 MX6QDL_PAD_EIM_D18__EIM_DATA18          0x1b0b0
 673                                 MX6QDL_PAD_EIM_D19__EIM_DATA19          0x1b0b0
 674                                 MX6QDL_PAD_EIM_D20__EIM_DATA20          0x1b0b0
 675                                 MX6QDL_PAD_EIM_D21__EIM_DATA21          0x1b0b0
 676                                 MX6QDL_PAD_EIM_D22__EIM_DATA22          0x1b0b0
 677                                 MX6QDL_PAD_EIM_D23__EIM_DATA23          0x1b0b0
 678                                 MX6QDL_PAD_EIM_D24__EIM_DATA24          0x1b0b0
 679                                 MX6QDL_PAD_EIM_D25__EIM_DATA25          0x1b0b0
 680                                 MX6QDL_PAD_EIM_D26__EIM_DATA26          0x1b0b0
 681                                 MX6QDL_PAD_EIM_D27__EIM_DATA27          0x1b0b0
 682                                 MX6QDL_PAD_EIM_D28__EIM_DATA28          0x1b0b0
 683                                 MX6QDL_PAD_EIM_D29__EIM_DATA29          0x1b0b0
 684                                 MX6QDL_PAD_EIM_D30__EIM_DATA30          0x1b0b0
 685                                 MX6QDL_PAD_EIM_D31__EIM_DATA31          0x1b0b0
 686                                 MX6QDL_PAD_EIM_A23__EIM_ADDR23          0xb0b1
 687                                 MX6QDL_PAD_EIM_A22__EIM_ADDR22          0xb0b1
 688                                 MX6QDL_PAD_EIM_A21__EIM_ADDR21          0xb0b1
 689                                 MX6QDL_PAD_EIM_A20__EIM_ADDR20          0xb0b1
 690                                 MX6QDL_PAD_EIM_A19__EIM_ADDR19          0xb0b1
 691                                 MX6QDL_PAD_EIM_A18__EIM_ADDR18          0xb0b1
 692                                 MX6QDL_PAD_EIM_A17__EIM_ADDR17          0xb0b1
 693                                 MX6QDL_PAD_EIM_A16__EIM_ADDR16          0xb0b1
 694                                 MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 695                                 MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 696                                 MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 697                                 MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 698                                 MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 699                                 MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 700                                 MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 701                                 MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 702                                 MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 703                                 MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 704                                 MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 705                                 MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 706                                 MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 707                                 MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 708                                 MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 709                                 MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 710                         >;
 711                 };
 712         };
 713 };
 714
 715 &ldb {
 716         status = "okay";
 717
 718         lvds-channel@0 {
 719                 fsl,data-mapping = "spwg";
 720                 fsl,data-width = <18>;
 721                 status = "okay";
 722
 723                 display-timings {
 724                         native-mode = <&timing0>;
 725                         timing0: hsd100pxn1 {
 726                                 clock-frequency = <65000000>;
 727                                 hactive = <1024>;
 728                                 vactive = <768>;
 729                                 hback-porch = <220>;
 730                                 hfront-porch = <40>;
 731                                 vback-porch = <21>;
 732                                 vfront-porch = <7>;
 733                                 hsync-len = <60>;
 734                                 vsync-len = <10>;
 735                         };
 736                 };
 737         };
 738 };
 739
 740 &pwm3 {
 741         pinctrl-names = "default";
 742         pinctrl-0 = <&pinctrl_pwm3>;
 743         status = "okay";
 744 };
 745
 746 &spdif {
 747         pinctrl-names = "default";
 748         pinctrl-0 = <&pinctrl_spdif>;
 749         status = "okay";
 750 };
 751
 752 &uart4 {
 753         pinctrl-names = "default";
 754         pinctrl-0 = <&pinctrl_uart4>;
 755         status = "okay";
 756 };
 757
 758 &usbh1 {
 759         vbus-supply = <&reg_usb_h1_vbus>;
 760         status = "okay";
 761 };
 762
 763 &usbotg {
 764         vbus-supply = <&reg_usb_otg_vbus>;
 765         pinctrl-names = "default";
 766         pinctrl-0 = <&pinctrl_usbotg>;
 767         status = "okay";
 768 };
 769
 770 &usdhc3 {
 771         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 772         pinctrl-0 = <&pinctrl_usdhc3>;
 773         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 774         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 775         cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
 776         wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
 777         status = "okay";
 778 };
 779
 780 &weim {
 781         pinctrl-names = "default";
 782         pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
 783         ranges = <0 0 0x08000000 0x08000000>;
 784         status = "disabled"; /* pin conflict with SPI NOR */
 785
 786         nor@0,0 {
 787                 compatible = "cfi-flash";
 788                 reg = <0 0 0x02000000>;
 789                 #address-cells = <1>;
 790                 #size-cells = <1>;
 791                 bank-width = <2>;
 792                 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
 793                                 0x0000c000 0x1404a38e 0x00000000>;
 794         };
 795 };