arch/arm/boot/dts/imx6qdl-gw5913.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9
  10 / {
  11         /* these are used by bootloader for disabling nodes */
  12         aliases {
  13                 led0 = &led0;
  14                 led1 = &led1;
  15                 nand = &gpmi;
  16                 usb0 = &usbh1;
  17                 usb1 = &usbotg;
  18         };
  19
  20         chosen {
  21                 stdout-path = &uart2;
  22         };
  23
  24         gpio-keys {
  25                 compatible = "gpio-keys";
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 user-pb {
  30                         label = "user_pb";
  31                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  32                         linux,code = <BTN_0>;
  33                 };
  34
  35                 user-pb1x {
  36                         label = "user_pb1x";
  37                         linux,code = <BTN_1>;
  38                         interrupt-parent = <&gsc>;
  39                         interrupts = <0>;
  40                 };
  41
  42                 key-erased {
  43                         label = "key-erased";
  44                         linux,code = <BTN_2>;
  45                         interrupt-parent = <&gsc>;
  46                         interrupts = <1>;
  47                 };
  48
  49                 eeprom-wp {
  50                         label = "eeprom_wp";
  51                         linux,code = <BTN_3>;
  52                         interrupt-parent = <&gsc>;
  53                         interrupts = <2>;
  54                 };
  55
  56                 tamper {
  57                         label = "tamper";
  58                         linux,code = <BTN_4>;
  59                         interrupt-parent = <&gsc>;
  60                         interrupts = <5>;
  61                 };
  62
  63                 switch-hold {
  64                         label = "switch_hold";
  65                         linux,code = <BTN_5>;
  66                         interrupt-parent = <&gsc>;
  67                         interrupts = <7>;
  68                 };
  69         };
  70
  71         leds {
  72                 compatible = "gpio-leds";
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&pinctrl_gpio_leds>;
  75
  76                 led0: user1 {
  77                         label = "user1";
  78                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  79                         default-state = "on";
  80                         linux,default-trigger = "heartbeat";
  81                 };
  82
  83                 led1: user2 {
  84                         label = "user2";
  85                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  86                         default-state = "off";
  87                 };
  88         };
  89
  90         memory@10000000 {
  91                 device_type = "memory";
  92                 reg = <0x10000000 0x20000000>;
  93         };
  94
  95         pps {
  96                 compatible = "pps-gpio";
  97                 pinctrl-names = "default";
  98                 pinctrl-0 = <&pinctrl_pps>;
  99                 gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
 100                 status = "okay";
 101         };
 102
 103         reg_3p3v: regulator-3p3v {
 104                 compatible = "regulator-fixed";
 105                 regulator-name = "3P3V";
 106                 regulator-min-microvolt = <3300000>;
 107                 regulator-max-microvolt = <3300000>;
 108                 regulator-always-on;
 109         };
 110
 111         reg_5p0v: regulator-5p0v {
 112                 compatible = "regulator-fixed";
 113                 regulator-name = "5P0V";
 114                 regulator-min-microvolt = <5000000>;
 115                 regulator-max-microvolt = <5000000>;
 116                 regulator-always-on;
 117         };
 118 };
 119
 120 &fec {
 121         pinctrl-names = "default";
 122         pinctrl-0 = <&pinctrl_enet>;
 123         phy-mode = "rgmii-id";
 124         status = "okay";
 125 };
 126
 127 &gpmi {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_gpmi_nand>;
 130         status = "okay";
 131 };
 132
 133 &i2c1 {
 134         clock-frequency = <100000>;
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pinctrl_i2c1>;
 137         status = "okay";
 138
 139         gsc: gsc@20 {
 140                 compatible = "gw,gsc";
 141                 reg = <0x20>;
 142                 interrupt-parent = <&gpio1>;
 143                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 144                 interrupt-controller;
 145                 #interrupt-cells = <1>;
 146                 #size-cells = <0>;
 147
 148                 adc {
 149                         compatible = "gw,gsc-adc";
 150                         #address-cells = <1>;
 151                         #size-cells = <0>;
 152
 153                         channel@6 {
 154                                 gw,mode = <0>;
 155                                 reg = <0x06>;
 156                                 label = "temp";
 157                         };
 158
 159                         channel@8 {
 160                                 gw,mode = <3>;
 161                                 reg = <0x08>;
 162                                 label = "vdd_bat";
 163                         };
 164
 165                         channel@82 {
 166                                 gw,mode = <2>;
 167                                 reg = <0x82>;
 168                                 label = "vdd_vin";
 169                                 gw,voltage-divider-ohms = <22100 1000>;
 170                                 gw,voltage-offset-microvolt = <800000>;
 171                         };
 172
 173                         channel@84 {
 174                                 gw,mode = <2>;
 175                                 reg = <0x84>;
 176                                 label = "vdd_5p0";
 177                                 gw,voltage-divider-ohms = <22100 10000>;
 178                         };
 179
 180                         channel@86 {
 181                                 gw,mode = <2>;
 182                                 reg = <0x86>;
 183                                 label = "vdd_3p3";
 184                                 gw,voltage-divider-ohms = <10000 10000>;
 185                         };
 186
 187                         channel@88 {
 188                                 gw,mode = <2>;
 189                                 reg = <0x88>;
 190                                 label = "vdd_2p5";
 191                                 gw,voltage-divider-ohms = <10000 10000>;
 192                         };
 193
 194                         channel@8c {
 195                                 gw,mode = <2>;
 196                                 reg = <0x8c>;
 197                                 label = "vdd_arm";
 198                         };
 199
 200                         channel@8e {
 201                                 gw,mode = <2>;
 202                                 reg = <0x8e>;
 203                                 label = "vdd_soc";
 204                         };
 205
 206                         channel@90 {
 207                                 gw,mode = <2>;
 208                                 reg = <0x90>;
 209                                 label = "vdd_1p5";
 210                         };
 211
 212                         channel@92 {
 213                                 gw,mode = <2>;
 214                                 reg = <0x92>;
 215                                 label = "vdd_1p0";
 216                         };
 217
 218                         channel@98 {
 219                                 gw,mode = <2>;
 220                                 reg = <0x98>;
 221                                 label = "vdd_3p0";
 222                         };
 223
 224                         channel@9a {
 225                                 gw,mode = <2>;
 226                                 reg = <0x9a>;
 227                                 label = "vdd_an1";
 228                                 gw,voltage-divider-ohms = <10000 10000>;
 229                         };
 230
 231                         channel@a2 {
 232                                 gw,mode = <2>;
 233                                 reg = <0xa2>;
 234                                 label = "vdd_gsc";
 235                                 gw,voltage-divider-ohms = <10000 10000>;
 236                         };
 237                 };
 238         };
 239
 240         gsc_gpio: gpio@23 {
 241                 compatible = "nxp,pca9555";
 242                 reg = <0x23>;
 243                 gpio-controller;
 244                 #gpio-cells = <2>;
 245                 interrupt-parent = <&gsc>;
 246                 interrupts = <4>;
 247         };
 248
 249         eeprom@50 {
 250                 compatible = "atmel,24c02";
 251                 reg = <0x50>;
 252                 pagesize = <16>;
 253         };
 254
 255         eeprom@51 {
 256                 compatible = "atmel,24c02";
 257                 reg = <0x51>;
 258                 pagesize = <16>;
 259         };
 260
 261         eeprom@52 {
 262                 compatible = "atmel,24c02";
 263                 reg = <0x52>;
 264                 pagesize = <16>;
 265         };
 266
 267         eeprom@53 {
 268                 compatible = "atmel,24c02";
 269                 reg = <0x53>;
 270                 pagesize = <16>;
 271         };
 272
 273         rtc@68 {
 274                 compatible = "dallas,ds1672";
 275                 reg = <0x68>;
 276         };
 277 };
 278
 279 &i2c2 {
 280         clock-frequency = <100000>;
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&pinctrl_i2c2>;
 283         status = "okay";
 284 };
 285
 286 &i2c3 {
 287         clock-frequency = <100000>;
 288         pinctrl-names = "default";
 289         pinctrl-0 = <&pinctrl_i2c3>;
 290         status = "okay";
 291 };
 292
 293 &pcie {
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_pcie>;
 296         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 297         status = "okay";
 298 };
 299
 300 &pwm2 {
 301         pinctrl-names = "default";
 302         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 303         status = "disabled";
 304 };
 305
 306 &pwm3 {
 307         pinctrl-names = "default";
 308         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 309         status = "disabled";
 310 };
 311
 312 &pwm4 {
 313         pinctrl-names = "default";
 314         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 315         status = "disabled";
 316 };
 317
 318 &uart1 {
 319         pinctrl-names = "default";
 320         pinctrl-0 = <&pinctrl_uart1>;
 321         status = "okay";
 322 };
 323
 324 &uart2 {
 325         pinctrl-names = "default";
 326         pinctrl-0 = <&pinctrl_uart2>;
 327         status = "okay";
 328 };
 329
 330 &uart3 {
 331         pinctrl-names = "default";
 332         pinctrl-0 = <&pinctrl_uart3>;
 333         status = "okay";
 334 };
 335
 336 &uart5 {
 337         pinctrl-names = "default";
 338         pinctrl-0 = <&pinctrl_uart5>;
 339         status = "okay";
 340 };
 341
 342 &usbotg {
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_usbotg>;
 345         disable-over-current;
 346         status = "okay";
 347 };
 348
 349 &usbh1 {
 350         status = "okay";
 351 };
 352
 353 &wdog1 {
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&pinctrl_wdog>;
 356         fsl,ext-reset-output;
 357 };
 358
 359 &iomuxc {
 360         pinctrl_enet: enetgrp {
 361                 fsl,pins = <
 362                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 363                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 364                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 365                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 366                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 367                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 368                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 369                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 370                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 371                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 372                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 373                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 374                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 375                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 376                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 377                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 378                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 379                 >;
 380         };
 381
 382         pinctrl_gpio_leds: gpioledsgrp {
 383                 fsl,pins = <
 384                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 385                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 386                 >;
 387         };
 388
 389         pinctrl_gpmi_nand: gpminandgrp {
 390                 fsl,pins = <
 391                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 392                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 393                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 394                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 395                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 396                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 397                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 398                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 399                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 400                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 401                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 402                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 403                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 404                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 405                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 406                 >;
 407         };
 408
 409         pinctrl_i2c1: i2c1grp {
 410                 fsl,pins = <
 411                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 412                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 413                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 414                 >;
 415         };
 416
 417         pinctrl_i2c2: i2c2grp {
 418                 fsl,pins = <
 419                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 420                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 421                 >;
 422         };
 423
 424         pinctrl_i2c3: i2c3grp {
 425                 fsl,pins = <
 426                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 427                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 428                 >;
 429         };
 430
 431         pinctrl_pcie: pciegrp {
 432                 fsl,pins = <
 433                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 434                 >;
 435         };
 436
 437         pinctrl_pps: ppsgrp {
 438                 fsl,pins = <
 439                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b1
 440                 >;
 441         };
 442
 443         pinctrl_pwm2: pwm2grp {
 444                 fsl,pins = <
 445                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 446                 >;
 447         };
 448
 449         pinctrl_pwm3: pwm3grp {
 450                 fsl,pins = <
 451                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 452                 >;
 453         };
 454
 455         pinctrl_pwm4: pwm4grp {
 456                 fsl,pins = <
 457                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 458                 >;
 459         };
 460
 461         pinctrl_uart1: uart1grp {
 462                 fsl,pins = <
 463                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 464                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 465                 >;
 466         };
 467
 468         pinctrl_uart2: uart2grp {
 469                 fsl,pins = <
 470                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 471                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 472                 >;
 473         };
 474
 475         pinctrl_uart3: uart3grp {
 476                 fsl,pins = <
 477                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 478                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 479                 >;
 480         };
 481
 482         pinctrl_uart5: uart5grp {
 483                 fsl,pins = <
 484                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 485                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 486                 >;
 487         };
 488
 489         pinctrl_usbotg: usbotggrp {
 490                 fsl,pins = <
 491                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 492                 >;
 493         };
 494
 495         pinctrl_wdog: wdoggrp {
 496                 fsl,pins = <
 497                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 498                 >;
 499         };
 500 };