arch/arm/boot/dts/imx6qdl-gw5913.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         /* these are used by bootloader for disabling nodes */
  10         aliases {
  11                 led0 = &led0;
  12                 led1 = &led1;
  13                 nand = &gpmi;
  14                 usb0 = &usbh1;
  15                 usb1 = &usbotg;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart2;
  20         };
  21
  22         leds {
  23                 compatible = "gpio-leds";
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&pinctrl_gpio_leds>;
  26
  27                 led0: user1 {
  28                         label = "user1";
  29                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  30                         default-state = "on";
  31                         linux,default-trigger = "heartbeat";
  32                 };
  33
  34                 led1: user2 {
  35                         label = "user2";
  36                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  37                         default-state = "off";
  38                 };
  39         };
  40
  41         memory@10000000 {
  42                 device_type = "memory";
  43                 reg = <0x10000000 0x20000000>;
  44         };
  45
  46         pps {
  47                 compatible = "pps-gpio";
  48                 pinctrl-names = "default";
  49                 pinctrl-0 = <&pinctrl_pps>;
  50                 gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
  51                 status = "okay";
  52         };
  53
  54         reg_3p3v: regulator-3p3v {
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "3P3V";
  57                 regulator-min-microvolt = <3300000>;
  58                 regulator-max-microvolt = <3300000>;
  59                 regulator-always-on;
  60         };
  61
  62         reg_5p0v: regulator-5p0v {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "5P0V";
  65                 regulator-min-microvolt = <5000000>;
  66                 regulator-max-microvolt = <5000000>;
  67                 regulator-always-on;
  68         };
  69 };
  70
  71 &fec {
  72         pinctrl-names = "default";
  73         pinctrl-0 = <&pinctrl_enet>;
  74         phy-mode = "rgmii-id";
  75         status = "okay";
  76 };
  77
  78 &gpmi {
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_gpmi_nand>;
  81         status = "okay";
  82 };
  83
  84 &i2c1 {
  85         clock-frequency = <100000>;
  86         pinctrl-names = "default";
  87         pinctrl-0 = <&pinctrl_i2c1>;
  88         status = "okay";
  89
  90         gpio@23 {
  91                 compatible = "nxp,pca9555";
  92                 reg = <0x23>;
  93                 gpio-controller;
  94                 #gpio-cells = <2>;
  95         };
  96
  97         eeprom@50 {
  98                 compatible = "atmel,24c02";
  99                 reg = <0x50>;
 100                 pagesize = <16>;
 101         };
 102
 103         eeprom@51 {
 104                 compatible = "atmel,24c02";
 105                 reg = <0x51>;
 106                 pagesize = <16>;
 107         };
 108
 109         eeprom@52 {
 110                 compatible = "atmel,24c02";
 111                 reg = <0x52>;
 112                 pagesize = <16>;
 113         };
 114
 115         eeprom@53 {
 116                 compatible = "atmel,24c02";
 117                 reg = <0x53>;
 118                 pagesize = <16>;
 119         };
 120
 121         rtc@68 {
 122                 compatible = "dallas,ds1672";
 123                 reg = <0x68>;
 124         };
 125 };
 126
 127 &i2c2 {
 128         clock-frequency = <100000>;
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_i2c2>;
 131         status = "okay";
 132 };
 133
 134 &i2c3 {
 135         clock-frequency = <100000>;
 136         pinctrl-names = "default";
 137         pinctrl-0 = <&pinctrl_i2c3>;
 138         status = "okay";
 139 };
 140
 141 &pcie {
 142         pinctrl-names = "default";
 143         pinctrl-0 = <&pinctrl_pcie>;
 144         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 145         status = "okay";
 146 };
 147
 148 &pwm2 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 151         status = "disabled";
 152 };
 153
 154 &pwm3 {
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 157         status = "disabled";
 158 };
 159
 160 &pwm4 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 163         status = "disabled";
 164 };
 165
 166 &uart1 {
 167         pinctrl-names = "default";
 168         pinctrl-0 = <&pinctrl_uart1>;
 169         status = "okay";
 170 };
 171
 172 &uart2 {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_uart2>;
 175         status = "okay";
 176 };
 177
 178 &uart3 {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_uart3>;
 181         status = "okay";
 182 };
 183
 184 &uart5 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_uart5>;
 187         status = "okay";
 188 };
 189
 190 &usbotg {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_usbotg>;
 193         disable-over-current;
 194         status = "okay";
 195 };
 196
 197 &usbh1 {
 198         status = "okay";
 199 };
 200
 201 &wdog1 {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_wdog>;
 204         fsl,ext-reset-output;
 205 };
 206
 207 &iomuxc {
 208         pinctrl_enet: enetgrp {
 209                 fsl,pins = <
 210                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 211                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 212                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 213                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 214                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 215                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 216                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 217                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 218                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 219                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 220                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 221                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 222                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 223                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 224                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 225                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 226                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 227                 >;
 228         };
 229
 230         pinctrl_gpio_leds: gpioledsgrp {
 231                 fsl,pins = <
 232                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 233                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 234                 >;
 235         };
 236
 237         pinctrl_gpmi_nand: gpminandgrp {
 238                 fsl,pins = <
 239                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 240                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 241                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 242                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 243                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 244                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 245                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 246                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 247                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 248                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 249                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 250                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 251                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 252                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 253                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 254                 >;
 255         };
 256
 257         pinctrl_i2c1: i2c1grp {
 258                 fsl,pins = <
 259                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 260                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 261                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 262                 >;
 263         };
 264
 265         pinctrl_i2c2: i2c2grp {
 266                 fsl,pins = <
 267                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 268                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 269                 >;
 270         };
 271
 272         pinctrl_i2c3: i2c3grp {
 273                 fsl,pins = <
 274                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 275                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 276                 >;
 277         };
 278
 279         pinctrl_pcie: pciegrp {
 280                 fsl,pins = <
 281                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 282                 >;
 283         };
 284
 285         pinctrl_pps: ppsgrp {
 286                 fsl,pins = <
 287                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x1b0b1
 288                 >;
 289         };
 290
 291         pinctrl_pwm2: pwm2grp {
 292                 fsl,pins = <
 293                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 294                 >;
 295         };
 296
 297         pinctrl_pwm3: pwm3grp {
 298                 fsl,pins = <
 299                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 300                 >;
 301         };
 302
 303         pinctrl_pwm4: pwm4grp {
 304                 fsl,pins = <
 305                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 306                 >;
 307         };
 308
 309         pinctrl_uart1: uart1grp {
 310                 fsl,pins = <
 311                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 312                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 313                 >;
 314         };
 315
 316         pinctrl_uart2: uart2grp {
 317                 fsl,pins = <
 318                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 319                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 320                 >;
 321         };
 322
 323         pinctrl_uart3: uart3grp {
 324                 fsl,pins = <
 325                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 326                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 327                 >;
 328         };
 329
 330         pinctrl_uart5: uart5grp {
 331                 fsl,pins = <
 332                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 333                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 334                 >;
 335         };
 336
 337         pinctrl_usbotg: usbotggrp {
 338                 fsl,pins = <
 339                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 340                 >;
 341         };
 342
 343         pinctrl_wdog: wdoggrp {
 344                 fsl,pins = <
 345                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 346                 >;
 347         };
 348 };