arch/arm/boot/dts/imx6qdl-gw5912.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         /* these are used by bootloader for disabling nodes */
  10         aliases {
  11                 led0 = &led0;
  12                 led1 = &led1;
  13                 led2 = &led2;
  14                 nand = &gpmi;
  15                 usb0 = &usbh1;
  16                 usb1 = &usbotg;
  17         };
  18
  19         chosen {
  20                 stdout-path = &uart2;
  21         };
  22
  23         leds {
  24                 compatible = "gpio-leds";
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinctrl_gpio_leds>;
  27
  28                 led0: user1 {
  29                         label = "user1";
  30                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  31                         default-state = "on";
  32                         linux,default-trigger = "heartbeat";
  33                 };
  34
  35                 led1: user2 {
  36                         label = "user2";
  37                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  38                         default-state = "off";
  39                 };
  40
  41                 led2: user3 {
  42                         label = "user3";
  43                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  44                         default-state = "off";
  45                 };
  46         };
  47
  48         memory@10000000 {
  49                 device_type = "memory";
  50                 reg = <0x10000000 0x40000000>;
  51         };
  52
  53         pps {
  54                 compatible = "pps-gpio";
  55                 pinctrl-names = "default";
  56                 pinctrl-0 = <&pinctrl_pps>;
  57                 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  58         };
  59
  60         reg_3p3v: regulator-3p3v {
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "3P3V";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 regulator-always-on;
  66         };
  67
  68         reg_usb_vbus: regulator-5p0v {
  69                 compatible = "regulator-fixed";
  70                 regulator-name = "usb_vbus";
  71                 regulator-min-microvolt = <5000000>;
  72                 regulator-max-microvolt = <5000000>;
  73                 regulator-always-on;
  74         };
  75 };
  76
  77 &can1 {
  78         pinctrl-names = "default";
  79         pinctrl-0 = <&pinctrl_flexcan1>;
  80         status = "okay";
  81 };
  82
  83 &ecspi2 {
  84         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_ecspi2>;
  87         status = "okay";
  88 };
  89
  90 &fec {
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&pinctrl_enet>;
  93         phy-mode = "rgmii-id";
  94         status = "okay";
  95 };
  96
  97 &gpmi {
  98         pinctrl-names = "default";
  99         pinctrl-0 = <&pinctrl_gpmi_nand>;
 100         status = "okay";
 101 };
 102
 103 &i2c1 {
 104         clock-frequency = <100000>;
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_i2c1>;
 107         status = "okay";
 108
 109         gpio@23 {
 110                 compatible = "nxp,pca9555";
 111                 reg = <0x23>;
 112                 gpio-controller;
 113                 #gpio-cells = <2>;
 114         };
 115
 116         eeprom@50 {
 117                 compatible = "atmel,24c02";
 118                 reg = <0x50>;
 119                 pagesize = <16>;
 120         };
 121
 122         eeprom@51 {
 123                 compatible = "atmel,24c02";
 124                 reg = <0x51>;
 125                 pagesize = <16>;
 126         };
 127
 128         eeprom@52 {
 129                 compatible = "atmel,24c02";
 130                 reg = <0x52>;
 131                 pagesize = <16>;
 132         };
 133
 134         eeprom@53 {
 135                 compatible = "atmel,24c02";
 136                 reg = <0x53>;
 137                 pagesize = <16>;
 138         };
 139
 140         rtc@68 {
 141                 compatible = "dallas,ds1672";
 142                 reg = <0x68>;
 143         };
 144 };
 145
 146 &i2c2 {
 147         clock-frequency = <100000>;
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_i2c2>;
 150         status = "okay";
 151 };
 152
 153 &i2c3 {
 154         clock-frequency = <100000>;
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_i2c3>;
 157         status = "okay";
 158
 159         accel@19 {
 160                 pinctrl-names = "default";
 161                 pinctrl-0 = <&pinctrl_accel>;
 162                 compatible = "st,lis2de12";
 163                 reg = <0x19>;
 164                 st,drdy-int-pin = <1>;
 165                 interrupt-parent = <&gpio7>;
 166                 interrupts = <13 0>;
 167                 interrupt-names = "INT1";
 168         };
 169 };
 170
 171 &pcie {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_pcie>;
 174         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 175         status = "okay";
 176 };
 177
 178 &pwm1 {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
 181         status = "disabled";
 182 };
 183
 184 &pwm2 {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 187         status = "disabled";
 188 };
 189
 190 &pwm3 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 193         status = "disabled";
 194 };
 195
 196 &pwm4 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 199         status = "disabled";
 200 };
 201
 202 &uart1 {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_uart1>;
 205         rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
 206         status = "okay";
 207 };
 208
 209 &uart2 {
 210         pinctrl-names = "default";
 211         pinctrl-0 = <&pinctrl_uart2>;
 212         status = "okay";
 213 };
 214
 215 &uart5 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_uart5>;
 218         status = "okay";
 219 };
 220
 221 &usbotg {
 222         vbus-supply = <&reg_usb_vbus>;
 223         pinctrl-names = "default";
 224         pinctrl-0 = <&pinctrl_usbotg>;
 225         disable-over-current;
 226         dr_mode = "host";
 227         status = "okay";
 228 };
 229
 230 &usbh1 {
 231         vbus-supply = <&reg_usb_vbus>;
 232         status = "okay";
 233 };
 234
 235 &usdhc3 {
 236         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 237         pinctrl-0 = <&pinctrl_usdhc3>;
 238         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 239         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 240         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 241         vmmc-supply = <&reg_3p3v>;
 242         no-1-8-v; /* firmware will remove if board revision supports */
 243         status = "okay";
 244 };
 245
 246 &wdog1 {
 247         status = "disabled";
 248 };
 249
 250 &wdog2 {
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&pinctrl_wdog>;
 253         fsl,ext-reset-output;
 254         status = "okay";
 255 };
 256
 257 &iomuxc {
 258         pinctrl_accel: accelmuxgrp {
 259                 fsl,pins = <
 260                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b1
 261                 >;
 262         };
 263
 264         pinctrl_enet: enetgrp {
 265                 fsl,pins = <
 266                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 267                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 268                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 269                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 270                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 271                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 272                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 273                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 274                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 275                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 276                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 277                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 278                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 279                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 280                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 281                 >;
 282         };
 283
 284         pinctrl_ecspi2: escpi2grp {
 285                 fsl,pins = <
 286                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 287                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 288                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
 289                         MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x100b1
 290                 >;
 291         };
 292
 293         pinctrl_flexcan1: flexcan1grp {
 294                 fsl,pins = <
 295                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 296                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 297                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x4001b0b0
 298                 >;
 299         };
 300
 301         pinctrl_gpio_leds: gpioledsgrp {
 302                 fsl,pins = <
 303                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 304                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 305                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 306                 >;
 307         };
 308
 309         pinctrl_gpmi_nand: gpminandgrp {
 310                 fsl,pins = <
 311                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 312                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 313                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 314                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 315                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 316                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 317                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 318                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 319                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 320                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 321                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 322                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 323                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 324                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 325                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 326                 >;
 327         };
 328
 329         pinctrl_i2c1: i2c1grp {
 330                 fsl,pins = <
 331                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 332                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 333                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 334                 >;
 335         };
 336
 337         pinctrl_i2c2: i2c2grp {
 338                 fsl,pins = <
 339                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 340                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 341                 >;
 342         };
 343
 344         pinctrl_i2c3: i2c3grp {
 345                 fsl,pins = <
 346                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 347                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 348                 >;
 349         };
 350
 351         pinctrl_pcie: pciegrp {
 352                 fsl,pins = <
 353                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0
 354                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0
 355                 >;
 356         };
 357
 358         pinctrl_pps: ppsgrp {
 359                 fsl,pins = <
 360                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b1
 361                 >;
 362         };
 363
 364         pinctrl_pwm1: pwm1grp {
 365                 fsl,pins = <
 366                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 367                 >;
 368         };
 369
 370         pinctrl_pwm2: pwm2grp {
 371                 fsl,pins = <
 372                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 373                 >;
 374         };
 375
 376         pinctrl_pwm3: pwm3grp {
 377                 fsl,pins = <
 378                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 379                 >;
 380         };
 381
 382         pinctrl_pwm4: pwm4grp {
 383                 fsl,pins = <
 384                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
 385                 >;
 386         };
 387
 388         pinctrl_uart1: uart1grp {
 389                 fsl,pins = <
 390                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 391                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 392                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x4001b0b1
 393                 >;
 394         };
 395
 396         pinctrl_uart2: uart2grp {
 397                 fsl,pins = <
 398                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 399                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 400                         MX6QDL_PAD_SD4_DAT3__GPIO2_IO11         0x4001b0b1
 401                 >;
 402         };
 403
 404         pinctrl_uart5: uart5grp {
 405                 fsl,pins = <
 406                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 407                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 408                 >;
 409         };
 410
 411         pinctrl_usbotg: usbotggrp {
 412                 fsl,pins = <
 413                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 414                 >;
 415         };
 416
 417         pinctrl_usdhc3: usdhc3grp {
 418                 fsl,pins = <
 419                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 420                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 421                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 422                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 423                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 424                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 425                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 426                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 427                 >;
 428         };
 429
 430         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 431                 fsl,pins = <
 432                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 433                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 434                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 435                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 436                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 437                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 438                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 439                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 440                 >;
 441         };
 442
 443         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 444                 fsl,pins = <
 445                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 446                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 447                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 448                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 449                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 450                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 451                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 452                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 453                 >;
 454         };
 455
 456         pinctrl_wdog: wdoggrp {
 457                 fsl,pins = <
 458                         MX6QDL_PAD_SD1_DAT3__WDOG2_B            0x1b0b0
 459                 >;
 460         };
 461 };