arch/arm/boot/dts/imx6qdl-gw5910.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9
  10 / {
  11         /* these are used by bootloader for disabling nodes */
  12         aliases {
  13                 led0 = &led0;
  14                 led1 = &led1;
  15                 led2 = &led2;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart2;
  20         };
  21
  22         memory@10000000 {
  23                 device_type = "memory";
  24                 reg = <0x10000000 0x20000000>;
  25         };
  26
  27         gpio-keys {
  28                 compatible = "gpio-keys";
  29
  30                 user-pb {
  31                         label = "user_pb";
  32                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  33                         linux,code = <BTN_0>;
  34                 };
  35
  36                 user-pb1x {
  37                         label = "user_pb1x";
  38                         linux,code = <BTN_1>;
  39                         interrupt-parent = <&gsc>;
  40                         interrupts = <0>;
  41                 };
  42
  43                 key-erased {
  44                         label = "key-erased";
  45                         linux,code = <BTN_2>;
  46                         interrupt-parent = <&gsc>;
  47                         interrupts = <1>;
  48                 };
  49
  50                 eeprom-wp {
  51                         label = "eeprom_wp";
  52                         linux,code = <BTN_3>;
  53                         interrupt-parent = <&gsc>;
  54                         interrupts = <2>;
  55                 };
  56
  57                 tamper {
  58                         label = "tamper";
  59                         linux,code = <BTN_4>;
  60                         interrupt-parent = <&gsc>;
  61                         interrupts = <5>;
  62                 };
  63
  64                 switch-hold {
  65                         label = "switch_hold";
  66                         linux,code = <BTN_5>;
  67                         interrupt-parent = <&gsc>;
  68                         interrupts = <7>;
  69                 };
  70         };
  71
  72         leds {
  73                 compatible = "gpio-leds";
  74                 pinctrl-names = "default";
  75                 pinctrl-0 = <&pinctrl_gpio_leds>;
  76
  77                 led0: user1 {
  78                         label = "user1";
  79                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  80                         default-state = "on";
  81                         linux,default-trigger = "heartbeat";
  82                 };
  83
  84                 led1: user2 {
  85                         label = "user2";
  86                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  87                         default-state = "off";
  88                 };
  89
  90                 led2: user3 {
  91                         label = "user3";
  92                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  93                         default-state = "off";
  94                 };
  95         };
  96
  97         pps {
  98                 compatible = "pps-gpio";
  99                 pinctrl-names = "default";
 100                 pinctrl-0 = <&pinctrl_pps>;
 101                 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 102                 status = "okay";
 103         };
 104
 105         reg_3p3v: regulator-3p3v {
 106                 compatible = "regulator-fixed";
 107                 regulator-name = "3P3V";
 108                 regulator-min-microvolt = <3300000>;
 109                 regulator-max-microvolt = <3300000>;
 110                 regulator-always-on;
 111         };
 112
 113         reg_5p0v: regulator-5p0v {
 114                 compatible = "regulator-fixed";
 115                 regulator-name = "5P0V";
 116                 regulator-min-microvolt = <5000000>;
 117                 regulator-max-microvolt = <5000000>;
 118                 regulator-always-on;
 119         };
 120
 121         reg_wl: regulator-wl {
 122                 pinctrl-names = "default";
 123                 pinctrl-0 = <&pinctrl_reg_wl>;
 124                 compatible = "regulator-fixed";
 125                 regulator-name = "wl";
 126                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 127                 startup-delay-us = <100>;
 128                 enable-active-high;
 129                 regulator-min-microvolt = <3300000>;
 130                 regulator-max-microvolt = <3300000>;
 131         };
 132 };
 133
 134
 135 &ecspi3 {
 136         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
 137         pinctrl-names = "default";
 138         pinctrl-0 = <&pinctrl_ecspi3>;
 139         status = "okay";
 140 };
 141
 142 &fec {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_enet>;
 145         phy-mode = "rgmii-id";
 146         status = "okay";
 147 };
 148
 149 &gpmi {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_gpmi_nand>;
 152         status = "okay";
 153 };
 154
 155 &i2c1 {
 156         clock-frequency = <100000>;
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_i2c1>;
 159         status = "okay";
 160
 161         gsc: gsc@20 {
 162                 compatible = "gw,gsc";
 163                 reg = <0x20>;
 164                 interrupt-parent = <&gpio1>;
 165                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 166                 interrupt-controller;
 167                 #interrupt-cells = <1>;
 168                 #size-cells = <0>;
 169
 170                 adc {
 171                         compatible = "gw,gsc-adc";
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174
 175                         channel@6 {
 176                                 gw,mode = <0>;
 177                                 reg = <0x06>;
 178                                 label = "temp";
 179                         };
 180
 181                         channel@8 {
 182                                 gw,mode = <3>;
 183                                 reg = <0x08>;
 184                                 label = "vdd_bat";
 185                         };
 186
 187                         channel@82 {
 188                                 gw,mode = <2>;
 189                                 reg = <0x82>;
 190                                 label = "vdd_vin";
 191                                 gw,voltage-divider-ohms = <22100 1000>;
 192                                 gw,voltage-offset-microvolt = <800000>;
 193                         };
 194
 195                         channel@84 {
 196                                 gw,mode = <2>;
 197                                 reg = <0x84>;
 198                                 label = "vdd_5p0";
 199                                 gw,voltage-divider-ohms = <22100 10000>;
 200                         };
 201
 202                         channel@86 {
 203                                 gw,mode = <2>;
 204                                 reg = <0x86>;
 205                                 label = "vdd_3p3";
 206                                 gw,voltage-divider-ohms = <10000 10000>;
 207                         };
 208
 209                         channel@88 {
 210                                 gw,mode = <2>;
 211                                 reg = <0x88>;
 212                                 label = "vdd_2p5";
 213                                 gw,voltage-divider-ohms = <10000 10000>;
 214                         };
 215
 216                         channel@8c {
 217                                 gw,mode = <2>;
 218                                 reg = <0x8c>;
 219                                 label = "vdd_3p0";
 220                         };
 221
 222                         channel@8e {
 223                                 gw,mode = <2>;
 224                                 reg = <0x8e>;
 225                                 label = "vdd_arm";
 226                         };
 227
 228                         channel@90 {
 229                                 gw,mode = <2>;
 230                                 reg = <0x90>;
 231                                 label = "vdd_soc";
 232                         };
 233
 234                         channel@92 {
 235                                 gw,mode = <2>;
 236                                 reg = <0x92>;
 237                                 label = "vdd_1p5";
 238                         };
 239
 240                         channel@98 {
 241                                 gw,mode = <2>;
 242                                 reg = <0x98>;
 243                                 label = "vdd_1p8";
 244                         };
 245
 246                         channel@9a {
 247                                 gw,mode = <2>;
 248                                 reg = <0x9a>;
 249                                 label = "vdd_1p0";
 250                                 gw,voltage-divider-ohms = <10000 10000>;
 251                         };
 252
 253                         channel@9c {
 254                                 gw,mode = <2>;
 255                                 reg = <0x9c>;
 256                                 label = "vdd_an1";
 257                                 gw,voltage-divider-ohms = <10000 10000>;
 258                         };
 259
 260                         channel@a2 {
 261                                 gw,mode = <2>;
 262                                 reg = <0xa2>;
 263                                 label = "vdd_gsc";
 264                                 gw,voltage-divider-ohms = <10000 10000>;
 265                         };
 266                 };
 267         };
 268
 269         gsc_gpio: gpio@23 {
 270                 compatible = "nxp,pca9555";
 271                 reg = <0x23>;
 272                 gpio-controller;
 273                 #gpio-cells = <2>;
 274                 interrupt-parent = <&gsc>;
 275                 interrupts = <4>;
 276         };
 277
 278         eeprom@50 {
 279                 compatible = "atmel,24c02";
 280                 reg = <0x50>;
 281                 pagesize = <16>;
 282         };
 283
 284         eeprom@51 {
 285                 compatible = "atmel,24c02";
 286                 reg = <0x51>;
 287                 pagesize = <16>;
 288         };
 289
 290         eeprom@52 {
 291                 compatible = "atmel,24c02";
 292                 reg = <0x52>;
 293                 pagesize = <16>;
 294         };
 295
 296         eeprom@53 {
 297                 compatible = "atmel,24c02";
 298                 reg = <0x53>;
 299                 pagesize = <16>;
 300         };
 301
 302         rtc@68 {
 303                 compatible = "dallas,ds1672";
 304                 reg = <0x68>;
 305         };
 306 };
 307
 308 &i2c2 {
 309         clock-frequency = <100000>;
 310         pinctrl-names = "default";
 311         pinctrl-0 = <&pinctrl_i2c2>;
 312         status = "okay";
 313 };
 314
 315 &i2c3 {
 316         clock-frequency = <100000>;
 317         pinctrl-names = "default";
 318         pinctrl-0 = <&pinctrl_i2c3>;
 319         status = "okay";
 320
 321         accel@19 {
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&pinctrl_accel>;
 324                 compatible = "st,lis2de12";
 325                 reg = <0x19>;
 326                 st,drdy-int-pin = <1>;
 327                 interrupt-parent = <&gpio7>;
 328                 interrupts = <13 0>;
 329                 interrupt-names = "INT1";
 330         };
 331 };
 332
 333 &pcie {
 334         pinctrl-names = "default";
 335         pinctrl-0 = <&pinctrl_pcie>;
 336         reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
 337         status = "okay";
 338 };
 339
 340 &pwm2 {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 343         status = "disabled";
 344 };
 345
 346 &pwm3 {
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 349         status = "disabled";
 350 };
 351
 352 /* off-board RS232 */
 353 &uart1 {
 354         pinctrl-names = "default";
 355         pinctrl-0 = <&pinctrl_uart1>;
 356         status = "okay";
 357 };
 358
 359 /* serial console */
 360 &uart2 {
 361         pinctrl-names = "default";
 362         pinctrl-0 = <&pinctrl_uart2>;
 363         status = "okay";
 364 };
 365
 366 /* cc1352 */
 367 &uart3 {
 368         pinctrl-names = "default";
 369         pinctrl-0 = <&pinctrl_uart3>;
 370         uart-has-rtscts;
 371         status = "okay";
 372 };
 373
 374 /* Sterling-LWB Bluetooth */
 375 &uart4 {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
 378         uart-has-rtscts;
 379         status = "okay";
 380
 381         bluetooth {
 382                 compatible = "brcm,bcm4330-bt";
 383                 shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 384         };
 385 };
 386
 387 /* GPS */
 388 &uart5 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_uart5>;
 391         status = "okay";
 392 };
 393
 394 &usbotg {
 395         vbus-supply = <&reg_5p0v>;
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_usbotg>;
 398         disable-over-current;
 399         status = "okay";
 400 };
 401
 402 &usbh1 {
 403         status = "okay";
 404 };
 405
 406 /* Sterling-LWB SDIO WiFi */
 407 &usdhc2 {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_usdhc2>;
 410         vmmc-supply = <&reg_wl>;
 411         non-removable;
 412         bus-width = <4>;
 413         status = "okay";
 414 };
 415
 416 &usdhc3 {
 417         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 418         pinctrl-0 = <&pinctrl_usdhc3>;
 419         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 420         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 421         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 422         vmmc-supply = <&reg_3p3v>;
 423         status = "okay";
 424 };
 425
 426 &wdog1 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_wdog>;
 429         fsl,ext-reset-output;
 430 };
 431
 432 &iomuxc {
 433         pinctrl_accel: accelmuxgrp {
 434                 fsl,pins = <
 435                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b1
 436                 >;
 437         };
 438
 439         pinctrl_bten: btengrp {
 440                 fsl,pins = <
 441                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b1
 442                 >;
 443         };
 444
 445         pinctrl_ecspi3: escpi3grp {
 446                 fsl,pins = <
 447                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 448                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 449                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 450                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
 451                 >;
 452         };
 453
 454         pinctrl_enet: enetgrp {
 455                 fsl,pins = <
 456                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 457                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 458                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 459                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 460                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 461                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 462                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 463                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 464                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 465                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 466                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 467                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 468                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 469                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 470                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 471                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 472                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 473                 >;
 474         };
 475
 476         pinctrl_gpio_leds: gpioledsgrp {
 477                 fsl,pins = <
 478                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
 479                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
 480                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
 481                 >;
 482         };
 483
 484         pinctrl_gpmi_nand: gpminandgrp {
 485                 fsl,pins = <
 486                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 487                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 488                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 489                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 490                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 491                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 492                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 493                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 494                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 495                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 496                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 497                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 498                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 499                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 500                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 501                 >;
 502         };
 503
 504         pinctrl_i2c1: i2c1grp {
 505                 fsl,pins = <
 506                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 507                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 508                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 509                 >;
 510         };
 511
 512         pinctrl_i2c2: i2c2grp {
 513                 fsl,pins = <
 514                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 515                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 516                 >;
 517         };
 518
 519         pinctrl_i2c3: i2c3grp {
 520                 fsl,pins = <
 521                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 522                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 523                 >;
 524         };
 525
 526         pinctrl_pcie: pciegrp {
 527                 fsl,pins = <
 528                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b0
 529                 >;
 530         };
 531
 532         pinctrl_pps: ppsgrp {
 533                 fsl,pins = <
 534                         MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16     0x1b0b1
 535                 >;
 536         };
 537
 538         pinctrl_pwm2: pwm2grp {
 539                 fsl,pins = <
 540                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 541                 >;
 542         };
 543
 544         pinctrl_pwm3: pwm3grp {
 545                 fsl,pins = <
 546                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 547                 >;
 548         };
 549
 550         pinctrl_reg_wl: regwlgrp {
 551                 fsl,pins = <
 552                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b1
 553                 >;
 554         };
 555
 556         pinctrl_uart1: uart1grp {
 557                 fsl,pins = <
 558                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 559                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 560                 >;
 561         };
 562
 563         pinctrl_uart2: uart2grp {
 564                 fsl,pins = <
 565                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 566                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 567                 >;
 568         };
 569
 570         pinctrl_uart3: uart3grp {
 571                 fsl,pins = <
 572                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 573                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 574                         MX6QDL_PAD_EIM_D23__UART3_RTS_B         0x1b0b1
 575                         MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
 576                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x4001b0b1 /* DIO20 */
 577                         MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05      0x4001b0b1 /* DIO14 */
 578                         MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06      0x4001b0b1 /* DIO15 */
 579                         MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08      0x1b0b1 /* TMS */
 580                         MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x1b0b1 /* TCK */
 581                         MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10      0x1b0b1 /* TDO */
 582                         MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11      0x1b0b1 /* TDI */
 583                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x4001b0b1 /* RST# */
 584                 >;
 585         };
 586
 587         pinctrl_uart4: uart4grp {
 588                 fsl,pins = <
 589                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 590                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 591                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 592                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 593                 >;
 594         };
 595
 596         pinctrl_uart5: uart5grp {
 597                 fsl,pins = <
 598                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 599                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 600                 >;
 601         };
 602
 603         pinctrl_usbotg: usbotggrp {
 604                 fsl,pins = <
 605                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 606                 >;
 607         };
 608
 609         pinctrl_usdhc2: usdhc2grp {
 610                 fsl,pins = <
 611                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 612                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 613                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 614                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 615                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 616                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 617                 >;
 618         };
 619
 620         pinctrl_usdhc3: usdhc3grp {
 621                 fsl,pins = <
 622                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 623                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 624                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 625                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 626                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 627                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 628                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 629                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 630                 >;
 631         };
 632
 633         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 634                 fsl,pins = <
 635                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 636                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
 637                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 638                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 639                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 640                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 641                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 642                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 643                 >;
 644         };
 645
 646         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 647                 fsl,pins = <
 648                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 649                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 650                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 651                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 652                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 653                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 654                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 655                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 656                 >;
 657         };
 658
 659         pinctrl_wdog: wdoggrp {
 660                 fsl,pins = <
 661                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 662                 >;
 663         };
 664 };