arch/arm/boot/dts/imx6qdl-gw5910.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         /* these are used by bootloader for disabling nodes */
  10         aliases {
  11                 led0 = &led0;
  12                 led1 = &led1;
  13                 led2 = &led2;
  14         };
  15
  16         chosen {
  17                 stdout-path = &uart2;
  18         };
  19
  20         memory@10000000 {
  21                 device_type = "memory";
  22                 reg = <0x10000000 0x20000000>;
  23         };
  24
  25         leds {
  26                 compatible = "gpio-leds";
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pinctrl_gpio_leds>;
  29
  30                 led0: user1 {
  31                         label = "user1";
  32                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  33                         default-state = "on";
  34                         linux,default-trigger = "heartbeat";
  35                 };
  36
  37                 led1: user2 {
  38                         label = "user2";
  39                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  40                         default-state = "off";
  41                 };
  42
  43                 led2: user3 {
  44                         label = "user3";
  45                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  46                         default-state = "off";
  47                 };
  48         };
  49
  50         pps {
  51                 compatible = "pps-gpio";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_pps>;
  54                 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
  55                 status = "okay";
  56         };
  57
  58         reg_3p3v: regulator-3p3v {
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "3P3V";
  61                 regulator-min-microvolt = <3300000>;
  62                 regulator-max-microvolt = <3300000>;
  63                 regulator-always-on;
  64         };
  65
  66         reg_5p0v: regulator-5p0v {
  67                 compatible = "regulator-fixed";
  68                 regulator-name = "5P0V";
  69                 regulator-min-microvolt = <5000000>;
  70                 regulator-max-microvolt = <5000000>;
  71                 regulator-always-on;
  72         };
  73
  74         reg_wl: regulator-wl {
  75                 pinctrl-names = "default";
  76                 pinctrl-0 = <&pinctrl_reg_wl>;
  77                 compatible = "regulator-fixed";
  78                 regulator-name = "wl";
  79                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  80                 startup-delay-us = <100>;
  81                 enable-active-high;
  82                 regulator-min-microvolt = <3300000>;
  83                 regulator-max-microvolt = <3300000>;
  84                 regulator-always-on;
  85         };
  86
  87         reg_bt: regulator-bt {
  88                 pinctrl-names = "default";
  89                 pinctrl-0 = <&pinctrl_reg_bt>;
  90                 compatible = "regulator-fixed";
  91                 regulator-name = "bt";
  92                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
  93                 startup-delay-us = <100>;
  94                 enable-active-high;
  95                 regulator-min-microvolt = <3300000>;
  96                 regulator-max-microvolt = <3300000>;
  97                 regulator-always-on;
  98         };
  99 };
 100
 101
 102 &ecspi3 {
 103         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_ecspi3>;
 106         status = "okay";
 107 };
 108
 109 &fec {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_enet>;
 112         phy-mode = "rgmii-id";
 113         status = "okay";
 114 };
 115
 116 &gpmi {
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_gpmi_nand>;
 119         status = "okay";
 120 };
 121
 122 &i2c1 {
 123         clock-frequency = <100000>;
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&pinctrl_i2c1>;
 126         status = "okay";
 127
 128         gpio@23 {
 129                 compatible = "nxp,pca9555";
 130                 reg = <0x23>;
 131                 gpio-controller;
 132                 #gpio-cells = <2>;
 133         };
 134
 135         eeprom@50 {
 136                 compatible = "atmel,24c02";
 137                 reg = <0x50>;
 138                 pagesize = <16>;
 139         };
 140
 141         eeprom@51 {
 142                 compatible = "atmel,24c02";
 143                 reg = <0x51>;
 144                 pagesize = <16>;
 145         };
 146
 147         eeprom@52 {
 148                 compatible = "atmel,24c02";
 149                 reg = <0x52>;
 150                 pagesize = <16>;
 151         };
 152
 153         eeprom@53 {
 154                 compatible = "atmel,24c02";
 155                 reg = <0x53>;
 156                 pagesize = <16>;
 157         };
 158
 159         rtc@68 {
 160                 compatible = "dallas,ds1672";
 161                 reg = <0x68>;
 162         };
 163 };
 164
 165 &i2c2 {
 166         clock-frequency = <100000>;
 167         pinctrl-names = "default";
 168         pinctrl-0 = <&pinctrl_i2c2>;
 169         status = "okay";
 170 };
 171
 172 &i2c3 {
 173         clock-frequency = <100000>;
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_i2c3>;
 176         status = "okay";
 177
 178         accel@19 {
 179                 pinctrl-names = "default";
 180                 pinctrl-0 = <&pinctrl_accel>;
 181                 compatible = "st,lis2de12";
 182                 reg = <0x19>;
 183                 st,drdy-int-pin = <1>;
 184                 interrupt-parent = <&gpio7>;
 185                 interrupts = <13 0>;
 186                 interrupt-names = "INT1";
 187         };
 188 };
 189
 190 &pcie {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_pcie>;
 193         reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
 194         status = "okay";
 195 };
 196
 197 &pwm2 {
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 200         status = "disabled";
 201 };
 202
 203 &pwm3 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 206         status = "disabled";
 207 };
 208
 209 /* off-board RS232 */
 210 &uart1 {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_uart1>;
 213         status = "okay";
 214 };
 215
 216 /* serial console */
 217 &uart2 {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_uart2>;
 220         status = "okay";
 221 };
 222
 223 /* cc1352 */
 224 &uart3 {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_uart3>;
 227         uart-has-rtscts;
 228         status = "okay";
 229 };
 230
 231 /* Sterling-LWB Bluetooth */
 232 &uart4 {
 233         pinctrl-names = "default";
 234         pinctrl-0 = <&pinctrl_uart4>;
 235         uart-has-rtscts;
 236         status = "okay";
 237 };
 238
 239 /* GPS */
 240 &uart5 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_uart5>;
 243         status = "okay";
 244 };
 245
 246 &usbotg {
 247         vbus-supply = <&reg_5p0v>;
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pinctrl_usbotg>;
 250         disable-over-current;
 251         status = "okay";
 252 };
 253
 254 &usbh1 {
 255         status = "okay";
 256 };
 257
 258 /* Sterling-LWB SDIO WiFi */
 259 &usdhc2 {
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&pinctrl_usdhc2>;
 262         vmmc-supply = <&reg_3p3v>;
 263         non-removable;
 264         bus-width = <4>;
 265         status = "okay";
 266 };
 267
 268 &usdhc3 {
 269         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 270         pinctrl-0 = <&pinctrl_usdhc3>;
 271         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 272         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 273         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 274         vmmc-supply = <&reg_3p3v>;
 275         status = "okay";
 276 };
 277
 278 &wdog1 {
 279         pinctrl-names = "default";
 280         pinctrl-0 = <&pinctrl_wdog>;
 281         fsl,ext-reset-output;
 282 };
 283
 284 &iomuxc {
 285         pinctrl_accel: accelmuxgrp {
 286                 fsl,pins = <
 287                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b1
 288                 >;
 289         };
 290
 291         pinctrl_ecspi3: escpi3grp {
 292                 fsl,pins = <
 293                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 294                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 295                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 296                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
 297                 >;
 298         };
 299
 300         pinctrl_enet: enetgrp {
 301                 fsl,pins = <
 302                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 303                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 304                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 305                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 306                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 307                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 308                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 309                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 310                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 311                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 312                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 313                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 314                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 315                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 316                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 317                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 318                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 319                 >;
 320         };
 321
 322         pinctrl_gpio_leds: gpioledsgrp {
 323                 fsl,pins = <
 324                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
 325                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
 326                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
 327                 >;
 328         };
 329
 330         pinctrl_gpmi_nand: gpminandgrp {
 331                 fsl,pins = <
 332                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 333                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 334                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 335                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 336                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 337                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 338                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 339                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 340                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 341                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 342                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 343                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 344                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 345                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 346                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 347                 >;
 348         };
 349
 350         pinctrl_i2c1: i2c1grp {
 351                 fsl,pins = <
 352                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 353                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 354                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 355                 >;
 356         };
 357
 358         pinctrl_i2c2: i2c2grp {
 359                 fsl,pins = <
 360                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 361                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 362                 >;
 363         };
 364
 365         pinctrl_i2c3: i2c3grp {
 366                 fsl,pins = <
 367                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 368                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 369                 >;
 370         };
 371
 372         pinctrl_pcie: pciegrp {
 373                 fsl,pins = <
 374                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b0
 375                 >;
 376         };
 377
 378         pinctrl_pps: ppsgrp {
 379                 fsl,pins = <
 380                         MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16     0x1b0b1
 381                 >;
 382         };
 383
 384         pinctrl_pwm2: pwm2grp {
 385                 fsl,pins = <
 386                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 387                 >;
 388         };
 389
 390         pinctrl_pwm3: pwm3grp {
 391                 fsl,pins = <
 392                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 393                 >;
 394         };
 395
 396         pinctrl_reg_bt: regbtgrp {
 397                 fsl,pins = <
 398                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b1
 399                 >;
 400         };
 401
 402         pinctrl_reg_wl: regwlgrp {
 403                 fsl,pins = <
 404                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b1
 405                 >;
 406         };
 407
 408         pinctrl_uart1: uart1grp {
 409                 fsl,pins = <
 410                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 411                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 412                 >;
 413         };
 414
 415         pinctrl_uart2: uart2grp {
 416                 fsl,pins = <
 417                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 418                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 419                 >;
 420         };
 421
 422         pinctrl_uart3: uart3grp {
 423                 fsl,pins = <
 424                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 425                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 426                         MX6QDL_PAD_EIM_D23__UART3_RTS_B         0x1b0b1
 427                         MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
 428                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x4001b0b1 /* DIO20 */
 429                         MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05      0x4001b0b1 /* DIO14 */
 430                         MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06      0x4001b0b1 /* DIO15 */
 431                         MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08      0x1b0b1 /* TMS */
 432                         MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x1b0b1 /* TCK */
 433                         MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10      0x1b0b1 /* TDO */
 434                         MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11      0x1b0b1 /* TDI */
 435                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x4001b0b1 /* RST# */
 436                 >;
 437         };
 438
 439         pinctrl_uart4: uart4grp {
 440                 fsl,pins = <
 441                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 442                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 443                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 444                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 445                 >;
 446         };
 447
 448         pinctrl_uart5: uart5grp {
 449                 fsl,pins = <
 450                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 451                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 452                 >;
 453         };
 454
 455         pinctrl_usbotg: usbotggrp {
 456                 fsl,pins = <
 457                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 458                 >;
 459         };
 460
 461         pinctrl_usdhc2: usdhc2grp {
 462                 fsl,pins = <
 463                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 464                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 465                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 466                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 467                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 468                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 469                 >;
 470         };
 471
 472         pinctrl_usdhc3: usdhc3grp {
 473                 fsl,pins = <
 474                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 475                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 476                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 477                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 478                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 479                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 480                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 481                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 482                 >;
 483         };
 484
 485         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 486                 fsl,pins = <
 487                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 488                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
 489                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 490                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 491                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 492                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 493                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 494                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 495                 >;
 496         };
 497
 498         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 499                 fsl,pins = <
 500                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 501                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 502                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 503                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 504                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 505                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 506                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 507                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 508                 >;
 509         };
 510
 511         pinctrl_wdog: wdoggrp {
 512                 fsl,pins = <
 513                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 514                 >;
 515         };
 516 };