arch/arm/boot/dts/imx6qdl-gw5910.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8
   9 / {
  10         /* these are used by bootloader for disabling nodes */
  11         aliases {
  12                 led0 = &led0;
  13                 led1 = &led1;
  14                 led2 = &led2;
  15         };
  16
  17         chosen {
  18                 stdout-path = &uart2;
  19         };
  20
  21         memory@10000000 {
  22                 device_type = "memory";
  23                 reg = <0x10000000 0x20000000>;
  24         };
  25
  26         gpio-keys {
  27                 compatible = "gpio-keys";
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 user-pb {
  32                         label = "user_pb";
  33                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  34                         linux,code = <BTN_0>;
  35                 };
  36
  37                 user-pb1x {
  38                         label = "user_pb1x";
  39                         linux,code = <BTN_1>;
  40                         interrupt-parent = <&gsc>;
  41                         interrupts = <0>;
  42                 };
  43
  44                 key-erased {
  45                         label = "key-erased";
  46                         linux,code = <BTN_2>;
  47                         interrupt-parent = <&gsc>;
  48                         interrupts = <1>;
  49                 };
  50
  51                 eeprom-wp {
  52                         label = "eeprom_wp";
  53                         linux,code = <BTN_3>;
  54                         interrupt-parent = <&gsc>;
  55                         interrupts = <2>;
  56                 };
  57
  58                 tamper {
  59                         label = "tamper";
  60                         linux,code = <BTN_4>;
  61                         interrupt-parent = <&gsc>;
  62                         interrupts = <5>;
  63                 };
  64
  65                 switch-hold {
  66                         label = "switch_hold";
  67                         linux,code = <BTN_5>;
  68                         interrupt-parent = <&gsc>;
  69                         interrupts = <7>;
  70                 };
  71         };
  72
  73         leds {
  74                 compatible = "gpio-leds";
  75                 pinctrl-names = "default";
  76                 pinctrl-0 = <&pinctrl_gpio_leds>;
  77
  78                 led0: user1 {
  79                         label = "user1";
  80                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  81                         default-state = "on";
  82                         linux,default-trigger = "heartbeat";
  83                 };
  84
  85                 led1: user2 {
  86                         label = "user2";
  87                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  88                         default-state = "off";
  89                 };
  90
  91                 led2: user3 {
  92                         label = "user3";
  93                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  94                         default-state = "off";
  95                 };
  96         };
  97
  98         pps {
  99                 compatible = "pps-gpio";
 100                 pinctrl-names = "default";
 101                 pinctrl-0 = <&pinctrl_pps>;
 102                 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 103                 status = "okay";
 104         };
 105
 106         reg_3p3v: regulator-3p3v {
 107                 compatible = "regulator-fixed";
 108                 regulator-name = "3P3V";
 109                 regulator-min-microvolt = <3300000>;
 110                 regulator-max-microvolt = <3300000>;
 111                 regulator-always-on;
 112         };
 113
 114         reg_5p0v: regulator-5p0v {
 115                 compatible = "regulator-fixed";
 116                 regulator-name = "5P0V";
 117                 regulator-min-microvolt = <5000000>;
 118                 regulator-max-microvolt = <5000000>;
 119                 regulator-always-on;
 120         };
 121
 122         reg_wl: regulator-wl {
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&pinctrl_reg_wl>;
 125                 compatible = "regulator-fixed";
 126                 regulator-name = "wl";
 127                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 128                 startup-delay-us = <100>;
 129                 enable-active-high;
 130                 regulator-min-microvolt = <3300000>;
 131                 regulator-max-microvolt = <3300000>;
 132         };
 133 };
 134
 135
 136 &ecspi3 {
 137         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_ecspi3>;
 140         status = "okay";
 141 };
 142
 143 &fec {
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pinctrl_enet>;
 146         phy-mode = "rgmii-id";
 147         status = "okay";
 148 };
 149
 150 &gpmi {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_gpmi_nand>;
 153         status = "okay";
 154 };
 155
 156 &i2c1 {
 157         clock-frequency = <100000>;
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_i2c1>;
 160         status = "okay";
 161
 162         gsc: gsc@20 {
 163                 compatible = "gw,gsc";
 164                 reg = <0x20>;
 165                 interrupt-parent = <&gpio1>;
 166                 interrupts = <4 GPIO_ACTIVE_LOW>;
 167                 interrupt-controller;
 168                 #interrupt-cells = <1>;
 169                 #size-cells = <0>;
 170
 171                 adc {
 172                         compatible = "gw,gsc-adc";
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175
 176                         channel@6 {
 177                                 gw,mode = <0>;
 178                                 reg = <0x06>;
 179                                 label = "temp";
 180                         };
 181
 182                         channel@8 {
 183                                 gw,mode = <3>;
 184                                 reg = <0x08>;
 185                                 label = "vdd_bat";
 186                         };
 187
 188                         channel@82 {
 189                                 gw,mode = <2>;
 190                                 reg = <0x82>;
 191                                 label = "vdd_vin";
 192                                 gw,voltage-divider-ohms = <22100 1000>;
 193                                 gw,voltage-offset-microvolt = <800000>;
 194                         };
 195
 196                         channel@84 {
 197                                 gw,mode = <2>;
 198                                 reg = <0x84>;
 199                                 label = "vdd_5p0";
 200                                 gw,voltage-divider-ohms = <22100 10000>;
 201                         };
 202
 203                         channel@86 {
 204                                 gw,mode = <2>;
 205                                 reg = <0x86>;
 206                                 label = "vdd_3p3";
 207                                 gw,voltage-divider-ohms = <10000 10000>;
 208                         };
 209
 210                         channel@88 {
 211                                 gw,mode = <2>;
 212                                 reg = <0x88>;
 213                                 label = "vdd_2p5";
 214                                 gw,voltage-divider-ohms = <10000 10000>;
 215                         };
 216
 217                         channel@8c {
 218                                 gw,mode = <2>;
 219                                 reg = <0x8c>;
 220                                 label = "vdd_3p0";
 221                         };
 222
 223                         channel@8e {
 224                                 gw,mode = <2>;
 225                                 reg = <0x8e>;
 226                                 label = "vdd_arm";
 227                         };
 228
 229                         channel@90 {
 230                                 gw,mode = <2>;
 231                                 reg = <0x90>;
 232                                 label = "vdd_soc";
 233                         };
 234
 235                         channel@92 {
 236                                 gw,mode = <2>;
 237                                 reg = <0x92>;
 238                                 label = "vdd_1p5";
 239                         };
 240
 241                         channel@98 {
 242                                 gw,mode = <2>;
 243                                 reg = <0x98>;
 244                                 label = "vdd_1p8";
 245                         };
 246
 247                         channel@9a {
 248                                 gw,mode = <2>;
 249                                 reg = <0x9a>;
 250                                 label = "vdd_1p0";
 251                                 gw,voltage-divider-ohms = <10000 10000>;
 252                         };
 253
 254                         channel@9c {
 255                                 gw,mode = <2>;
 256                                 reg = <0x9c>;
 257                                 label = "vdd_an1";
 258                                 gw,voltage-divider-ohms = <10000 10000>;
 259                         };
 260
 261                         channel@a2 {
 262                                 gw,mode = <2>;
 263                                 reg = <0xa2>;
 264                                 label = "vdd_gsc";
 265                                 gw,voltage-divider-ohms = <10000 10000>;
 266                         };
 267                 };
 268         };
 269
 270         gsc_gpio: gpio@23 {
 271                 compatible = "nxp,pca9555";
 272                 reg = <0x23>;
 273                 gpio-controller;
 274                 #gpio-cells = <2>;
 275                 interrupt-parent = <&gsc>;
 276                 interrupts = <4>;
 277         };
 278
 279         eeprom@50 {
 280                 compatible = "atmel,24c02";
 281                 reg = <0x50>;
 282                 pagesize = <16>;
 283         };
 284
 285         eeprom@51 {
 286                 compatible = "atmel,24c02";
 287                 reg = <0x51>;
 288                 pagesize = <16>;
 289         };
 290
 291         eeprom@52 {
 292                 compatible = "atmel,24c02";
 293                 reg = <0x52>;
 294                 pagesize = <16>;
 295         };
 296
 297         eeprom@53 {
 298                 compatible = "atmel,24c02";
 299                 reg = <0x53>;
 300                 pagesize = <16>;
 301         };
 302
 303         rtc@68 {
 304                 compatible = "dallas,ds1672";
 305                 reg = <0x68>;
 306         };
 307 };
 308
 309 &i2c2 {
 310         clock-frequency = <100000>;
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&pinctrl_i2c2>;
 313         status = "okay";
 314 };
 315
 316 &i2c3 {
 317         clock-frequency = <100000>;
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&pinctrl_i2c3>;
 320         status = "okay";
 321
 322         accel@19 {
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&pinctrl_accel>;
 325                 compatible = "st,lis2de12";
 326                 reg = <0x19>;
 327                 st,drdy-int-pin = <1>;
 328                 interrupt-parent = <&gpio7>;
 329                 interrupts = <13 0>;
 330                 interrupt-names = "INT1";
 331         };
 332 };
 333
 334 &pcie {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_pcie>;
 337         reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
 338         status = "okay";
 339 };
 340
 341 &pwm2 {
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 344         status = "disabled";
 345 };
 346
 347 &pwm3 {
 348         pinctrl-names = "default";
 349         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 350         status = "disabled";
 351 };
 352
 353 /* off-board RS232 */
 354 &uart1 {
 355         pinctrl-names = "default";
 356         pinctrl-0 = <&pinctrl_uart1>;
 357         status = "okay";
 358 };
 359
 360 /* serial console */
 361 &uart2 {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_uart2>;
 364         status = "okay";
 365 };
 366
 367 /* cc1352 */
 368 &uart3 {
 369         pinctrl-names = "default";
 370         pinctrl-0 = <&pinctrl_uart3>;
 371         uart-has-rtscts;
 372         status = "okay";
 373 };
 374
 375 /* Sterling-LWB Bluetooth */
 376 &uart4 {
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
 379         uart-has-rtscts;
 380         status = "okay";
 381
 382         bluetooth {
 383                 compatible = "brcm,bcm4330-bt";
 384                 shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 385         };
 386 };
 387
 388 /* GPS */
 389 &uart5 {
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_uart5>;
 392         status = "okay";
 393 };
 394
 395 &usbotg {
 396         vbus-supply = <&reg_5p0v>;
 397         pinctrl-names = "default";
 398         pinctrl-0 = <&pinctrl_usbotg>;
 399         disable-over-current;
 400         status = "okay";
 401 };
 402
 403 &usbh1 {
 404         status = "okay";
 405 };
 406
 407 /* Sterling-LWB SDIO WiFi */
 408 &usdhc2 {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&pinctrl_usdhc2>;
 411         vmmc-supply = <&reg_wl>;
 412         non-removable;
 413         bus-width = <4>;
 414         status = "okay";
 415 };
 416
 417 &usdhc3 {
 418         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 419         pinctrl-0 = <&pinctrl_usdhc3>;
 420         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 421         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 422         cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
 423         vmmc-supply = <&reg_3p3v>;
 424         status = "okay";
 425 };
 426
 427 &wdog1 {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_wdog>;
 430         fsl,ext-reset-output;
 431 };
 432
 433 &iomuxc {
 434         pinctrl_accel: accelmuxgrp {
 435                 fsl,pins = <
 436                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x1b0b1
 437                 >;
 438         };
 439
 440         pinctrl_bten: btengrp {
 441                 fsl,pins = <
 442                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b1
 443                 >;
 444         };
 445
 446         pinctrl_ecspi3: escpi3grp {
 447                 fsl,pins = <
 448                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 449                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 450                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 451                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
 452                 >;
 453         };
 454
 455         pinctrl_enet: enetgrp {
 456                 fsl,pins = <
 457                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 458                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 459                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 460                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 461                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 462                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 463                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 464                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 465                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 466                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 467                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 468                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 469                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 470                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 471                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 472                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 473                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 474                 >;
 475         };
 476
 477         pinctrl_gpio_leds: gpioledsgrp {
 478                 fsl,pins = <
 479                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06  0x1b0b0
 480                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07  0x1b0b0
 481                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15  0x1b0b0
 482                 >;
 483         };
 484
 485         pinctrl_gpmi_nand: gpminandgrp {
 486                 fsl,pins = <
 487                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 488                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 489                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 490                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 491                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 492                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 493                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 494                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 495                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 496                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 497                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 498                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 499                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 500                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 501                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 502                 >;
 503         };
 504
 505         pinctrl_i2c1: i2c1grp {
 506                 fsl,pins = <
 507                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 508                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 509                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 510                 >;
 511         };
 512
 513         pinctrl_i2c2: i2c2grp {
 514                 fsl,pins = <
 515                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 516                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 517                 >;
 518         };
 519
 520         pinctrl_i2c3: i2c3grp {
 521                 fsl,pins = <
 522                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 523                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 524                 >;
 525         };
 526
 527         pinctrl_pcie: pciegrp {
 528                 fsl,pins = <
 529                         MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x1b0b0
 530                 >;
 531         };
 532
 533         pinctrl_pps: ppsgrp {
 534                 fsl,pins = <
 535                         MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16     0x1b0b1
 536                 >;
 537         };
 538
 539         pinctrl_pwm2: pwm2grp {
 540                 fsl,pins = <
 541                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 542                 >;
 543         };
 544
 545         pinctrl_pwm3: pwm3grp {
 546                 fsl,pins = <
 547                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 548                 >;
 549         };
 550
 551         pinctrl_reg_wl: regwlgrp {
 552                 fsl,pins = <
 553                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b1
 554                 >;
 555         };
 556
 557         pinctrl_uart1: uart1grp {
 558                 fsl,pins = <
 559                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 560                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 561                 >;
 562         };
 563
 564         pinctrl_uart2: uart2grp {
 565                 fsl,pins = <
 566                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 567                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 568                 >;
 569         };
 570
 571         pinctrl_uart3: uart3grp {
 572                 fsl,pins = <
 573                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 574                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 575                         MX6QDL_PAD_EIM_D23__UART3_RTS_B         0x1b0b1
 576                         MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
 577                         MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x4001b0b1 /* DIO20 */
 578                         MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05      0x4001b0b1 /* DIO14 */
 579                         MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06      0x4001b0b1 /* DIO15 */
 580                         MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08      0x1b0b1 /* TMS */
 581                         MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x1b0b1 /* TCK */
 582                         MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10      0x1b0b1 /* TDO */
 583                         MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11      0x1b0b1 /* TDI */
 584                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x4001b0b1 /* RST# */
 585                 >;
 586         };
 587
 588         pinctrl_uart4: uart4grp {
 589                 fsl,pins = <
 590                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 591                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 592                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 593                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 594                 >;
 595         };
 596
 597         pinctrl_uart5: uart5grp {
 598                 fsl,pins = <
 599                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 600                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 601                 >;
 602         };
 603
 604         pinctrl_usbotg: usbotggrp {
 605                 fsl,pins = <
 606                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 607                 >;
 608         };
 609
 610         pinctrl_usdhc2: usdhc2grp {
 611                 fsl,pins = <
 612                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 613                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 614                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 615                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 616                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 617                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 618                 >;
 619         };
 620
 621         pinctrl_usdhc3: usdhc3grp {
 622                 fsl,pins = <
 623                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 624                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 625                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 626                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 627                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 628                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 629                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x17059 /* CD */
 630                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x17059
 631                 >;
 632         };
 633
 634         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 635                 fsl,pins = <
 636                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 637                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x170b9
 638                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 639                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 640                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 641                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 642                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170b9 /* CD */
 643                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170b9
 644                 >;
 645         };
 646
 647         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 648                 fsl,pins = <
 649                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 650                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 651                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 652                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 653                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 654                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 655                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x170f9 /* CD */
 656                         MX6QDL_PAD_NANDF_CS1__SD3_VSELECT       0x170f9
 657                 >;
 658         };
 659
 660         pinctrl_wdog: wdoggrp {
 661                 fsl,pins = <
 662                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 663                 >;
 664         };
 665 };