arch/arm/boot/dts/imx6qdl-gw5903.dtsi

   1 /*
   2  * Copyright 2017 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/input/linux-event-codes.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51
  52 / {
  53         chosen {
  54                 stdout-path = &uart2;
  55         };
  56
  57         backlight {
  58                 compatible = "pwm-backlight";
  59                 pwms = <&pwm1 0 5000000>;
  60                 brightness-levels = <
  61                         0  1  2  3  4  5  6  7  8  9
  62                         10 11 12 13 14 15 16 17 18 19
  63                         20 21 22 23 24 25 26 27 28 29
  64                         30 31 32 33 34 35 36 37 38 39
  65                         40 41 42 43 44 45 46 47 48 49
  66                         50 51 52 53 54 55 56 57 58 59
  67                         60 61 62 63 64 65 66 67 68 69
  68                         70 71 72 73 74 75 76 77 78 79
  69                         80 81 82 83 84 85 86 87 88 89
  70                         90 91 92 93 94 95 96 97 98 99
  71                         100
  72                         >;
  73                 default-brightness-level = <100>;
  74         };
  75
  76         gpio-keys {
  77                 compatible = "gpio-keys";
  78
  79                 user-pb {
  80                         label = "user_pb";
  81                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  82                         linux,code = <BTN_0>;
  83                 };
  84
  85                 user-pb1x {
  86                         label = "user_pb1x";
  87                         linux,code = <BTN_1>;
  88                         interrupt-parent = <&gsc>;
  89                         interrupts = <0>;
  90                 };
  91
  92                 key-erased {
  93                         label = "key-erased";
  94                         linux,code = <BTN_2>;
  95                         interrupt-parent = <&gsc>;
  96                         interrupts = <1>;
  97                 };
  98
  99                 eeprom-wp {
 100                         label = "eeprom_wp";
 101                         linux,code = <BTN_3>;
 102                         interrupt-parent = <&gsc>;
 103                         interrupts = <2>;
 104                 };
 105
 106                 tamper {
 107                         label = "tamper";
 108                         linux,code = <BTN_4>;
 109                         interrupt-parent = <&gsc>;
 110                         interrupts = <5>;
 111                 };
 112
 113                 switch-hold {
 114                         label = "switch_hold";
 115                         linux,code = <BTN_5>;
 116                         interrupt-parent = <&gsc>;
 117                         interrupts = <7>;
 118                 };
 119         };
 120
 121         leds {
 122                 compatible = "gpio-leds";
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&pinctrl_gpio_leds>;
 125
 126                 led0: user1 {
 127                         label = "user1";
 128                         gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
 129                         default-state = "off";
 130                 };
 131         };
 132
 133         memory@10000000 {
 134                 device_type = "memory";
 135                 reg = <0x10000000 0x40000000>;
 136         };
 137
 138         reg_5p0v: regulator-5p0v {
 139                 compatible = "regulator-fixed";
 140                 regulator-name = "5P0V";
 141                 regulator-min-microvolt = <5000000>;
 142                 regulator-max-microvolt = <5000000>;
 143                 regulator-always-on;
 144         };
 145
 146         reg_3p3v: regulator-3p3v {
 147                 compatible = "regulator-fixed";
 148                 regulator-name = "3P3V";
 149                 regulator-min-microvolt = <3300000>;
 150                 regulator-max-microvolt = <3300000>;
 151                 regulator-always-on;
 152         };
 153
 154         reg_2p5v: regulator-2p5v {
 155                 compatible = "regulator-fixed";
 156                 regulator-name = "2P5V";
 157                 regulator-min-microvolt = <2500000>;
 158                 regulator-max-microvolt = <2500000>;
 159                 regulator-always-on;
 160         };
 161
 162         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 163                 compatible = "regulator-fixed";
 164                 regulator-name = "usb_h1_vbus";
 165                 regulator-min-microvolt = <5000000>;
 166                 regulator-max-microvolt = <5000000>;
 167                 gpio = <&gpio3 30 0>;
 168                 enable-active-high;
 169         };
 170
 171         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 172                 compatible = "regulator-fixed";
 173                 regulator-name = "usb_otg_vbus";
 174                 regulator-min-microvolt = <5000000>;
 175                 regulator-max-microvolt = <5000000>;
 176                 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
 177                 enable-active-high;
 178         };
 179
 180         reg_12p0: regulator-12p0v {
 181                 compatible = "regulator-fixed";
 182                 regulator-name = "12P0V";
 183                 regulator-min-microvolt = <12000000>;
 184                 regulator-max-microvolt = <12000000>;
 185                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 186                 enable-active-high;
 187         };
 188
 189         sound {
 190                 compatible = "fsl,imx-audio-tlv320";
 191                 model = "imx-tlv320";
 192                 ssi-controller = <&ssi1>;
 193                 audio-codec = <&tlv320aic3105>;
 194                 /* routing of sink, source */
 195                 audio-routing =
 196                         /* TLV320 LINE1L pin <-> Mic Jack connector */
 197                         "LINE1L", "Mic Jack",
 198                         /* board Headphone Jack <-> HPOUT */
 199                         "Headphone Jack", "HPLOUT",
 200                         "Headphone Jack", "HPROUT",
 201                         "Mic Jack", "Mic Bias";
 202                 mux-int-port = <1>;
 203                 mux-ext-port = <6>;
 204         };
 205 };
 206
 207 &audmux {
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&pinctrl_audmux>;
 210         status = "okay";
 211 };
 212
 213 &clks {
 214         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 215                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 216         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 217                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 218 };
 219
 220 &fec {
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_enet>;
 223         phy-mode = "rgmii-id";
 224         status = "okay";
 225 };
 226
 227 &i2c1 {
 228         clock-frequency = <100000>;
 229         pinctrl-names = "default";
 230         pinctrl-0 = <&pinctrl_i2c1>;
 231         status = "okay";
 232
 233         gsc: gsc@20 {
 234                 compatible = "gw,gsc";
 235                 reg = <0x20>;
 236                 interrupt-parent = <&gpio1>;
 237                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 238                 interrupt-controller;
 239                 #interrupt-cells = <1>;
 240                 #size-cells = <0>;
 241
 242                 adc {
 243                         compatible = "gw,gsc-adc";
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246
 247                         channel@0 {
 248                                 gw,mode = <0>;
 249                                 reg = <0x00>;
 250                                 label = "temp";
 251                         };
 252
 253                         channel@2 {
 254                                 gw,mode = <1>;
 255                                 reg = <0x02>;
 256                                 label = "vdd_vin";
 257                         };
 258
 259                         channel@5 {
 260                                 gw,mode = <1>;
 261                                 reg = <0x05>;
 262                                 label = "vdd_3p3";
 263                         };
 264
 265                         channel@8 {
 266                                 gw,mode = <1>;
 267                                 reg = <0x08>;
 268                                 label = "vdd_bat";
 269                         };
 270
 271                         channel@b {
 272                                 gw,mode = <1>;
 273                                 reg = <0x0b>;
 274                                 label = "vdd_5p0";
 275                         };
 276
 277                         channel@e {
 278                                 gw,mode = <1>;
 279                                 reg = <0xe>;
 280                                 label = "vdd_arm";
 281                         };
 282
 283                         channel@11 {
 284                                 gw,mode = <1>;
 285                                 reg = <0x11>;
 286                                 label = "vdd_soc";
 287                         };
 288
 289                         channel@14 {
 290                                 gw,mode = <1>;
 291                                 reg = <0x14>;
 292                                 label = "vdd_3p0";
 293                         };
 294
 295                         channel@17 {
 296                                 gw,mode = <1>;
 297                                 reg = <0x17>;
 298                                 label = "vdd_1p5";
 299                         };
 300
 301                         channel@1d {
 302                                 gw,mode = <1>;
 303                                 reg = <0x1d>;
 304                                 label = "vdd_1p8";
 305                         };
 306
 307                         channel@20 {
 308                                 gw,mode = <1>;
 309                                 reg = <0x20>;
 310                                 label = "vdd_an1";
 311                         };
 312
 313                         channel@23 {
 314                                 gw,mode = <1>;
 315                                 reg = <0x23>;
 316                                 label = "vdd_2p5";
 317                         };
 318                 };
 319         };
 320
 321         gsc_gpio: gpio@23 {
 322                 compatible = "nxp,pca9555";
 323                 reg = <0x23>;
 324                 gpio-controller;
 325                 #gpio-cells = <2>;
 326                 interrupt-parent = <&gsc>;
 327                 interrupts = <4>;
 328         };
 329
 330         eeprom1: eeprom@50 {
 331                 compatible = "atmel,24c02";
 332                 reg = <0x50>;
 333                 pagesize = <16>;
 334         };
 335
 336         eeprom2: eeprom@51 {
 337                 compatible = "atmel,24c02";
 338                 reg = <0x51>;
 339                 pagesize = <16>;
 340         };
 341
 342         eeprom3: eeprom@52 {
 343                 compatible = "atmel,24c02";
 344                 reg = <0x52>;
 345                 pagesize = <16>;
 346         };
 347
 348         eeprom4: eeprom@53 {
 349                 compatible = "atmel,24c02";
 350                 reg = <0x53>;
 351                 pagesize = <16>;
 352         };
 353
 354         dts1672: rtc@68 {
 355                 compatible = "dallas,ds1672";
 356                 reg = <0x68>;
 357         };
 358 };
 359
 360 &i2c2 {
 361         clock-frequency = <400000>;
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_i2c2>;
 364         status = "okay";
 365
 366         ltc3676: pmic@3c {
 367                 compatible = "lltc,ltc3676";
 368                 reg = <0x3c>;
 369                 interrupt-parent = <&gpio1>;
 370                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 371
 372                 regulators {
 373                         /* VDD_1P8 (1+R1/R2 = 2.505): Aud/eMMC/microSD/Touch */
 374                         reg_1p8v: sw1 {
 375                                 regulator-name = "vdd1p8";
 376                                 regulator-min-microvolt = <1033310>;
 377                                 regulator-max-microvolt = <2004000>;
 378                                 lltc,fb-voltage-divider = <301000 200000>;
 379                                 regulator-ramp-delay = <7000>;
 380                                 regulator-boot-on;
 381                                 regulator-always-on;
 382                         };
 383
 384                         /* VDD_DDR (1+R1/R2 = 2.105) */
 385                         reg_vdd_ddr: sw2 {
 386                                 regulator-name = "vddddr";
 387                                 regulator-min-microvolt = <868310>;
 388                                 regulator-max-microvolt = <1684000>;
 389                                 lltc,fb-voltage-divider = <221000 200000>;
 390                                 regulator-ramp-delay = <7000>;
 391                                 regulator-boot-on;
 392                                 regulator-always-on;
 393                         };
 394
 395                         /* VDD_ARM (1+R1/R2 = 1.635) */
 396                         reg_vdd_arm: sw3 {
 397                                 regulator-name = "vddarm";
 398                                 regulator-min-microvolt = <674400>;
 399                                 regulator-max-microvolt = <1308000>;
 400                                 lltc,fb-voltage-divider = <127000 200000>;
 401                                 regulator-ramp-delay = <7000>;
 402                                 regulator-boot-on;
 403                                 regulator-always-on;
 404                                 linux,phandle = <&reg_vdd_arm>;
 405                         };
 406
 407                         /* VDD_SOC (1+R1/R2 = 1.635) */
 408                         reg_vdd_soc: sw4 {
 409                                 regulator-name = "vddsoc";
 410                                 regulator-min-microvolt = <674400>;
 411                                 regulator-max-microvolt = <1308000>;
 412                                 lltc,fb-voltage-divider = <127000 200000>;
 413                                 regulator-ramp-delay = <7000>;
 414                                 regulator-boot-on;
 415                                 regulator-always-on;
 416                                 linux,phandle = <&reg_vdd_soc>;
 417                         };
 418
 419                         /* VDD_1P0 (1+R1/R2 = 1.38): */
 420                         reg_1p0v: ldo2 {
 421                                 regulator-name = "vdd1p0";
 422                                 regulator-min-microvolt = <1002777>;
 423                                 regulator-max-microvolt = <1002777>;
 424                                 lltc,fb-voltage-divider = <100000 261000>;
 425                                 regulator-boot-on;
 426                                 regulator-always-on;
 427                         };
 428
 429                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 430                         reg_3p0v: ldo4 {
 431                                 regulator-name = "vdd3p0";
 432                                 regulator-min-microvolt = <3023250>;
 433                                 regulator-max-microvolt = <3023250>;
 434                                 lltc,fb-voltage-divider = <634000 200000>;
 435                                 regulator-boot-on;
 436                                 regulator-always-on;
 437                         };
 438                 };
 439         };
 440 };
 441
 442 &i2c3 {
 443         clock-frequency = <400000>;
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&pinctrl_i2c3>;
 446         status = "okay";
 447
 448         tlv320aic3105: codec@18 {
 449                 compatible = "ti,tlv320aic3x";
 450                 reg = <0x18>;
 451                 reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
 452                 clocks = <&clks IMX6QDL_CLK_CKO>;
 453                 ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
 454                 /* Regulators */
 455                 DRVDD-supply = <&reg_3p3v>;
 456                 AVDD-supply = <&reg_3p3v>;
 457                 IOVDD-supply = <&reg_3p3v>;
 458                 DVDD-supply = <&reg_1p8v>;
 459         };
 460
 461         accelerometer@1d {
 462                 compatible = "fsl,mma8451";
 463                 reg = <0x1d>;
 464                 interrupt-parent = <&gpio7>;
 465                 interrupts = <11 IRQ_TYPE_EDGE_RISING>;
 466                 interrupt-names = "INT2";
 467         };
 468
 469         /* headphone detect */
 470         ts3a227e@3b {
 471                 compatible = "ti,ts3a227e";
 472                 reg = <0x3b>;
 473                 interrupt-parent = <&gpio5>;
 474                 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 475                 ti,micbias = <4>; /* 2.5V micbias */
 476         };
 477 };
 478
 479 &ldb {
 480         status = "okay";
 481
 482         lvds-channel@0 {
 483                 fsl,data-mapping = "spwg";
 484                 fsl,data-width = <18>;
 485                 status = "okay";
 486
 487                 display-timings {
 488                         native-mode = <&timing0>;
 489                         timing0: g101evn010 {
 490                                 clock-frequency = <68930000>;
 491                                 hactive = <1280>;
 492                                 vactive = <800>;
 493                                 hback-porch = <220>;
 494                                 hfront-porch = <40>;
 495                                 vback-porch = <21>;
 496                                 vfront-porch = <7>;
 497                                 hsync-len = <60>;
 498                                 vsync-len = <10>;
 499                         };
 500                 };
 501         };
 502 };
 503
 504 &pwm1 {
 505         #pwm-cells = <2>;
 506         pinctrl-names = "default";
 507         pinctrl-0 = <&pinctrl_pwm1>;
 508         status = "okay";
 509 };
 510
 511 &ssi1 {
 512         status = "okay";
 513 };
 514
 515 &uart1 {
 516         pinctrl-names = "default";
 517         pinctrl-0 = <&pinctrl_uart1>;
 518         status = "okay";
 519 };
 520
 521 &uart2 {
 522         pinctrl-names = "default";
 523         pinctrl-0 = <&pinctrl_uart2>;
 524         status = "okay";
 525 };
 526
 527 &usbotg {
 528         vbus-supply = <&reg_usb_otg_vbus>;
 529         pinctrl-names = "default";
 530         pinctrl-0 = <&pinctrl_usbotg>;
 531         disable-over-current;
 532         status = "okay";
 533 };
 534
 535 &usbh1 {
 536         vbus-supply = <&reg_usb_h1_vbus>;
 537         status = "okay";
 538 };
 539
 540 &usdhc1 {
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&pinctrl_usdhc1_200mhz>;
 543         vmmc-supply = <&reg_3p3v>;
 544         non-removable;
 545         bus-width = <4>;
 546         status = "okay";
 547 };
 548
 549 &usdhc2 {
 550         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 551         pinctrl-0 = <&pinctrl_usdhc2>;
 552         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 553         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 554         cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 555         vmmc-supply = <&reg_3p3v>;
 556         max-frequency = <100000000>;
 557         status = "okay";
 558 };
 559
 560 &usdhc3 {
 561         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 562         pinctrl-0 = <&pinctrl_usdhc3>;
 563         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 564         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 565         non-removable;
 566         vmmc-supply = <&reg_3p3v>;
 567         keep-power-in-suspend;
 568         status = "okay";
 569 };
 570
 571 &wdog1 {
 572         pinctrl-names = "default";
 573         pinctrl-0 = <&pinctrl_wdog>;
 574         fsl,ext-reset-output;
 575 };
 576
 577 &iomuxc {
 578         pinctrl_audmux: audmuxgrp {
 579                 fsl,pins = <
 580                         MX6QDL_PAD_DI0_PIN2__AUD6_TXD           0x130b0
 581                         MX6QDL_PAD_DI0_PIN3__AUD6_TXFS          0x130b0
 582                         MX6QDL_PAD_DI0_PIN4__AUD6_RXD           0x130b0
 583                         MX6QDL_PAD_DI0_PIN15__AUD6_TXC          0x130b0
 584                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0 /* MCK */
 585                 >;
 586         };
 587
 588         pinctrl_enet: enetgrp {
 589                 fsl,pins = <
 590                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 591                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 592                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 593                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 594                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 595                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 596                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 597                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 598                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 599                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 600                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 601                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 602                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 603                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 604                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 605                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
 606                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x4001b0b0 /* PHY_EN */
 607                 >;
 608         };
 609
 610         pinctrl_gpio_leds: gpioledsgrp {
 611                 fsl,pins = <
 612                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x1b0b0
 613                 >;
 614         };
 615
 616         pinctrl_i2c1: i2c1grp {
 617                 fsl,pins = <
 618                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 619                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 620                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0 /* GSC_IRQ# */
 621                 >;
 622         };
 623
 624         pinctrl_i2c2: i2c2grp {
 625                 fsl,pins = <
 626                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 627                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 628                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 629                 >;
 630         };
 631
 632         pinctrl_i2c3: i2c3grp {
 633                 fsl,pins = <
 634                         /* I2C3 */
 635                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 636                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 637
 638                         /* Headphone Detect */
 639                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x0001b0b0 /* HPDET_IRQ# */
 640                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x0001b0b0 /* HPDET_MIC# */
 641
 642                         /* Codec */
 643                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x0001b0b0 /* CODEC_RST# */
 644
 645                         /* Touch Controller */
 646                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x0001b0b0 /* TOUCH_IRQ# */
 647                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x0001b0b0 /* TOUCH_RST */
 648
 649                         /* Stow Sensor */
 650                         MX6QDL_PAD_GPIO_16__GPIO7_IO11          0x0001b0b0 /* ACCEL_IRQ2 */
 651                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x0001b0b0 /* ACCEL_IRQ1 */
 652                 >;
 653         };
 654
 655         pinctrl_pwm1: pwm1grp {
 656                 fsl,pins = <
 657                         MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
 658                 >;
 659         };
 660
 661         pinctrl_uart1: uart1grp {
 662                 fsl,pins = <
 663                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 664                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 665                         MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30       0x1b0b1 /* TXEN */
 666                 >;
 667         };
 668
 669         pinctrl_uart2: uart2grp {
 670                 fsl,pins = <
 671                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 672                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 673                 >;
 674         };
 675
 676         pinctrl_usbotg: usbotggrp {
 677                 fsl,pins = <
 678                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
 679                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x4001b0b0 /* PWR_EN */
 680                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 681                 >;
 682         };
 683
 684         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 685                 fsl,pins = <
 686                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x4001b0b0 /* EMMY_EN */
 687                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x4001b0b0 /* EMMY_CFG1# */
 688                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05         0x4001b0b0 /* EMMY_CFG2# */
 689                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06         0x0001b0b0 /* EMMY_BTWAKE# */
 690                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07         0x0001b0b0 /* EMMY_WFWAKE# */
 691
 692                         MX6QDL_PAD_SD1_CLK__SD1_CLK             0x100f9
 693                         MX6QDL_PAD_SD1_CMD__SD1_CMD             0x100f9
 694                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x170f9
 695                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x170f9
 696                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x170f9
 697                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x170f9
 698                 >;
 699         };
 700
 701         pinctrl_usdhc2: usdhc2grp {
 702                 fsl,pins = <
 703                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 704                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 705                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 706                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 707                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 708                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 709                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x17059 /* CD */
 710                         MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x17059
 711                 >;
 712         };
 713
 714         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 715                 fsl,pins = <
 716                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
 717                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
 718                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
 719                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
 720                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
 721                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
 722                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x170b9 /* CD */
 723                         MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x170b9
 724                 >;
 725         };
 726
 727         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 728                 fsl,pins = <
 729                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
 730                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
 731                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
 732                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
 733                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
 734                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
 735                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x170f9 /* CD */
 736                         MX6QDL_PAD_KEY_ROW1__SD2_VSELECT        0x170f9
 737                 >;
 738         };
 739
 740         pinctrl_usdhc3: usdhc3grp {
 741                 fsl,pins = <
 742                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 743                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 744                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
 745                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 746                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 747                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 748                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 749                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 750                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 751                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 752                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 753                 >;
 754         };
 755
 756         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 757                 fsl,pins = <
 758                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 759                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 760                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
 761                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 762                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 763                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 764                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 765                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 766                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 767                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 768                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 769                 >;
 770         };
 771
 772         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 773                 fsl,pins = <
 774                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 775                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 776                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
 777                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 778                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 779                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 780                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 781                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 782                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 783                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 784                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 785                 >;
 786         };
 787
 788         pinctrl_wdog: wdoggrp {
 789                 fsl,pins = <
 790                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 791                 >;
 792         };
 793 };