arch/arm/boot/dts/imx6qdl-gw551x.dtsi

   1 /*
   2  * Copyright 2014 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/media/tda1997x.h>
  50 #include <dt-bindings/sound/fsl-imx-audmux.h>
  51
  52 / {
  53         /* these are used by bootloader for disabling nodes */
  54         aliases {
  55                 led0 = &led0;
  56                 nand = &gpmi;
  57                 ssi0 = &ssi1;
  58                 usb0 = &usbh1;
  59                 usb1 = &usbotg;
  60         };
  61
  62         chosen {
  63                 bootargs = "console=ttymxc1,115200";
  64         };
  65
  66         leds {
  67                 compatible = "gpio-leds";
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&pinctrl_gpio_leds>;
  70
  71                 led0: user1 {
  72                         label = "user1";
  73                         gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
  74                         default-state = "on";
  75                         linux,default-trigger = "heartbeat";
  76                 };
  77         };
  78
  79         memory@10000000 {
  80                 device_type = "memory";
  81                 reg = <0x10000000 0x20000000>;
  82         };
  83
  84         reg_5p0v: regulator-5p0v {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "5P0V";
  87                 regulator-min-microvolt = <5000000>;
  88                 regulator-max-microvolt = <5000000>;
  89         };
  90
  91         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "usb_h1_vbus";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96         };
  97
  98         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  99                 compatible = "regulator-fixed";
 100                 regulator-name = "usb_otg_vbus";
 101                 regulator-min-microvolt = <5000000>;
 102                 regulator-max-microvolt = <5000000>;
 103         };
 104
 105         sound-digital {
 106                 compatible = "simple-audio-card";
 107                 simple-audio-card,name = "tda1997x-audio";
 108                 simple-audio-card,format = "i2s";
 109                 simple-audio-card,bitclock-master = <&sound_codec>;
 110                 simple-audio-card,frame-master = <&sound_codec>;
 111
 112                 sound_cpu: simple-audio-card,cpu {
 113                         sound-dai = <&ssi2>;
 114                 };
 115
 116                 sound_codec: simple-audio-card,codec {
 117                         sound-dai = <&hdmi_receiver>;
 118                 };
 119         };
 120 };
 121
 122 &audmux {
 123         pinctrl-names = "default";
 124         pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
 125         status = "okay";
 126
 127         ssi1 {
 128                 fsl,audmux-port = <0>;
 129                 fsl,port-config = <
 130                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 131                         IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
 132                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 133                         IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
 134                         IMX_AUDMUX_V2_PTCR_SYN)
 135                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 136                 >;
 137         };
 138
 139         aud5 {
 140                 fsl,audmux-port = <4>;
 141                 fsl,port-config = <
 142                         IMX_AUDMUX_V2_PTCR_SYN
 143                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
 144         };
 145 };
 146
 147 &can1 {
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_flexcan1>;
 150         status = "okay";
 151 };
 152
 153 &gpmi {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_gpmi_nand>;
 156         status = "okay";
 157 };
 158
 159 &hdmi {
 160         ddc-i2c-bus = <&i2c3>;
 161         status = "okay";
 162 };
 163
 164 &i2c1 {
 165         clock-frequency = <100000>;
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_i2c1>;
 168         status = "okay";
 169
 170         eeprom1: eeprom@50 {
 171                 compatible = "atmel,24c02";
 172                 reg = <0x50>;
 173                 pagesize = <16>;
 174         };
 175
 176         eeprom2: eeprom@51 {
 177                 compatible = "atmel,24c02";
 178                 reg = <0x51>;
 179                 pagesize = <16>;
 180         };
 181
 182         eeprom3: eeprom@52 {
 183                 compatible = "atmel,24c02";
 184                 reg = <0x52>;
 185                 pagesize = <16>;
 186         };
 187
 188         eeprom4: eeprom@53 {
 189                 compatible = "atmel,24c02";
 190                 reg = <0x53>;
 191                 pagesize = <16>;
 192         };
 193
 194         gpio: pca9555@23 {
 195                 compatible = "nxp,pca9555";
 196                 reg = <0x23>;
 197                 gpio-controller;
 198                 #gpio-cells = <2>;
 199         };
 200
 201         rtc: ds1672@68 {
 202                 compatible = "dallas,ds1672";
 203                 reg = <0x68>;
 204         };
 205 };
 206
 207 &i2c2 {
 208         clock-frequency = <100000>;
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&pinctrl_i2c2>;
 211         status = "okay";
 212
 213         ltc3676: pmic@3c {
 214                 compatible = "lltc,ltc3676";
 215                 reg = <0x3c>;
 216                 pinctrl-names = "default";
 217                 pinctrl-0 = <&pinctrl_pmic>;
 218                 interrupt-parent = <&gpio1>;
 219                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 220
 221                 regulators {
 222                         /* VDD_SOC (1+R1/R2 = 1.635) */
 223                         reg_vdd_soc: sw1 {
 224                                 regulator-name = "vddsoc";
 225                                 regulator-min-microvolt = <674400>;
 226                                 regulator-max-microvolt = <1308000>;
 227                                 lltc,fb-voltage-divider = <127000 200000>;
 228                                 regulator-ramp-delay = <7000>;
 229                                 regulator-boot-on;
 230                                 regulator-always-on;
 231                         };
 232
 233                         /* VDD_DDR (1+R1/R2 = 2.105) */
 234                         reg_vdd_ddr: sw2 {
 235                                 regulator-name = "vddddr";
 236                                 regulator-min-microvolt = <868310>;
 237                                 regulator-max-microvolt = <1684000>;
 238                                 lltc,fb-voltage-divider = <221000 200000>;
 239                                 regulator-ramp-delay = <7000>;
 240                                 regulator-boot-on;
 241                                 regulator-always-on;
 242                         };
 243
 244                         /* VDD_ARM (1+R1/R2 = 1.635) */
 245                         reg_vdd_arm: sw3 {
 246                                 regulator-name = "vddarm";
 247                                 regulator-min-microvolt = <674400>;
 248                                 regulator-max-microvolt = <1308000>;
 249                                 lltc,fb-voltage-divider = <127000 200000>;
 250                                 regulator-ramp-delay = <7000>;
 251                                 regulator-boot-on;
 252                                 regulator-always-on;
 253                         };
 254
 255                         /* VDD_3P3 (1+R1/R2 = 1.281) */
 256                         reg_3p3: sw4 {
 257                                 regulator-name = "vdd3p3";
 258                                 regulator-min-microvolt = <1880000>;
 259                                 regulator-max-microvolt = <3647000>;
 260                                 lltc,fb-voltage-divider = <200000 56200>;
 261                                 regulator-ramp-delay = <7000>;
 262                                 regulator-boot-on;
 263                                 regulator-always-on;
 264                         };
 265
 266                         /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */
 267                         reg_1p8a: ldo2 {
 268                                 regulator-name = "vdd1p8a";
 269                                 regulator-min-microvolt = <1816125>;
 270                                 regulator-max-microvolt = <1816125>;
 271                                 lltc,fb-voltage-divider = <301000 200000>;
 272                                 regulator-boot-on;
 273                                 regulator-always-on;
 274                         };
 275
 276                         /* VDD_1P8b: HDMI In analog */
 277                         reg_1p8b: ldo3 {
 278                                 regulator-name = "vdd1p8b";
 279                                 regulator-min-microvolt = <1800000>;
 280                                 regulator-max-microvolt = <1800000>;
 281                                 regulator-boot-on;
 282                         };
 283
 284                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 285                         reg_3p0: ldo4 {
 286                                 regulator-name = "vdd3p0";
 287                                 regulator-min-microvolt = <3023250>;
 288                                 regulator-max-microvolt = <3023250>;
 289                                 lltc,fb-voltage-divider = <634000 200000>;
 290                                 regulator-boot-on;
 291                                 regulator-always-on;
 292                         };
 293                 };
 294         };
 295 };
 296
 297 &i2c3 {
 298         clock-frequency = <100000>;
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&pinctrl_i2c3>;
 301         status = "okay";
 302
 303         gpio_exp: pca9555@24 {
 304                 compatible = "nxp,pca9555";
 305                 reg = <0x24>;
 306                 gpio-controller;
 307                 #gpio-cells = <2>;
 308         };
 309
 310         hdmi_receiver: hdmi-receiver@48 {
 311                 compatible = "nxp,tda19971";
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&pinctrl_tda1997x>;
 314                 reg = <0x48>;
 315                 interrupt-parent = <&gpio1>;
 316                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 317                 DOVDD-supply = <&reg_3p3>;
 318                 AVDD-supply = <&reg_1p8b>;
 319                 DVDD-supply = <&reg_1p8a>;
 320                 #sound-dai-cells = <0>;
 321                 nxp,audout-format = "i2s";
 322                 nxp,audout-layout = <0>;
 323                 nxp,audout-width = <16>;
 324                 nxp,audout-mclk-fs = <128>;
 325                 /*
 326                  * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
 327                  * and Y[11:4] across 16bits in the same cycle
 328                  * which we map to VP[15:08]<->CSI_DATA[19:12]
 329                  */
 330                 nxp,vidout-portcfg =
 331                         /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
 332                         < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
 333                         /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
 334                         < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
 335                         /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
 336                         < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
 337                         /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
 338                         < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
 339
 340                 port {
 341                         tda1997x_to_ipu1_csi0_mux: endpoint {
 342                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 343                                 bus-width = <16>;
 344                                 hsync-active = <1>;
 345                                 vsync-active = <1>;
 346                                 data-active = <1>;
 347                         };
 348                 };
 349         };
 350 };
 351
 352 &ipu1_csi0_from_ipu1_csi0_mux {
 353         bus-width = <16>;
 354 };
 355
 356 &ipu1_csi0_mux_from_parallel_sensor {
 357         remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
 358         bus-width = <16>;
 359 };
 360
 361 &ipu1_csi0 {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 364 };
 365
 366 &pcie {
 367         pinctrl-names = "default";
 368         pinctrl-0 = <&pinctrl_pcie>;
 369         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 370         status = "okay";
 371 };
 372
 373 &pwm2 {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 376         status = "disabled";
 377 };
 378
 379 &pwm3 {
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 382         status = "disabled";
 383 };
 384
 385 &ssi1 {
 386         status = "okay";
 387 };
 388
 389 &uart2 {
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_uart2>;
 392         status = "okay";
 393 };
 394
 395 &uart3 {
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_uart3>;
 398         status = "okay";
 399 };
 400
 401 &usbotg {
 402         vbus-supply = <&reg_usb_otg_vbus>;
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_usbotg>;
 405         disable-over-current;
 406         status = "okay";
 407 };
 408
 409 &usbh1 {
 410         vbus-supply = <&reg_usb_h1_vbus>;
 411         status = "okay";
 412 };
 413
 414 &wdog1 {
 415         pinctrl-names = "default";
 416         pinctrl-0 = <&pinctrl_wdog>;
 417         fsl,ext-reset-output;
 418 };
 419
 420 &iomuxc {
 421         pinctrl_audmux: audmuxgrp {
 422                 fsl,pins = <
 423                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 424                         MX6QDL_PAD_DISP0_DAT14__AUD5_RXC        0x130b0
 425                         MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS       0x130b0
 426                 >;
 427         };
 428
 429         pinctrl_flexcan1: flexcan1grp {
 430                 fsl,pins = <
 431                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 432                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 433                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* CAN_STBY */
 434                 >;
 435         };
 436
 437         pinctrl_gpio_leds: gpioledsgrp {
 438                 fsl,pins = <
 439                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
 440                 >;
 441         };
 442
 443         pinctrl_gpmi_nand: gpminandgrp {
 444                 fsl,pins = <
 445                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 446                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 447                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 448                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 449                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 450                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 451                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 452                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 453                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 454                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 455                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 456                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 457                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 458                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 459                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 460                 >;
 461         };
 462
 463         pinctrl_i2c1: i2c1grp {
 464                 fsl,pins = <
 465                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 466                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 467                 >;
 468         };
 469
 470         pinctrl_i2c2: i2c2grp {
 471                 fsl,pins = <
 472                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 473                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 474                 >;
 475         };
 476
 477         pinctrl_i2c3: i2c3grp {
 478                 fsl,pins = <
 479                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 480                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 481                 >;
 482         };
 483
 484         pinctrl_ipu1_csi0: ipu1_csi0grp {
 485                 fsl,pins = <
 486                         MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04          0x1b0b0
 487                         MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05          0x1b0b0
 488                         MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06          0x1b0b0
 489                         MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07          0x1b0b0
 490                         MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08          0x1b0b0
 491                         MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09          0x1b0b0
 492                         MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10         0x1b0b0
 493                         MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11         0x1b0b0
 494                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12         0x1b0b0
 495                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13         0x1b0b0
 496                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14         0x1b0b0
 497                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15         0x1b0b0
 498                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16         0x1b0b0
 499                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17         0x1b0b0
 500                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18         0x1b0b0
 501                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19         0x1b0b0
 502                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC           0x1b0b0
 503                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK        0x1b0b0
 504                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC          0x1b0b0
 505                 >;
 506         };
 507
 508         pinctrl_pcie: pciegrp {
 509                 fsl,pins = <
 510                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0 /* PCIE RST */
 511                 >;
 512         };
 513
 514         pinctrl_pmic: pmicgrp {
 515                 fsl,pins = <
 516                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 517                 >;
 518         };
 519
 520         pinctrl_pwm2: pwm2grp {
 521                 fsl,pins = <
 522                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 523                 >;
 524         };
 525
 526         pinctrl_pwm3: pwm3grp {
 527                 fsl,pins = <
 528                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 529                 >;
 530         };
 531
 532         pinctrl_tda1997x: tda1997xgrp {
 533                 fsl,pins = <
 534                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
 535                 >;
 536         };
 537
 538         pinctrl_uart2: uart2grp {
 539                 fsl,pins = <
 540                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 541                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 542                 >;
 543         };
 544
 545         pinctrl_uart3: uart3grp {
 546                 fsl,pins = <
 547                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 548                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 549                 >;
 550         };
 551
 552         pinctrl_usbotg: usbotggrp {
 553                 fsl,pins = <
 554                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 555                 >;
 556         };
 557
 558         pinctrl_wdog: wdoggrp {
 559                 fsl,pins = <
 560                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 561                 >;
 562         };
 563 };