arch/arm/boot/dts/imx6qdl-gw551x.dtsi

   1 /*
   2  * Copyright 2014 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/media/tda1997x.h>
  50 #include <dt-bindings/input/linux-event-codes.h>
  51 #include <dt-bindings/sound/fsl-imx-audmux.h>
  52
  53 / {
  54         /* these are used by bootloader for disabling nodes */
  55         aliases {
  56                 led0 = &led0;
  57                 nand = &gpmi;
  58                 ssi0 = &ssi1;
  59                 usb0 = &usbh1;
  60                 usb1 = &usbotg;
  61         };
  62
  63         chosen {
  64                 bootargs = "console=ttymxc1,115200";
  65         };
  66
  67         gpio-keys {
  68                 compatible = "gpio-keys";
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 user-pb {
  73                         label = "user_pb";
  74                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  75                         linux,code = <BTN_0>;
  76                 };
  77
  78                 user-pb1x {
  79                         label = "user_pb1x";
  80                         linux,code = <BTN_1>;
  81                         interrupt-parent = <&gsc>;
  82                         interrupts = <0>;
  83                 };
  84
  85                 key-erased {
  86                         label = "key-erased";
  87                         linux,code = <BTN_2>;
  88                         interrupt-parent = <&gsc>;
  89                         interrupts = <1>;
  90                 };
  91
  92                 eeprom-wp {
  93                         label = "eeprom_wp";
  94                         linux,code = <BTN_3>;
  95                         interrupt-parent = <&gsc>;
  96                         interrupts = <2>;
  97                 };
  98
  99                 tamper {
 100                         label = "tamper";
 101                         linux,code = <BTN_4>;
 102                         interrupt-parent = <&gsc>;
 103                         interrupts = <5>;
 104                 };
 105
 106                 switch-hold {
 107                         label = "switch_hold";
 108                         linux,code = <BTN_5>;
 109                         interrupt-parent = <&gsc>;
 110                         interrupts = <7>;
 111                 };
 112         };
 113
 114         leds {
 115                 compatible = "gpio-leds";
 116                 pinctrl-names = "default";
 117                 pinctrl-0 = <&pinctrl_gpio_leds>;
 118
 119                 led0: user1 {
 120                         label = "user1";
 121                         gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
 122                         default-state = "on";
 123                         linux,default-trigger = "heartbeat";
 124                 };
 125         };
 126
 127         memory@10000000 {
 128                 device_type = "memory";
 129                 reg = <0x10000000 0x20000000>;
 130         };
 131
 132         reg_5p0v: regulator-5p0v {
 133                 compatible = "regulator-fixed";
 134                 regulator-name = "5P0V";
 135                 regulator-min-microvolt = <5000000>;
 136                 regulator-max-microvolt = <5000000>;
 137         };
 138
 139         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 140                 compatible = "regulator-fixed";
 141                 regulator-name = "usb_h1_vbus";
 142                 regulator-min-microvolt = <5000000>;
 143                 regulator-max-microvolt = <5000000>;
 144         };
 145
 146         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 147                 compatible = "regulator-fixed";
 148                 regulator-name = "usb_otg_vbus";
 149                 regulator-min-microvolt = <5000000>;
 150                 regulator-max-microvolt = <5000000>;
 151         };
 152
 153         sound-digital {
 154                 compatible = "simple-audio-card";
 155                 simple-audio-card,name = "tda1997x-audio";
 156                 simple-audio-card,format = "i2s";
 157                 simple-audio-card,bitclock-master = <&sound_codec>;
 158                 simple-audio-card,frame-master = <&sound_codec>;
 159
 160                 sound_cpu: simple-audio-card,cpu {
 161                         sound-dai = <&ssi1>;
 162                 };
 163
 164                 sound_codec: simple-audio-card,codec {
 165                         sound-dai = <&hdmi_receiver>;
 166                 };
 167         };
 168 };
 169
 170 &audmux {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
 173         status = "okay";
 174
 175         ssi1 {
 176                 fsl,audmux-port = <0>;
 177                 fsl,port-config = <
 178                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 179                         IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
 180                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 181                         IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
 182                         IMX_AUDMUX_V2_PTCR_SYN)
 183                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 184                 >;
 185         };
 186
 187         aud5 {
 188                 fsl,audmux-port = <4>;
 189                 fsl,port-config = <
 190                         IMX_AUDMUX_V2_PTCR_SYN
 191                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
 192         };
 193 };
 194
 195 &can1 {
 196         pinctrl-names = "default";
 197         pinctrl-0 = <&pinctrl_flexcan1>;
 198         status = "okay";
 199 };
 200
 201 &gpmi {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_gpmi_nand>;
 204         status = "okay";
 205 };
 206
 207 &hdmi {
 208         ddc-i2c-bus = <&i2c3>;
 209         status = "okay";
 210 };
 211
 212 &i2c1 {
 213         clock-frequency = <100000>;
 214         pinctrl-names = "default";
 215         pinctrl-0 = <&pinctrl_i2c1>;
 216         status = "okay";
 217
 218         gsc: gsc@20 {
 219                 compatible = "gw,gsc";
 220                 reg = <0x20>;
 221                 interrupt-parent = <&gpio1>;
 222                 interrupts = <4 GPIO_ACTIVE_LOW>;
 223                 interrupt-controller;
 224                 #interrupt-cells = <1>;
 225                 #size-cells = <0>;
 226
 227                 adc {
 228                         compatible = "gw,gsc-adc";
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231
 232                         channel@0 {
 233                                 gw,mode = <0>;
 234                                 reg = <0x00>;
 235                                 label = "temp";
 236                         };
 237
 238                         channel@2 {
 239                                 gw,mode = <1>;
 240                                 reg = <0x02>;
 241                                 label = "vdd_vin";
 242                         };
 243
 244                         channel@5 {
 245                                 gw,mode = <1>;
 246                                 reg = <0x05>;
 247                                 label = "vdd_3p3";
 248                         };
 249
 250                         channel@8 {
 251                                 gw,mode = <1>;
 252                                 reg = <0x08>;
 253                                 label = "vdd_bat";
 254                         };
 255
 256                         channel@b {
 257                                 gw,mode = <1>;
 258                                 reg = <0x0b>;
 259                                 label = "vdd_5p0";
 260                         };
 261
 262                         channel@e {
 263                                 gw,mode = <1>;
 264                                 reg = <0xe>;
 265                                 label = "vdd_arm";
 266                         };
 267
 268                         channel@11 {
 269                                 gw,mode = <1>;
 270                                 reg = <0x11>;
 271                                 label = "vdd_soc";
 272                         };
 273
 274                         channel@14 {
 275                                 gw,mode = <1>;
 276                                 reg = <0x14>;
 277                                 label = "vdd_3p0";
 278                         };
 279
 280                         channel@17 {
 281                                 gw,mode = <1>;
 282                                 reg = <0x17>;
 283                                 label = "vdd_1p5";
 284                         };
 285
 286                         channel@1d {
 287                                 gw,mode = <1>;
 288                                 reg = <0x1d>;
 289                                 label = "vdd_1p8a";
 290                         };
 291
 292                         channel@20 {
 293                                 gw,mode = <1>;
 294                                 reg = <0x20>;
 295                                 label = "vdd_1p0b";
 296                         };
 297                 };
 298         };
 299
 300         gsc_gpio: gpio@23 {
 301                 compatible = "nxp,pca9555";
 302                 reg = <0x23>;
 303                 gpio-controller;
 304                 #gpio-cells = <2>;
 305                 interrupt-parent = <&gsc>;
 306                 interrupts = <4>;
 307         };
 308
 309         eeprom1: eeprom@50 {
 310                 compatible = "atmel,24c02";
 311                 reg = <0x50>;
 312                 pagesize = <16>;
 313         };
 314
 315         eeprom2: eeprom@51 {
 316                 compatible = "atmel,24c02";
 317                 reg = <0x51>;
 318                 pagesize = <16>;
 319         };
 320
 321         eeprom3: eeprom@52 {
 322                 compatible = "atmel,24c02";
 323                 reg = <0x52>;
 324                 pagesize = <16>;
 325         };
 326
 327         eeprom4: eeprom@53 {
 328                 compatible = "atmel,24c02";
 329                 reg = <0x53>;
 330                 pagesize = <16>;
 331         };
 332
 333         rtc: ds1672@68 {
 334                 compatible = "dallas,ds1672";
 335                 reg = <0x68>;
 336         };
 337 };
 338
 339 &i2c2 {
 340         clock-frequency = <100000>;
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pinctrl_i2c2>;
 343         status = "okay";
 344
 345         ltc3676: pmic@3c {
 346                 compatible = "lltc,ltc3676";
 347                 reg = <0x3c>;
 348                 pinctrl-names = "default";
 349                 pinctrl-0 = <&pinctrl_pmic>;
 350                 interrupt-parent = <&gpio1>;
 351                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 352
 353                 regulators {
 354                         /* VDD_SOC (1+R1/R2 = 1.635) */
 355                         reg_vdd_soc: sw1 {
 356                                 regulator-name = "vddsoc";
 357                                 regulator-min-microvolt = <674400>;
 358                                 regulator-max-microvolt = <1308000>;
 359                                 lltc,fb-voltage-divider = <127000 200000>;
 360                                 regulator-ramp-delay = <7000>;
 361                                 regulator-boot-on;
 362                                 regulator-always-on;
 363                         };
 364
 365                         /* VDD_DDR (1+R1/R2 = 2.105) */
 366                         reg_vdd_ddr: sw2 {
 367                                 regulator-name = "vddddr";
 368                                 regulator-min-microvolt = <868310>;
 369                                 regulator-max-microvolt = <1684000>;
 370                                 lltc,fb-voltage-divider = <221000 200000>;
 371                                 regulator-ramp-delay = <7000>;
 372                                 regulator-boot-on;
 373                                 regulator-always-on;
 374                         };
 375
 376                         /* VDD_ARM (1+R1/R2 = 1.635) */
 377                         reg_vdd_arm: sw3 {
 378                                 regulator-name = "vddarm";
 379                                 regulator-min-microvolt = <674400>;
 380                                 regulator-max-microvolt = <1308000>;
 381                                 lltc,fb-voltage-divider = <127000 200000>;
 382                                 regulator-ramp-delay = <7000>;
 383                                 regulator-boot-on;
 384                                 regulator-always-on;
 385                         };
 386
 387                         /* VDD_3P3 (1+R1/R2 = 1.281) */
 388                         reg_3p3: sw4 {
 389                                 regulator-name = "vdd3p3";
 390                                 regulator-min-microvolt = <1880000>;
 391                                 regulator-max-microvolt = <3647000>;
 392                                 lltc,fb-voltage-divider = <200000 56200>;
 393                                 regulator-ramp-delay = <7000>;
 394                                 regulator-boot-on;
 395                                 regulator-always-on;
 396                         };
 397
 398                         /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */
 399                         reg_1p8a: ldo2 {
 400                                 regulator-name = "vdd1p8a";
 401                                 regulator-min-microvolt = <1816125>;
 402                                 regulator-max-microvolt = <1816125>;
 403                                 lltc,fb-voltage-divider = <301000 200000>;
 404                                 regulator-boot-on;
 405                                 regulator-always-on;
 406                         };
 407
 408                         /* VDD_1P8b: HDMI In analog */
 409                         reg_1p8b: ldo3 {
 410                                 regulator-name = "vdd1p8b";
 411                                 regulator-min-microvolt = <1800000>;
 412                                 regulator-max-microvolt = <1800000>;
 413                                 regulator-boot-on;
 414                         };
 415
 416                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 417                         reg_3p0: ldo4 {
 418                                 regulator-name = "vdd3p0";
 419                                 regulator-min-microvolt = <3023250>;
 420                                 regulator-max-microvolt = <3023250>;
 421                                 lltc,fb-voltage-divider = <634000 200000>;
 422                                 regulator-boot-on;
 423                                 regulator-always-on;
 424                         };
 425                 };
 426         };
 427 };
 428
 429 &i2c3 {
 430         clock-frequency = <100000>;
 431         pinctrl-names = "default";
 432         pinctrl-0 = <&pinctrl_i2c3>;
 433         status = "okay";
 434
 435         gpio_exp: pca9555@24 {
 436                 compatible = "nxp,pca9555";
 437                 reg = <0x24>;
 438                 gpio-controller;
 439                 #gpio-cells = <2>;
 440         };
 441
 442         hdmi_receiver: hdmi-receiver@48 {
 443                 compatible = "nxp,tda19971";
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&pinctrl_tda1997x>;
 446                 reg = <0x48>;
 447                 interrupt-parent = <&gpio1>;
 448                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 449                 DOVDD-supply = <&reg_3p3>;
 450                 AVDD-supply = <&reg_1p8b>;
 451                 DVDD-supply = <&reg_1p8a>;
 452                 #sound-dai-cells = <0>;
 453                 nxp,audout-format = "i2s";
 454                 nxp,audout-layout = <0>;
 455                 nxp,audout-width = <16>;
 456                 nxp,audout-mclk-fs = <128>;
 457                 /*
 458                  * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
 459                  * and Y[11:4] across 16bits in the same cycle
 460                  * which we map to VP[15:08]<->CSI_DATA[19:12]
 461                  */
 462                 nxp,vidout-portcfg =
 463                         /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
 464                         < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
 465                         /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
 466                         < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
 467                         /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
 468                         < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
 469                         /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
 470                         < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
 471
 472                 port {
 473                         tda1997x_to_ipu1_csi0_mux: endpoint {
 474                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 475                                 bus-width = <16>;
 476                                 hsync-active = <1>;
 477                                 vsync-active = <1>;
 478                                 data-active = <1>;
 479                         };
 480                 };
 481         };
 482 };
 483
 484 &ipu1_csi0_from_ipu1_csi0_mux {
 485         bus-width = <16>;
 486 };
 487
 488 &ipu1_csi0_mux_from_parallel_sensor {
 489         remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
 490         bus-width = <16>;
 491 };
 492
 493 &ipu1_csi0 {
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 496 };
 497
 498 &pcie {
 499         pinctrl-names = "default";
 500         pinctrl-0 = <&pinctrl_pcie>;
 501         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 502         status = "okay";
 503 };
 504
 505 &pwm2 {
 506         pinctrl-names = "default";
 507         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 508         status = "disabled";
 509 };
 510
 511 &pwm3 {
 512         pinctrl-names = "default";
 513         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 514         status = "disabled";
 515 };
 516
 517 &ssi1 {
 518         status = "okay";
 519 };
 520
 521 &uart2 {
 522         pinctrl-names = "default";
 523         pinctrl-0 = <&pinctrl_uart2>;
 524         status = "okay";
 525 };
 526
 527 &uart3 {
 528         pinctrl-names = "default";
 529         pinctrl-0 = <&pinctrl_uart3>;
 530         status = "okay";
 531 };
 532
 533 &usbotg {
 534         vbus-supply = <&reg_usb_otg_vbus>;
 535         pinctrl-names = "default";
 536         pinctrl-0 = <&pinctrl_usbotg>;
 537         disable-over-current;
 538         status = "okay";
 539 };
 540
 541 &usbh1 {
 542         vbus-supply = <&reg_usb_h1_vbus>;
 543         status = "okay";
 544 };
 545
 546 &wdog1 {
 547         pinctrl-names = "default";
 548         pinctrl-0 = <&pinctrl_wdog>;
 549         fsl,ext-reset-output;
 550 };
 551
 552 &iomuxc {
 553         pinctrl_audmux: audmuxgrp {
 554                 fsl,pins = <
 555                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 556                         MX6QDL_PAD_DISP0_DAT14__AUD5_RXC        0x130b0
 557                         MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS       0x130b0
 558                 >;
 559         };
 560
 561         pinctrl_flexcan1: flexcan1grp {
 562                 fsl,pins = <
 563                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 564                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 565                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* CAN_STBY */
 566                 >;
 567         };
 568
 569         pinctrl_gpio_leds: gpioledsgrp {
 570                 fsl,pins = <
 571                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
 572                 >;
 573         };
 574
 575         pinctrl_gpmi_nand: gpminandgrp {
 576                 fsl,pins = <
 577                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 578                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 579                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 580                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 581                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 582                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 583                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 584                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 585                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 586                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 587                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 588                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 589                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 590                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 591                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 592                 >;
 593         };
 594
 595         pinctrl_i2c1: i2c1grp {
 596                 fsl,pins = <
 597                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 598                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 599                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0xb0b1
 600                 >;
 601         };
 602
 603         pinctrl_i2c2: i2c2grp {
 604                 fsl,pins = <
 605                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 606                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 607                 >;
 608         };
 609
 610         pinctrl_i2c3: i2c3grp {
 611                 fsl,pins = <
 612                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 613                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 614                 >;
 615         };
 616
 617         pinctrl_ipu1_csi0: ipu1_csi0grp {
 618                 fsl,pins = <
 619                         MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04          0x1b0b0
 620                         MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05          0x1b0b0
 621                         MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06          0x1b0b0
 622                         MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07          0x1b0b0
 623                         MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08          0x1b0b0
 624                         MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09          0x1b0b0
 625                         MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10         0x1b0b0
 626                         MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11         0x1b0b0
 627                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12         0x1b0b0
 628                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13         0x1b0b0
 629                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14         0x1b0b0
 630                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15         0x1b0b0
 631                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16         0x1b0b0
 632                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17         0x1b0b0
 633                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18         0x1b0b0
 634                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19         0x1b0b0
 635                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC           0x1b0b0
 636                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK        0x1b0b0
 637                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC          0x1b0b0
 638                 >;
 639         };
 640
 641         pinctrl_pcie: pciegrp {
 642                 fsl,pins = <
 643                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0 /* PCIE RST */
 644                 >;
 645         };
 646
 647         pinctrl_pmic: pmicgrp {
 648                 fsl,pins = <
 649                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 650                 >;
 651         };
 652
 653         pinctrl_pwm2: pwm2grp {
 654                 fsl,pins = <
 655                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 656                 >;
 657         };
 658
 659         pinctrl_pwm3: pwm3grp {
 660                 fsl,pins = <
 661                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 662                 >;
 663         };
 664
 665         pinctrl_tda1997x: tda1997xgrp {
 666                 fsl,pins = <
 667                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
 668                 >;
 669         };
 670
 671         pinctrl_uart2: uart2grp {
 672                 fsl,pins = <
 673                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 674                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 675                 >;
 676         };
 677
 678         pinctrl_uart3: uart3grp {
 679                 fsl,pins = <
 680                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 681                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 682                 >;
 683         };
 684
 685         pinctrl_usbotg: usbotggrp {
 686                 fsl,pins = <
 687                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 688                 >;
 689         };
 690
 691         pinctrl_wdog: wdoggrp {
 692                 fsl,pins = <
 693                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 694                 >;
 695         };
 696 };