1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2013 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
9 /* these are used by bootloader for disabling nodes */
21 bootargs = "console=ttymxc1,115200";
25 compatible = "pwm-backlight";
26 pwms = <&pwm4 0 5000000>;
27 brightness-levels = <0 4 8 16 32 64 128 255>;
28 default-brightness-level = <7>;
32 compatible = "gpio-leds";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_gpio_leds>;
38 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
40 linux,default-trigger = "heartbeat";
45 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
46 default-state = "off";
51 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
52 default-state = "off";
57 device_type = "memory";
58 reg = <0x10000000 0x40000000>;
62 compatible = "pps-gpio";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_pps>;
65 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
69 reg_1p0v: regulator-1p0v {
70 compatible = "regulator-fixed";
71 regulator-name = "1P0V";
72 regulator-min-microvolt = <1000000>;
73 regulator-max-microvolt = <1000000>;
77 reg_3p3v: regulator-3p3v {
78 compatible = "regulator-fixed";
79 regulator-name = "3P3V";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
85 reg_usb_h1_vbus: regulator-usb-h1-vbus {
86 compatible = "regulator-fixed";
87 regulator-name = "usb_h1_vbus";
88 regulator-min-microvolt = <5000000>;
89 regulator-max-microvolt = <5000000>;
93 reg_usb_otg_vbus: regulator-usb-otg-vbus {
94 compatible = "regulator-fixed";
95 regulator-name = "usb_otg_vbus";
96 regulator-min-microvolt = <5000000>;
97 regulator-max-microvolt = <5000000>;
98 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
103 compatible = "fsl,imx6q-ventana-sgtl5000",
104 "fsl,imx-audio-sgtl5000";
105 model = "sgtl5000-audio";
106 ssi-controller = <&ssi1>;
107 audio-codec = <&codec>;
109 "MIC_IN", "Mic Jack",
110 "Mic Jack", "Mic Bias",
111 "Headphone Jack", "HP_OUT";
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_audmux>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_flexcan1>;
130 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
131 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
132 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
133 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_enet>;
139 phy-mode = "rgmii-id";
140 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_gpmi_nand>;
151 ddc-i2c-bus = <&i2c3>;
156 clock-frequency = <100000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c1>;
162 compatible = "atmel,24c02";
168 compatible = "atmel,24c02";
174 compatible = "atmel,24c02";
180 compatible = "atmel,24c02";
186 compatible = "nxp,pca9555";
193 compatible = "dallas,ds1672";
199 clock-frequency = <100000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c2>;
205 compatible = "lltc,ltc3676";
207 interrupt-parent = <&gpio1>;
208 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
211 /* VDD_SOC (1+R1/R2 = 1.635) */
213 regulator-name = "vddsoc";
214 regulator-min-microvolt = <674400>;
215 regulator-max-microvolt = <1308000>;
216 lltc,fb-voltage-divider = <127000 200000>;
217 regulator-ramp-delay = <7000>;
222 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
224 regulator-name = "vdd1p8";
225 regulator-min-microvolt = <1033310>;
226 regulator-max-microvolt = <2004000>;
227 lltc,fb-voltage-divider = <301000 200000>;
228 regulator-ramp-delay = <7000>;
233 /* VDD_ARM (1+R1/R2 = 1.635) */
235 regulator-name = "vddarm";
236 regulator-min-microvolt = <674400>;
237 regulator-max-microvolt = <1308000>;
238 lltc,fb-voltage-divider = <127000 200000>;
239 regulator-ramp-delay = <7000>;
244 /* VDD_DDR (1+R1/R2 = 2.105) */
246 regulator-name = "vddddr";
247 regulator-min-microvolt = <868310>;
248 regulator-max-microvolt = <1684000>;
249 lltc,fb-voltage-divider = <221000 200000>;
250 regulator-ramp-delay = <7000>;
255 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
257 regulator-name = "vdd2p5";
258 regulator-min-microvolt = <2490375>;
259 regulator-max-microvolt = <2490375>;
260 lltc,fb-voltage-divider = <487000 200000>;
265 /* VDD_AUD_1P8: Audio codec */
267 regulator-name = "vdd1p8a";
268 regulator-min-microvolt = <1800000>;
269 regulator-max-microvolt = <1800000>;
273 /* VDD_HIGH (1+R1/R2 = 4.17) */
275 regulator-name = "vdd3p0";
276 regulator-min-microvolt = <3023250>;
277 regulator-max-microvolt = <3023250>;
278 lltc,fb-voltage-divider = <634000 200000>;
287 clock-frequency = <100000>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c3>;
293 compatible = "fsl,sgtl5000";
295 clocks = <&clks IMX6QDL_CLK_CKO>;
296 VDDA-supply = <®_1p8v>;
297 VDDIO-supply = <®_3p3v>;
300 touchscreen: egalax_ts@4 {
301 compatible = "eeti,egalax_ts";
303 interrupt-parent = <&gpio1>;
305 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
309 compatible = "nxp,fxos8700";
318 fsl,data-mapping = "spwg";
319 fsl,data-width = <18>;
323 native-mode = <&timing0>;
324 timing0: hsd100pxn1 {
325 clock-frequency = <65000000>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_pcie>;
342 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_pwm4>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_uart1>;
371 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_uart2>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_uart5>;
388 vbus-supply = <®_usb_otg_vbus>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_usbotg>;
391 disable-over-current;
396 vbus-supply = <®_usb_h1_vbus>;
401 pinctrl-names = "default", "state_100mhz", "state_200mhz";
402 pinctrl-0 = <&pinctrl_usdhc3>;
403 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
404 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
405 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
406 vmmc-supply = <®_3p3v>;
407 no-1-8-v; /* firmware will remove if board revision supports */
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_wdog>;
414 fsl,ext-reset-output;
418 pinctrl_audmux: audmuxgrp {
420 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
421 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
422 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
423 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
424 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
428 pinctrl_enet: enetgrp {
430 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
431 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
432 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
433 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
434 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
435 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
436 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
437 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
438 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
439 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
440 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
441 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
442 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
443 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
444 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
445 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
449 pinctrl_flexcan1: flexcan1grp {
451 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
452 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
453 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
457 pinctrl_gpio_leds: gpioledsgrp {
459 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
460 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
461 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
465 pinctrl_gpmi_nand: gpminandgrp {
467 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
468 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
469 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
470 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
471 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
472 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
473 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
474 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
475 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
476 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
477 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
478 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
479 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
480 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
481 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
485 pinctrl_i2c1: i2c1grp {
487 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
488 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
492 pinctrl_i2c2: i2c2grp {
494 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
495 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
499 pinctrl_i2c3: i2c3grp {
501 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
502 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
506 pinctrl_pcie: pciegrp {
508 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
509 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
513 pinctrl_pmic: pmicgrp {
515 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
519 pinctrl_pps: ppsgrp {
521 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
525 pinctrl_pwm2: pwm2grp {
527 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
531 pinctrl_pwm3: pwm3grp {
533 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
537 pinctrl_pwm4: pwm4grp {
539 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
543 pinctrl_uart1: uart1grp {
545 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
546 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
547 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
551 pinctrl_uart2: uart2grp {
553 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
554 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
558 pinctrl_uart5: uart5grp {
560 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
561 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
565 pinctrl_usbotg: usbotggrp {
567 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
568 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
569 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
573 pinctrl_usdhc3: usdhc3grp {
575 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
576 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
577 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
578 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
579 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
580 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
581 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
582 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
586 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
588 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
589 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
590 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
591 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
592 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
593 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
594 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
595 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
599 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
601 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
602 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
603 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
604 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
605 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
606 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
607 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
608 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
612 pinctrl_wdog: wdoggrp {
614 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0