1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2013 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
11 /* these are used by bootloader for disabling nodes */
23 bootargs = "console=ttymxc1,115200";
27 compatible = "pwm-backlight";
28 pwms = <&pwm4 0 5000000>;
29 brightness-levels = <0 4 8 16 32 64 128 255>;
30 default-brightness-level = <7>;
34 compatible = "gpio-keys";
38 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
45 interrupt-parent = <&gsc>;
52 interrupt-parent = <&gsc>;
59 interrupt-parent = <&gsc>;
66 interrupt-parent = <&gsc>;
71 label = "switch_hold";
73 interrupt-parent = <&gsc>;
79 compatible = "gpio-leds";
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_gpio_leds>;
85 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
87 linux,default-trigger = "heartbeat";
92 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
93 default-state = "off";
98 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
99 default-state = "off";
104 device_type = "memory";
105 reg = <0x10000000 0x20000000>;
109 compatible = "pps-gpio";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_pps>;
112 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
116 reg_1p0v: regulator-1p0v {
117 compatible = "regulator-fixed";
118 regulator-name = "1P0V";
119 regulator-min-microvolt = <1000000>;
120 regulator-max-microvolt = <1000000>;
124 reg_3p3v: regulator-3p3v {
125 compatible = "regulator-fixed";
126 regulator-name = "3P3V";
127 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <3300000>;
132 reg_5p0v: regulator-5p0v {
133 compatible = "regulator-fixed";
134 regulator-name = "5P0V";
135 regulator-min-microvolt = <5000000>;
136 regulator-max-microvolt = <5000000>;
140 reg_usb_otg_vbus: regulator-usb-otg-vbus {
141 compatible = "regulator-fixed";
142 regulator-name = "usb_otg_vbus";
143 regulator-min-microvolt = <5000000>;
144 regulator-max-microvolt = <5000000>;
145 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
150 compatible = "fsl,imx6q-ventana-sgtl5000",
151 "fsl,imx-audio-sgtl5000";
152 model = "sgtl5000-audio";
153 ssi-controller = <&ssi1>;
154 audio-codec = <&codec>;
156 "MIC_IN", "Mic Jack",
157 "Mic Jack", "Mic Bias",
158 "Headphone Jack", "HP_OUT";
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_audmux>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_flexcan1>;
177 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
178 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
179 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
180 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
184 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_ecspi3>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_enet>;
193 phy-mode = "rgmii-id";
194 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_gpmi_nand>;
205 ddc-i2c-bus = <&i2c3>;
210 clock-frequency = <100000>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_i2c1>;
216 compatible = "gw,gsc";
218 interrupt-parent = <&gpio1>;
219 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
220 interrupt-controller;
221 #interrupt-cells = <1>;
225 compatible = "gw,gsc-adc";
226 #address-cells = <1>;
310 compatible = "nxp,pca9555";
314 interrupt-parent = <&gsc>;
319 compatible = "atmel,24c02";
325 compatible = "atmel,24c02";
331 compatible = "atmel,24c02";
337 compatible = "atmel,24c02";
343 compatible = "dallas,ds1672";
349 clock-frequency = <100000>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_i2c2>;
355 compatible = "lltc,ltc3676";
357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_pmic>;
359 interrupt-parent = <&gpio1>;
360 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
363 /* VDD_SOC (1+R1/R2 = 1.635) */
365 regulator-name = "vddsoc";
366 regulator-min-microvolt = <674400>;
367 regulator-max-microvolt = <1308000>;
368 lltc,fb-voltage-divider = <127000 200000>;
369 regulator-ramp-delay = <7000>;
374 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
376 regulator-name = "vdd1p8";
377 regulator-min-microvolt = <1033310>;
378 regulator-max-microvolt = <2004000>;
379 lltc,fb-voltage-divider = <301000 200000>;
380 regulator-ramp-delay = <7000>;
385 /* VDD_ARM (1+R1/R2 = 1.635) */
387 regulator-name = "vddarm";
388 regulator-min-microvolt = <674400>;
389 regulator-max-microvolt = <1308000>;
390 lltc,fb-voltage-divider = <127000 200000>;
391 regulator-ramp-delay = <7000>;
396 /* VDD_DDR (1+R1/R2 = 2.105) */
398 regulator-name = "vddddr";
399 regulator-min-microvolt = <868310>;
400 regulator-max-microvolt = <1684000>;
401 lltc,fb-voltage-divider = <221000 200000>;
402 regulator-ramp-delay = <7000>;
407 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
409 regulator-name = "vdd2p5";
410 regulator-min-microvolt = <2490375>;
411 regulator-max-microvolt = <2490375>;
412 lltc,fb-voltage-divider = <487000 200000>;
417 /* VDD_AUD_1P8: Audio codec */
419 regulator-name = "vdd1p8a";
420 regulator-min-microvolt = <1800000>;
421 regulator-max-microvolt = <1800000>;
425 /* VDD_HIGH (1+R1/R2 = 4.17) */
427 regulator-name = "vdd3p0";
428 regulator-min-microvolt = <3023250>;
429 regulator-max-microvolt = <3023250>;
430 lltc,fb-voltage-divider = <634000 200000>;
439 clock-frequency = <100000>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_i2c3>;
445 compatible = "fsl,sgtl5000";
447 clocks = <&clks IMX6QDL_CLK_CKO>;
448 VDDA-supply = <®_1p8v>;
449 VDDIO-supply = <®_3p3v>;
452 touchscreen: egalax_ts@4 {
453 compatible = "eeti,egalax_ts";
455 interrupt-parent = <&gpio7>;
457 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
461 compatible = "nxp,fxos8700";
470 fsl,data-mapping = "spwg";
471 fsl,data-width = <18>;
475 native-mode = <&timing0>;
476 timing0: hsd100pxn1 {
477 clock-frequency = <65000000>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&pinctrl_pcie>;
494 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
505 pinctrl-names = "default";
506 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
512 pinctrl-names = "default";
513 pinctrl-0 = <&pinctrl_pwm4>;
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_uart1>;
524 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_uart2>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&pinctrl_uart5>;
541 vbus-supply = <®_usb_otg_vbus>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pinctrl_usbotg>;
544 disable-over-current;
553 pinctrl-names = "default", "state_100mhz", "state_200mhz";
554 pinctrl-0 = <&pinctrl_usdhc3>;
555 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
556 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
557 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
558 vmmc-supply = <®_3p3v>;
559 no-1-8-v; /* firmware will remove if board revision supports */
564 pinctrl-names = "default";
565 pinctrl-0 = <&pinctrl_wdog>;
566 fsl,ext-reset-output;
570 pinctrl_audmux: audmuxgrp {
572 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
573 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
574 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
575 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
576 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
580 pinctrl_ecspi3: escpi3grp {
582 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
583 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
584 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
585 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
589 pinctrl_enet: enetgrp {
591 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
592 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
593 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
594 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
595 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
596 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
597 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
598 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
599 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
600 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
601 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
602 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
603 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
604 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
605 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
606 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
607 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
611 pinctrl_flexcan1: flexcan1grp {
613 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
614 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
615 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
619 pinctrl_gpio_leds: gpioledsgrp {
621 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
622 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
623 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
627 pinctrl_gpmi_nand: gpminandgrp {
629 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
630 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
631 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
632 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
633 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
634 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
635 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
636 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
637 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
638 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
639 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
640 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
641 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
642 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
643 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
647 pinctrl_i2c1: i2c1grp {
649 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
650 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
651 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
655 pinctrl_i2c2: i2c2grp {
657 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
658 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
662 pinctrl_i2c3: i2c3grp {
664 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
665 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
669 pinctrl_pcie: pciegrp {
671 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
675 pinctrl_pmic: pmicgrp {
677 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
681 pinctrl_pps: ppsgrp {
683 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
687 pinctrl_pwm2: pwm2grp {
689 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
693 pinctrl_pwm3: pwm3grp {
695 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
699 pinctrl_pwm4: pwm4grp {
701 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
705 pinctrl_uart1: uart1grp {
707 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
708 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
709 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
713 pinctrl_uart2: uart2grp {
715 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
716 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
720 pinctrl_uart5: uart5grp {
722 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
723 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
727 pinctrl_usbotg: usbotggrp {
729 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
730 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
734 pinctrl_usdhc3: usdhc3grp {
736 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
737 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
738 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
739 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
740 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
741 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
742 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
743 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
747 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
749 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
750 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
751 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
752 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
753 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
754 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
755 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
756 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
760 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
762 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
763 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
764 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
765 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
766 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
767 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
768 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
769 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
773 pinctrl_wdog: wdoggrp {
775 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0