1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2013 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
11 /* these are used by bootloader for disabling nodes */
21 bootargs = "console=ttymxc1,115200";
25 compatible = "gpio-keys";
31 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
38 interrupt-parent = <&gsc>;
45 interrupt-parent = <&gsc>;
52 interrupt-parent = <&gsc>;
59 interrupt-parent = <&gsc>;
64 label = "switch_hold";
66 interrupt-parent = <&gsc>;
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpio_leds>;
78 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
80 linux,default-trigger = "heartbeat";
85 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
86 default-state = "off";
91 device_type = "memory";
92 reg = <0x10000000 0x20000000>;
96 compatible = "pps-gpio";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_pps>;
99 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
103 reg_3p3v: regulator-3p3v {
104 compatible = "regulator-fixed";
105 regulator-name = "3P3V";
106 regulator-min-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>;
111 reg_5p0v: regulator-5p0v {
112 compatible = "regulator-fixed";
113 regulator-name = "5P0V";
114 regulator-min-microvolt = <5000000>;
115 regulator-max-microvolt = <5000000>;
119 reg_usb_otg_vbus: regulator-usb-otg-vbus {
120 compatible = "regulator-fixed";
121 regulator-name = "usb_otg_vbus";
122 regulator-min-microvolt = <5000000>;
123 regulator-max-microvolt = <5000000>;
124 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_enet>;
132 phy-mode = "rgmii-id";
133 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_gpmi_nand>;
144 ddc-i2c-bus = <&i2c3>;
149 clock-frequency = <100000>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_i2c1>;
155 compatible = "gw,gsc";
157 interrupt-parent = <&gpio1>;
158 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
159 interrupt-controller;
160 #interrupt-cells = <1>;
164 compatible = "gw,gsc-adc";
165 #address-cells = <1>;
243 compatible = "nxp,pca9555";
247 interrupt-parent = <&gsc>;
252 compatible = "atmel,24c02";
258 compatible = "atmel,24c02";
264 compatible = "atmel,24c02";
270 compatible = "atmel,24c02";
276 compatible = "dallas,ds1672";
282 clock-frequency = <100000>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_i2c2>;
288 compatible = "lltc,ltc3676";
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_pmic>;
292 interrupt-parent = <&gpio1>;
293 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
296 /* VDD_SOC (1+R1/R2 = 1.635) */
298 regulator-name = "vddsoc";
299 regulator-min-microvolt = <674400>;
300 regulator-max-microvolt = <1308000>;
301 lltc,fb-voltage-divider = <127000 200000>;
302 regulator-ramp-delay = <7000>;
307 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
309 regulator-name = "vdd1p8";
310 regulator-min-microvolt = <1033310>;
311 regulator-max-microvolt = <2004000>;
312 lltc,fb-voltage-divider = <301000 200000>;
313 regulator-ramp-delay = <7000>;
318 /* VDD_ARM (1+R1/R2 = 1.635) */
320 regulator-name = "vddarm";
321 regulator-min-microvolt = <674400>;
322 regulator-max-microvolt = <1308000>;
323 lltc,fb-voltage-divider = <127000 200000>;
324 regulator-ramp-delay = <7000>;
329 /* VDD_DDR (1+R1/R2 = 2.105) */
331 regulator-name = "vddddr";
332 regulator-min-microvolt = <868310>;
333 regulator-max-microvolt = <1684000>;
334 lltc,fb-voltage-divider = <221000 200000>;
335 regulator-ramp-delay = <7000>;
340 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
342 regulator-name = "vdd2p5";
343 regulator-min-microvolt = <2490375>;
344 regulator-max-microvolt = <2490375>;
345 lltc,fb-voltage-divider = <487000 200000>;
350 /* VDD_HIGH (1+R1/R2 = 4.17) */
352 regulator-name = "vdd3p0";
353 regulator-min-microvolt = <3023250>;
354 regulator-max-microvolt = <3023250>;
355 lltc,fb-voltage-divider = <634000 200000>;
364 clock-frequency = <100000>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_i2c3>;
370 compatible = "adi,adv7180";
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_adv7180>;
374 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
375 interrupt-parent = <&gpio5>;
376 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
379 adv7180_to_ipu1_csi0_mux: endpoint {
380 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
387 &ipu1_csi0_from_ipu1_csi0_mux {
391 &ipu1_csi0_mux_from_parallel_sensor {
392 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_ipu1_csi0>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_pcie>;
404 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_uart1>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_uart2>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&pinctrl_uart3>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_uart5>;
451 vbus-supply = <®_usb_otg_vbus>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_usbotg>;
454 disable-over-current;
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_wdog>;
465 fsl,ext-reset-output;
469 pinctrl_adv7180: adv7180grp {
471 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
472 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
476 pinctrl_enet: enetgrp {
478 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
479 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
480 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
481 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
482 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
483 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
484 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
485 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
486 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
487 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
488 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
489 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
490 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
491 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
492 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
493 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
494 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
498 pinctrl_gpio_leds: gpioledsgrp {
500 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
501 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
505 pinctrl_gpmi_nand: gpminandgrp {
507 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
508 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
509 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
510 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
511 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
512 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
513 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
514 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
515 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
516 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
517 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
518 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
519 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
520 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
521 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
525 pinctrl_i2c1: i2c1grp {
527 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
528 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
529 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
533 pinctrl_i2c2: i2c2grp {
535 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
536 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
540 pinctrl_i2c3: i2c3grp {
542 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
543 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
547 pinctrl_ipu1_csi0: ipu1csi0grp {
549 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
550 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
551 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
552 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
553 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
554 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
555 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
556 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
557 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
558 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
559 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
563 pinctrl_pcie: pciegrp {
565 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
569 pinctrl_pmic: pmicgrp {
571 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
575 pinctrl_pps: ppsgrp {
577 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
581 pinctrl_pwm2: pwm2grp {
583 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
587 pinctrl_pwm3: pwm3grp {
589 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
593 pinctrl_pwm4: pwm4grp {
595 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
599 pinctrl_uart1: uart1grp {
601 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
602 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
606 pinctrl_uart2: uart2grp {
608 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
609 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
613 pinctrl_uart3: uart3grp {
615 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
616 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
620 pinctrl_uart5: uart5grp {
622 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
623 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
627 pinctrl_usbotg: usbotggrp {
629 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
630 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
634 pinctrl_wdog: wdoggrp {
636 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0