1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2013 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
10 /* these are used by bootloader for disabling nodes */
20 bootargs = "console=ttymxc1,115200";
24 compatible = "gpio-keys";
28 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
35 interrupt-parent = <&gsc>;
42 interrupt-parent = <&gsc>;
49 interrupt-parent = <&gsc>;
56 interrupt-parent = <&gsc>;
61 label = "switch_hold";
63 interrupt-parent = <&gsc>;
69 compatible = "gpio-leds";
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_gpio_leds>;
75 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
77 linux,default-trigger = "heartbeat";
82 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
83 default-state = "off";
88 device_type = "memory";
89 reg = <0x10000000 0x20000000>;
93 compatible = "pps-gpio";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_pps>;
96 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
100 reg_3p3v: regulator-3p3v {
101 compatible = "regulator-fixed";
102 regulator-name = "3P3V";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
108 reg_5p0v: regulator-5p0v {
109 compatible = "regulator-fixed";
110 regulator-name = "5P0V";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
116 reg_usb_otg_vbus: regulator-usb-otg-vbus {
117 compatible = "regulator-fixed";
118 regulator-name = "usb_otg_vbus";
119 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>;
121 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_enet>;
129 phy-mode = "rgmii-id";
130 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_gpmi_nand>;
141 ddc-i2c-bus = <&i2c3>;
146 clock-frequency = <100000>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_i2c1>;
152 compatible = "gw,gsc";
154 interrupt-parent = <&gpio1>;
155 interrupts = <4 GPIO_ACTIVE_LOW>;
156 interrupt-controller;
157 #interrupt-cells = <1>;
161 compatible = "gw,gsc-adc";
162 #address-cells = <1>;
240 compatible = "nxp,pca9555";
244 interrupt-parent = <&gsc>;
249 compatible = "atmel,24c02";
255 compatible = "atmel,24c02";
261 compatible = "atmel,24c02";
267 compatible = "atmel,24c02";
273 compatible = "dallas,ds1672";
279 clock-frequency = <100000>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_i2c2>;
285 compatible = "lltc,ltc3676";
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_pmic>;
289 interrupt-parent = <&gpio1>;
290 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
293 /* VDD_SOC (1+R1/R2 = 1.635) */
295 regulator-name = "vddsoc";
296 regulator-min-microvolt = <674400>;
297 regulator-max-microvolt = <1308000>;
298 lltc,fb-voltage-divider = <127000 200000>;
299 regulator-ramp-delay = <7000>;
304 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
306 regulator-name = "vdd1p8";
307 regulator-min-microvolt = <1033310>;
308 regulator-max-microvolt = <2004000>;
309 lltc,fb-voltage-divider = <301000 200000>;
310 regulator-ramp-delay = <7000>;
315 /* VDD_ARM (1+R1/R2 = 1.635) */
317 regulator-name = "vddarm";
318 regulator-min-microvolt = <674400>;
319 regulator-max-microvolt = <1308000>;
320 lltc,fb-voltage-divider = <127000 200000>;
321 regulator-ramp-delay = <7000>;
326 /* VDD_DDR (1+R1/R2 = 2.105) */
328 regulator-name = "vddddr";
329 regulator-min-microvolt = <868310>;
330 regulator-max-microvolt = <1684000>;
331 lltc,fb-voltage-divider = <221000 200000>;
332 regulator-ramp-delay = <7000>;
337 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
339 regulator-name = "vdd2p5";
340 regulator-min-microvolt = <2490375>;
341 regulator-max-microvolt = <2490375>;
342 lltc,fb-voltage-divider = <487000 200000>;
347 /* VDD_HIGH (1+R1/R2 = 4.17) */
349 regulator-name = "vdd3p0";
350 regulator-min-microvolt = <3023250>;
351 regulator-max-microvolt = <3023250>;
352 lltc,fb-voltage-divider = <634000 200000>;
361 clock-frequency = <100000>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_i2c3>;
367 compatible = "adi,adv7180";
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_adv7180>;
371 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
372 interrupt-parent = <&gpio5>;
373 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
376 adv7180_to_ipu1_csi0_mux: endpoint {
377 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
384 &ipu1_csi0_from_ipu1_csi0_mux {
388 &ipu1_csi0_mux_from_parallel_sensor {
389 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_ipu1_csi0>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_pcie>;
401 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_uart1>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_uart2>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_uart3>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_uart5>;
448 vbus-supply = <®_usb_otg_vbus>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pinctrl_usbotg>;
451 disable-over-current;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_wdog>;
462 fsl,ext-reset-output;
466 pinctrl_adv7180: adv7180grp {
468 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
469 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
473 pinctrl_enet: enetgrp {
475 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
476 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
477 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
478 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
479 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
480 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
481 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
482 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
483 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
484 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
485 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
486 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
487 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
488 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
489 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
490 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
491 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
495 pinctrl_gpio_leds: gpioledsgrp {
497 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
498 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
502 pinctrl_gpmi_nand: gpminandgrp {
504 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
505 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
506 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
507 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
508 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
509 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
510 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
511 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
512 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
513 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
514 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
515 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
516 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
517 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
518 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
522 pinctrl_i2c1: i2c1grp {
524 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
525 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
526 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
530 pinctrl_i2c2: i2c2grp {
532 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
533 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
537 pinctrl_i2c3: i2c3grp {
539 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
540 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
544 pinctrl_ipu1_csi0: ipu1csi0grp {
546 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
547 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
548 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
549 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
550 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
551 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
552 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
553 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
554 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
555 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
556 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
560 pinctrl_pcie: pciegrp {
562 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
566 pinctrl_pmic: pmicgrp {
568 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
572 pinctrl_pps: ppsgrp {
574 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
578 pinctrl_pwm2: pwm2grp {
580 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
584 pinctrl_pwm3: pwm3grp {
586 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
590 pinctrl_pwm4: pwm4grp {
592 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
596 pinctrl_uart1: uart1grp {
598 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
599 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
603 pinctrl_uart2: uart2grp {
605 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
606 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
610 pinctrl_uart3: uart3grp {
612 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
613 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
617 pinctrl_uart5: uart5grp {
619 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
620 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
624 pinctrl_usbotg: usbotggrp {
626 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
627 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
631 pinctrl_wdog: wdoggrp {
633 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0