arch/arm/boot/dts/imx6qdl-gw51xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/linux-event-codes.h>
   8
   9 / {
  10         /* these are used by bootloader for disabling nodes */
  11         aliases {
  12                 led0 = &led0;
  13                 led1 = &led1;
  14                 nand = &gpmi;
  15                 usb0 = &usbh1;
  16                 usb1 = &usbotg;
  17         };
  18
  19         chosen {
  20                 bootargs = "console=ttymxc1,115200";
  21         };
  22
  23         gpio-keys {
  24                 compatible = "gpio-keys";
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 user-pb {
  29                         label = "user_pb";
  30                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  31                         linux,code = <BTN_0>;
  32                 };
  33
  34                 user-pb1x {
  35                         label = "user_pb1x";
  36                         linux,code = <BTN_1>;
  37                         interrupt-parent = <&gsc>;
  38                         interrupts = <0>;
  39                 };
  40
  41                 key-erased {
  42                         label = "key-erased";
  43                         linux,code = <BTN_2>;
  44                         interrupt-parent = <&gsc>;
  45                         interrupts = <1>;
  46                 };
  47
  48                 eeprom-wp {
  49                         label = "eeprom_wp";
  50                         linux,code = <BTN_3>;
  51                         interrupt-parent = <&gsc>;
  52                         interrupts = <2>;
  53                 };
  54
  55                 tamper {
  56                         label = "tamper";
  57                         linux,code = <BTN_4>;
  58                         interrupt-parent = <&gsc>;
  59                         interrupts = <5>;
  60                 };
  61
  62                 switch-hold {
  63                         label = "switch_hold";
  64                         linux,code = <BTN_5>;
  65                         interrupt-parent = <&gsc>;
  66                         interrupts = <7>;
  67                 };
  68         };
  69
  70         leds {
  71                 compatible = "gpio-leds";
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&pinctrl_gpio_leds>;
  74
  75                 led0: user1 {
  76                         label = "user1";
  77                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  78                         default-state = "on";
  79                         linux,default-trigger = "heartbeat";
  80                 };
  81
  82                 led1: user2 {
  83                         label = "user2";
  84                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  85                         default-state = "off";
  86                 };
  87         };
  88
  89         memory@10000000 {
  90                 device_type = "memory";
  91                 reg = <0x10000000 0x20000000>;
  92         };
  93
  94         pps {
  95                 compatible = "pps-gpio";
  96                 pinctrl-names = "default";
  97                 pinctrl-0 = <&pinctrl_pps>;
  98                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  99                 status = "okay";
 100         };
 101
 102         reg_3p3v: regulator-3p3v {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "3P3V";
 105                 regulator-min-microvolt = <3300000>;
 106                 regulator-max-microvolt = <3300000>;
 107                 regulator-always-on;
 108         };
 109
 110         reg_5p0v: regulator-5p0v {
 111                 compatible = "regulator-fixed";
 112                 regulator-name = "5P0V";
 113                 regulator-min-microvolt = <5000000>;
 114                 regulator-max-microvolt = <5000000>;
 115                 regulator-always-on;
 116         };
 117
 118         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 119                 compatible = "regulator-fixed";
 120                 regulator-name = "usb_otg_vbus";
 121                 regulator-min-microvolt = <5000000>;
 122                 regulator-max-microvolt = <5000000>;
 123                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 124                 enable-active-high;
 125         };
 126 };
 127
 128 &fec {
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&pinctrl_enet>;
 131         phy-mode = "rgmii-id";
 132         phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 133         status = "okay";
 134 };
 135
 136 &gpmi {
 137         pinctrl-names = "default";
 138         pinctrl-0 = <&pinctrl_gpmi_nand>;
 139         status = "okay";
 140 };
 141
 142 &hdmi {
 143         ddc-i2c-bus = <&i2c3>;
 144         status = "okay";
 145 };
 146
 147 &i2c1 {
 148         clock-frequency = <100000>;
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_i2c1>;
 151         status = "okay";
 152
 153         gsc: gsc@20 {
 154                 compatible = "gw,gsc";
 155                 reg = <0x20>;
 156                 interrupt-parent = <&gpio1>;
 157                 interrupts = <4 GPIO_ACTIVE_LOW>;
 158                 interrupt-controller;
 159                 #interrupt-cells = <1>;
 160                 #size-cells = <0>;
 161
 162                 adc {
 163                         compatible = "gw,gsc-adc";
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166
 167                         channel@0 {
 168                                 gw,mode = <0>;
 169                                 reg = <0x00>;
 170                                 label = "temp";
 171                         };
 172
 173                         channel@2 {
 174                                 gw,mode = <1>;
 175                                 reg = <0x02>;
 176                                 label = "vdd_vin";
 177                         };
 178
 179                         channel@5 {
 180                                 gw,mode = <1>;
 181                                 reg = <0x05>;
 182                                 label = "vdd_3p3";
 183                         };
 184
 185                         channel@8 {
 186                                 gw,mode = <1>;
 187                                 reg = <0x08>;
 188                                 label = "vdd_bat";
 189                         };
 190
 191                         channel@b {
 192                                 gw,mode = <1>;
 193                                 reg = <0x0b>;
 194                                 label = "vdd_5p0";
 195                         };
 196
 197                         channel@e {
 198                                 gw,mode = <1>;
 199                                 reg = <0xe>;
 200                                 label = "vdd_arm";
 201                         };
 202
 203                         channel@11 {
 204                                 gw,mode = <1>;
 205                                 reg = <0x11>;
 206                                 label = "vdd_soc";
 207                         };
 208
 209                         channel@14 {
 210                                 gw,mode = <1>;
 211                                 reg = <0x14>;
 212                                 label = "vdd_3p0";
 213                         };
 214
 215                         channel@17 {
 216                                 gw,mode = <1>;
 217                                 reg = <0x17>;
 218                                 label = "vdd_1p5";
 219                         };
 220
 221                         channel@1d {
 222                                 gw,mode = <1>;
 223                                 reg = <0x1d>;
 224                                 label = "vdd_1p8";
 225                         };
 226
 227                         channel@20 {
 228                                 gw,mode = <1>;
 229                                 reg = <0x20>;
 230                                 label = "vdd_an1";
 231                         };
 232
 233                         channel@23 {
 234                                 gw,mode = <1>;
 235                                 reg = <0x23>;
 236                                 label = "vdd_2p5";
 237                         };
 238                 };
 239         };
 240
 241         gsc_gpio: gpio@23 {
 242                 compatible = "nxp,pca9555";
 243                 reg = <0x23>;
 244                 gpio-controller;
 245                 #gpio-cells = <2>;
 246                 interrupt-parent = <&gsc>;
 247                 interrupts = <4>;
 248         };
 249
 250         eeprom1: eeprom@50 {
 251                 compatible = "atmel,24c02";
 252                 reg = <0x50>;
 253                 pagesize = <16>;
 254         };
 255
 256         eeprom2: eeprom@51 {
 257                 compatible = "atmel,24c02";
 258                 reg = <0x51>;
 259                 pagesize = <16>;
 260         };
 261
 262         eeprom3: eeprom@52 {
 263                 compatible = "atmel,24c02";
 264                 reg = <0x52>;
 265                 pagesize = <16>;
 266         };
 267
 268         eeprom4: eeprom@53 {
 269                 compatible = "atmel,24c02";
 270                 reg = <0x53>;
 271                 pagesize = <16>;
 272         };
 273
 274         rtc: ds1672@68 {
 275                 compatible = "dallas,ds1672";
 276                 reg = <0x68>;
 277         };
 278 };
 279
 280 &i2c2 {
 281         clock-frequency = <100000>;
 282         pinctrl-names = "default";
 283         pinctrl-0 = <&pinctrl_i2c2>;
 284         status = "okay";
 285
 286         ltc3676: pmic@3c {
 287                 compatible = "lltc,ltc3676";
 288                 reg = <0x3c>;
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&pinctrl_pmic>;
 291                 interrupt-parent = <&gpio1>;
 292                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 293
 294                 regulators {
 295                         /* VDD_SOC (1+R1/R2 = 1.635) */
 296                         reg_vdd_soc: sw1 {
 297                                 regulator-name = "vddsoc";
 298                                 regulator-min-microvolt = <674400>;
 299                                 regulator-max-microvolt = <1308000>;
 300                                 lltc,fb-voltage-divider = <127000 200000>;
 301                                 regulator-ramp-delay = <7000>;
 302                                 regulator-boot-on;
 303                                 regulator-always-on;
 304                         };
 305
 306                         /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
 307                         reg_1p8v: sw2 {
 308                                 regulator-name = "vdd1p8";
 309                                 regulator-min-microvolt = <1033310>;
 310                                 regulator-max-microvolt = <2004000>;
 311                                 lltc,fb-voltage-divider = <301000 200000>;
 312                                 regulator-ramp-delay = <7000>;
 313                                 regulator-boot-on;
 314                                 regulator-always-on;
 315                         };
 316
 317                         /* VDD_ARM (1+R1/R2 = 1.635) */
 318                         reg_vdd_arm: sw3 {
 319                                 regulator-name = "vddarm";
 320                                 regulator-min-microvolt = <674400>;
 321                                 regulator-max-microvolt = <1308000>;
 322                                 lltc,fb-voltage-divider = <127000 200000>;
 323                                 regulator-ramp-delay = <7000>;
 324                                 regulator-boot-on;
 325                                 regulator-always-on;
 326                         };
 327
 328                         /* VDD_DDR (1+R1/R2 = 2.105) */
 329                         reg_vdd_ddr: sw4 {
 330                                 regulator-name = "vddddr";
 331                                 regulator-min-microvolt = <868310>;
 332                                 regulator-max-microvolt = <1684000>;
 333                                 lltc,fb-voltage-divider = <221000 200000>;
 334                                 regulator-ramp-delay = <7000>;
 335                                 regulator-boot-on;
 336                                 regulator-always-on;
 337                         };
 338
 339                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 340                         reg_2p5v: ldo2 {
 341                                 regulator-name = "vdd2p5";
 342                                 regulator-min-microvolt = <2490375>;
 343                                 regulator-max-microvolt = <2490375>;
 344                                 lltc,fb-voltage-divider = <487000 200000>;
 345                                 regulator-boot-on;
 346                                 regulator-always-on;
 347                         };
 348
 349                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 350                         reg_3p0v: ldo4 {
 351                                 regulator-name = "vdd3p0";
 352                                 regulator-min-microvolt = <3023250>;
 353                                 regulator-max-microvolt = <3023250>;
 354                                 lltc,fb-voltage-divider = <634000 200000>;
 355                                 regulator-boot-on;
 356                                 regulator-always-on;
 357                         };
 358                 };
 359         };
 360 };
 361
 362 &i2c3 {
 363         clock-frequency = <100000>;
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_i2c3>;
 366         status = "okay";
 367
 368         adv7180: camera@20 {
 369                 compatible = "adi,adv7180";
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&pinctrl_adv7180>;
 372                 reg = <0x20>;
 373                 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
 374                 interrupt-parent = <&gpio5>;
 375                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 376
 377                 port {
 378                         adv7180_to_ipu1_csi0_mux: endpoint {
 379                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 380                                 bus-width = <8>;
 381                         };
 382                 };
 383         };
 384 };
 385
 386 &ipu1_csi0_from_ipu1_csi0_mux {
 387         bus-width = <8>;
 388 };
 389
 390 &ipu1_csi0_mux_from_parallel_sensor {
 391         remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
 392         bus-width = <8>;
 393 };
 394
 395 &ipu1_csi0 {
 396         pinctrl-names = "default";
 397         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 398 };
 399
 400 &pcie {
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_pcie>;
 403         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 404         status = "okay";
 405 };
 406
 407 &pwm2 {
 408         pinctrl-names = "default";
 409         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 410         status = "disabled";
 411 };
 412
 413 &pwm3 {
 414         pinctrl-names = "default";
 415         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 416         status = "disabled";
 417 };
 418
 419 &pwm4 {
 420         pinctrl-names = "default";
 421         pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 422         status = "disabled";
 423 };
 424
 425 &uart1 {
 426         pinctrl-names = "default";
 427         pinctrl-0 = <&pinctrl_uart1>;
 428         status = "okay";
 429 };
 430
 431 &uart2 {
 432         pinctrl-names = "default";
 433         pinctrl-0 = <&pinctrl_uart2>;
 434         status = "okay";
 435 };
 436
 437 &uart3 {
 438         pinctrl-names = "default";
 439         pinctrl-0 = <&pinctrl_uart3>;
 440         status = "okay";
 441 };
 442
 443 &uart5 {
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&pinctrl_uart5>;
 446         status = "okay";
 447 };
 448
 449 &usbotg {
 450         vbus-supply = <&reg_usb_otg_vbus>;
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pinctrl_usbotg>;
 453         disable-over-current;
 454         status = "okay";
 455 };
 456
 457 &usbh1 {
 458         status = "okay";
 459 };
 460
 461 &wdog1 {
 462         pinctrl-names = "default";
 463         pinctrl-0 = <&pinctrl_wdog>;
 464         fsl,ext-reset-output;
 465 };
 466
 467 &iomuxc {
 468         pinctrl_adv7180: adv7180grp {
 469                 fsl,pins = <
 470                         MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23        0x0001b0b0
 471                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x4001b0b0
 472                 >;
 473         };
 474
 475         pinctrl_enet: enetgrp {
 476                 fsl,pins = <
 477                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 478                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 479                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 480                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 481                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 482                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 483                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 484                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 485                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 486                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 487                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 488                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 489                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 490                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 491                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 492                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 493                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0 /* PHY Reset */
 494                 >;
 495         };
 496
 497         pinctrl_gpio_leds: gpioledsgrp {
 498                 fsl,pins = <
 499                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 500                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 501                 >;
 502         };
 503
 504         pinctrl_gpmi_nand: gpminandgrp {
 505                 fsl,pins = <
 506                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 507                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 508                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 509                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 510                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 511                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 512                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 513                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 514                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 515                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 516                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 517                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 518                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 519                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 520                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 521                 >;
 522         };
 523
 524         pinctrl_i2c1: i2c1grp {
 525                 fsl,pins = <
 526                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 527                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 528                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0 /* GSC_IRQ# */
 529                 >;
 530         };
 531
 532         pinctrl_i2c2: i2c2grp {
 533                 fsl,pins = <
 534                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 535                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 536                 >;
 537         };
 538
 539         pinctrl_i2c3: i2c3grp {
 540                 fsl,pins = <
 541                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 542                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 543                 >;
 544         };
 545
 546         pinctrl_ipu1_csi0: ipu1csi0grp {
 547                 fsl,pins = <
 548                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
 549                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x1b0b0
 550                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x1b0b0
 551                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x1b0b0
 552                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x1b0b0
 553                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x1b0b0
 554                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x1b0b0
 555                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x1b0b0
 556                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x1b0b0
 557                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x1b0b0
 558                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x1b0b0
 559                 >;
 560         };
 561
 562         pinctrl_pcie: pciegrp {
 563                 fsl,pins = <
 564                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 565                 >;
 566         };
 567
 568         pinctrl_pmic: pmicgrp {
 569                 fsl,pins = <
 570                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 571                 >;
 572         };
 573
 574         pinctrl_pps: ppsgrp {
 575                 fsl,pins = <
 576                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 577                 >;
 578         };
 579
 580         pinctrl_pwm2: pwm2grp {
 581                 fsl,pins = <
 582                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 583                 >;
 584         };
 585
 586         pinctrl_pwm3: pwm3grp {
 587                 fsl,pins = <
 588                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 589                 >;
 590         };
 591
 592         pinctrl_pwm4: pwm4grp {
 593                 fsl,pins = <
 594                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 595                 >;
 596         };
 597
 598         pinctrl_uart1: uart1grp {
 599                 fsl,pins = <
 600                         MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 601                         MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 602                 >;
 603         };
 604
 605         pinctrl_uart2: uart2grp {
 606                 fsl,pins = <
 607                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 608                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 609                 >;
 610         };
 611
 612         pinctrl_uart3: uart3grp {
 613                 fsl,pins = <
 614                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 615                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 616                 >;
 617         };
 618
 619         pinctrl_uart5: uart5grp {
 620                 fsl,pins = <
 621                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 622                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 623                 >;
 624         };
 625
 626         pinctrl_usbotg: usbotggrp {
 627                 fsl,pins = <
 628                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 629                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* OTG_PWR_EN */
 630                 >;
 631         };
 632
 633         pinctrl_wdog: wdoggrp {
 634                 fsl,pins = <
 635                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 636                 >;
 637         };
 638 };