arch/arm/boot/dts/imx6qdl-colibri.dtsi

   1 /*
   2  * Copyright 2014-2016 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Colibri iMX6DL/S Module";
  48         compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
  49
  50         backlight: backlight {
  51                 compatible = "pwm-backlight";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  54                 pwms = <&pwm3 0 5000000>;
  55                 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
  56                 status = "disabled";
  57         };
  58
  59         reg_module_3v3: regulator-module-3v3 {
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "+V3.3";
  62                 regulator-min-microvolt = <3300000>;
  63                 regulator-max-microvolt = <3300000>;
  64                 regulator-always-on;
  65         };
  66
  67         reg_module_3v3_audio: regulator-module-3v3-audio {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "+V3.3_AUDIO";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72                 regulator-always-on;
  73         };
  74
  75         reg_usb_host_vbus: regulator-usb-host-vbus {
  76                 compatible = "regulator-fixed";
  77                 pinctrl-names = "default";
  78                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
  79                 regulator-name = "usb_host_vbus";
  80                 regulator-min-microvolt = <5000000>;
  81                 regulator-max-microvolt = <5000000>;
  82                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
  83                 status = "disabled";
  84         };
  85
  86         sound {
  87                 compatible = "fsl,imx-audio-sgtl5000";
  88                 model = "imx6dl-colibri-sgtl5000";
  89                 ssi-controller = <&ssi1>;
  90                 audio-codec = <&codec>;
  91                 audio-routing =
  92                         "Headphone Jack", "HP_OUT",
  93                         "LINE_IN", "Line In Jack",
  94                         "MIC_IN", "Mic Jack",
  95                         "Mic Jack", "Mic Bias";
  96                 mux-int-port = <1>;
  97                 mux-ext-port = <5>;
  98         };
  99
 100         /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
 101         sound_spdif: sound-spdif {
 102                 compatible = "fsl,imx-audio-spdif";
 103                 model = "imx-spdif";
 104                 spdif-controller = <&spdif>;
 105                 spdif-in;
 106                 spdif-out;
 107                 status = "disabled";
 108         };
 109 };
 110
 111 &audmux {
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
 114         status = "okay";
 115 };
 116
 117 /* Optional on SODIMM 55/63 */
 118 &can1 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_flexcan1>;
 121         status = "disabled";
 122 };
 123
 124 /* Optional on SODIMM 178/188 */
 125 &can2 {
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_flexcan2>;
 128         status = "disabled";
 129 };
 130
 131 /* Colibri SSP */
 132 &ecspi4 {
 133         cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_ecspi4>;
 136         status = "disabled";
 137 };
 138
 139 &fec {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_enet>;
 142         phy-mode = "rmii";
 143         phy-handle = <&ethphy>;
 144         status = "okay";
 145
 146         mdio {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149
 150                 ethphy: ethernet-phy@0 {
 151                         reg = <0>;
 152                         micrel,led-mode = <0>;
 153                 };
 154         };
 155 };
 156
 157 &hdmi {
 158         pinctrl-names = "default";
 159         pinctrl-0 = <&pinctrl_hdmi_ddc>;
 160         status = "disabled";
 161 };
 162
 163 /*
 164  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 165  * touch screen controller
 166  */
 167 &i2c2 {
 168         clock-frequency = <100000>;
 169         pinctrl-names = "default", "gpio";
 170         pinctrl-0 = <&pinctrl_i2c2>;
 171         pinctrl-0 = <&pinctrl_i2c2_gpio>;
 172         scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 173         sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 174         status = "okay";
 175
 176         pmic: pfuze100@8 {
 177                 compatible = "fsl,pfuze100";
 178                 reg = <0x08>;
 179
 180                 regulators {
 181                         sw1a_reg: sw1ab {
 182                                 regulator-min-microvolt = <300000>;
 183                                 regulator-max-microvolt = <1875000>;
 184                                 regulator-boot-on;
 185                                 regulator-always-on;
 186                                 regulator-ramp-delay = <6250>;
 187                         };
 188
 189                         sw1c_reg: sw1c {
 190                                 regulator-min-microvolt = <300000>;
 191                                 regulator-max-microvolt = <1875000>;
 192                                 regulator-boot-on;
 193                                 regulator-always-on;
 194                                 regulator-ramp-delay = <6250>;
 195                         };
 196
 197                         sw3a_reg: sw3a {
 198                                 regulator-min-microvolt = <400000>;
 199                                 regulator-max-microvolt = <1975000>;
 200                                 regulator-boot-on;
 201                                 regulator-always-on;
 202                         };
 203
 204                         swbst_reg: swbst {
 205                                 regulator-min-microvolt = <5000000>;
 206                                 regulator-max-microvolt = <5150000>;
 207                                 regulator-boot-on;
 208                                 regulator-always-on;
 209                         };
 210
 211                         snvs_reg: vsnvs {
 212                                 regulator-min-microvolt = <1000000>;
 213                                 regulator-max-microvolt = <3000000>;
 214                                 regulator-boot-on;
 215                                 regulator-always-on;
 216                         };
 217
 218                         vref_reg: vrefddr {
 219                                 regulator-boot-on;
 220                                 regulator-always-on;
 221                         };
 222
 223                         /* vgen1: unused */
 224
 225                         vgen2_reg: vgen2 {
 226                                 regulator-min-microvolt = <800000>;
 227                                 regulator-max-microvolt = <1550000>;
 228                                 regulator-boot-on;
 229                                 regulator-always-on;
 230                         };
 231
 232                         /* vgen3: unused */
 233
 234                         vgen4_reg: vgen4 {
 235                                 regulator-min-microvolt = <1800000>;
 236                                 regulator-max-microvolt = <1800000>;
 237                                 regulator-boot-on;
 238                                 regulator-always-on;
 239                         };
 240
 241                         vgen5_reg: vgen5 {
 242                                 regulator-min-microvolt = <1800000>;
 243                                 regulator-max-microvolt = <3300000>;
 244                                 regulator-boot-on;
 245                                 regulator-always-on;
 246                         };
 247
 248                         vgen6_reg: vgen6 {
 249                                 regulator-min-microvolt = <1800000>;
 250                                 regulator-max-microvolt = <3300000>;
 251                                 regulator-boot-on;
 252                                 regulator-always-on;
 253                         };
 254                 };
 255         };
 256
 257         codec: sgtl5000@a {
 258                 compatible = "fsl,sgtl5000";
 259                 reg = <0x0a>;
 260                 clocks = <&clks IMX6QDL_CLK_CKO>;
 261                 VDDA-supply = <&reg_module_3v3_audio>;
 262                 VDDIO-supply = <&reg_module_3v3>;
 263                 VDDD-supply = <&vgen4_reg>;
 264                 lrclk-strength = <3>;
 265         };
 266
 267         /* STMPE811 touch screen controller */
 268         stmpe811@41 {
 269                 compatible = "st,stmpe811";
 270                 pinctrl-names = "default";
 271                 pinctrl-0 = <&pinctrl_touch_int>;
 272                 reg = <0x41>;
 273                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 274                 interrupt-parent = <&gpio6>;
 275                 interrupt-controller;
 276                 id = <0>;
 277                 blocks = <0x5>;
 278                 irq-trigger = <0x1>;
 279                 /* 3.25 MHz ADC clock speed */
 280                 st,adc-freq = <1>;
 281                 /* 12-bit ADC */
 282                 st,mod-12b = <1>;
 283                 /* internal ADC reference */
 284                 st,ref-sel = <0>;
 285                 /* ADC converstion time: 80 clocks */
 286                 st,sample-time = <4>;
 287
 288                 stmpe_touchscreen {
 289                         compatible = "st,stmpe-ts";
 290                         /* 8 sample average control */
 291                         st,ave-ctrl = <3>;
 292                         /* 7 length fractional part in z */
 293                         st,fraction-z = <7>;
 294                         /*
 295                          * 50 mA typical 80 mA max touchscreen drivers
 296                          * current limit value
 297                          */
 298                         st,i-drive = <1>;
 299                         /* 1 ms panel driver settling time */
 300                         st,settling = <3>;
 301                         /* 5 ms touch detect interrupt delay */
 302                         st,touch-det-delay = <5>;
 303                 };
 304
 305                 stmpe_adc {
 306                         compatible = "st,stmpe-adc";
 307                         /* forbid to use ADC channels 3-0 (touch) */
 308                         st,norequest-mask = <0x0F>;
 309                 };
 310         };
 311 };
 312
 313 /*
 314  * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
 315  */
 316 &i2c3 {
 317         clock-frequency = <100000>;
 318         pinctrl-names = "default", "gpio";
 319         pinctrl-0 = <&pinctrl_i2c3>;
 320         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 321         scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 322         sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 323         status = "disabled";
 324 };
 325
 326 /* Colibri PWM<B> */
 327 &pwm1 {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_pwm1>;
 330         status = "disabled";
 331 };
 332
 333 /* Colibri PWM<D> */
 334 &pwm2 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pinctrl_pwm2>;
 337         status = "disabled";
 338 };
 339
 340 /* Colibri PWM<A> */
 341 &pwm3 {
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pinctrl_pwm3>;
 344         status = "disabled";
 345 };
 346
 347 /* Colibri PWM<C> */
 348 &pwm4 {
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&pinctrl_pwm4>;
 351         status = "disabled";
 352 };
 353
 354 /* Optional S/PDIF out on SODIMM 137 */
 355 &spdif {
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&pinctrl_spdif>;
 358         status = "disabled";
 359 };
 360
 361 &ssi1 {
 362         status = "okay";
 363 };
 364
 365 /* Colibri UART_A */
 366 &uart1 {
 367         pinctrl-names = "default";
 368         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 369         fsl,dte-mode;
 370         uart-has-rtscts;
 371         status = "disabled";
 372 };
 373
 374 /* Colibri UART_B */
 375 &uart2 {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_uart2_dte>;
 378         fsl,dte-mode;
 379         uart-has-rtscts;
 380         status = "disabled";
 381 };
 382
 383 /* Colibri UART_C */
 384 &uart3 {
 385         pinctrl-names = "default";
 386         pinctrl-0 = <&pinctrl_uart3_dte>;
 387         fsl,dte-mode;
 388         status = "disabled";
 389 };
 390
 391 &usbotg {
 392         pinctrl-names = "default";
 393         disable-over-current;
 394         dr_mode = "peripheral";
 395         status = "disabled";
 396 };
 397
 398 /* Colibri MMC */
 399 &usdhc1 {
 400         pinctrl-names = "default";
 401         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
 402         cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
 403         disable-wp;
 404         vqmmc-supply = <&reg_module_3v3>;
 405         bus-width = <4>;
 406         no-1-8-v;
 407         status = "disabled";
 408 };
 409
 410 /* eMMC */
 411 &usdhc3 {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_usdhc3>;
 414         vqmmc-supply = <&reg_module_3v3>;
 415         bus-width = <8>;
 416         no-1-8-v;
 417         non-removable;
 418         status = "okay";
 419 };
 420
 421 &weim {
 422         pinctrl-names = "default";
 423         pinctrl-0 = <&pinctrl_weim_sram  &pinctrl_weim_cs0
 424                      &pinctrl_weim_cs1   &pinctrl_weim_cs2
 425                      &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
 426         #address-cells = <2>;
 427         #size-cells = <1>;
 428         status = "disabled";
 429 };
 430
 431 &iomuxc {
 432         pinctrl-names = "default";
 433         pinctrl-0 = <&pinctrl_usbh_oc_1>;
 434
 435         pinctrl_audmux: audmuxgrp {
 436                 fsl,pins = <
 437                         MX6QDL_PAD_KEY_COL0__AUD5_TXC   0x130b0
 438                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD   0x130b0
 439                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS  0x130b0
 440                         MX6QDL_PAD_KEY_ROW1__AUD5_RXD   0x130b0
 441                         /* SGTL5000 sys_mclk */
 442                         MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x000b0
 443                 >;
 444         };
 445
 446         pinctrl_cam_mclk: cammclkgrp {
 447                 fsl,pins = <
 448                         /* Parallel Camera CAM sys_mclk */
 449                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 450                 >;
 451         };
 452
 453         pinctrl_ecspi4: ecspi4grp {
 454                 fsl,pins = <
 455                         MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
 456                         MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
 457                         MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
 458                         /* SPI CS */
 459                         MX6QDL_PAD_EIM_A25__GPIO5_IO02  0x000b1
 460                 >;
 461         };
 462
 463         pinctrl_enet: enetgrp {
 464                 fsl,pins = <
 465                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 466                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 467                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 468                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 469                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x1b0b0
 470                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 471                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 472                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 473                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 474                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK     ((1<<30) | 0x1b0b0)
 475                 >;
 476         };
 477
 478         pinctrl_flexcan1: flexcan1grp {
 479                 fsl,pins = <
 480                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x1b0b0
 481                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x1b0b0
 482                 >;
 483         };
 484
 485         pinctrl_flexcan2: flexcan2grp {
 486                 fsl,pins = <
 487                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 488                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 489                 >;
 490         };
 491
 492         pinctrl_gpio_bl_on: gpioblon {
 493                 fsl,pins = <
 494                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x1b0b0
 495                 >;
 496         };
 497
 498         pinctrl_gpio_keys: gpiokeys {
 499                 fsl,pins = <
 500                         MX6QDL_PAD_EIM_A16__GPIO2_IO22          0x130b0
 501                 >;
 502         };
 503
 504         pinctrl_hdmi_ddc: hdmiddcgrp {
 505                 fsl,pins = <
 506                         MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
 507                         MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 508                 >;
 509         };
 510
 511         pinctrl_i2c2: i2c2grp {
 512                 fsl,pins = <
 513                         MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
 514                         MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
 515                 >;
 516         };
 517
 518         pinctrl_i2c2_gpio: i2c2grp {
 519                 fsl,pins = <
 520                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
 521                         MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
 522                 >;
 523         };
 524
 525         pinctrl_i2c3: i2c3grp {
 526                 fsl,pins = <
 527                         MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
 528                         MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
 529                 >;
 530         };
 531
 532         pinctrl_i2c3_gpio: i2c3gpiogrp {
 533                 fsl,pins = <
 534                         MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
 535                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
 536                 >;
 537         };
 538
 539         pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
 540                 fsl,pins = <
 541                         MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12    0xb0b1
 542                         MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13    0xb0b1
 543                         MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14    0xb0b1
 544                         MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15    0xb0b1
 545                         MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16    0xb0b1
 546                         MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17    0xb0b1
 547                         MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18    0xb0b1
 548                         MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19    0xb0b1
 549                         MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK    0xb0b1
 550                         MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC     0xb0b1
 551                         MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC     0xb0b1
 552                         /* Disable PWM pins on camera interface */
 553                         MX6QDL_PAD_SD4_DAT1__GPIO2_IO09         0x40
 554                         MX6QDL_PAD_GPIO_1__GPIO1_IO01           0x40
 555                 >;
 556         };
 557
 558         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 559                 fsl,pins = <
 560                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0xa1
 561                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0xa1
 562                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0xa1
 563                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0xa1
 564                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0xa1
 565                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0xa1
 566                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0xa1
 567                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0xa1
 568                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0xa1
 569                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0xa1
 570                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0xa1
 571                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0xa1
 572                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0xa1
 573                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0xa1
 574                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0xa1
 575                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0xa1
 576                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0xa1
 577                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0xa1
 578                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0xa1
 579                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0xa1
 580                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0xa1
 581                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0xa1
 582                 >;
 583         };
 584
 585         pinctrl_mic_gnd: gpiomicgnd {
 586                 fsl,pins = <
 587                         /* Controls Mic GND, PU or '1' pull Mic GND to GND */
 588                         MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
 589                 >;
 590         };
 591
 592         pinctrl_mmc_cd: gpiommccd {
 593                 fsl,pins = <
 594                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
 595                 >;
 596         };
 597
 598         pinctrl_pwm1: pwm1grp {
 599                 fsl,pins = <
 600                         MX6QDL_PAD_GPIO_9__PWM1_OUT     0x1b0b1
 601                 >;
 602         };
 603
 604         pinctrl_pwm2: pwm2grp {
 605                 fsl,pins = <
 606                         MX6QDL_PAD_GPIO_1__PWM2_OUT     0x1b0b1
 607                         MX6QDL_PAD_EIM_A21__GPIO2_IO17  0x00040
 608                 >;
 609         };
 610
 611         pinctrl_pwm3: pwm3grp {
 612                 fsl,pins = <
 613                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT   0x1b0b1
 614                         MX6QDL_PAD_EIM_A22__GPIO2_IO16  0x00040
 615                 >;
 616         };
 617
 618         pinctrl_pwm4: pwm4grp {
 619                 fsl,pins = <
 620                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT   0x1b0b1
 621                 >;
 622         };
 623
 624         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 625                 fsl,pins = <
 626                         /* USBH_EN */
 627                         MX6QDL_PAD_EIM_D31__GPIO3_IO31  0x0f058
 628                 >;
 629         };
 630
 631         pinctrl_usbh_oc_1: usbhoc1grp {
 632                 fsl,pins = <
 633                         /* USBH_OC */
 634                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x1b0b0
 635                 >;
 636         };
 637
 638         pinctrl_spdif: spdifgrp {
 639                 fsl,pins = <
 640                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 641                 >;
 642         };
 643
 644         pinctrl_touch_int: gpiotouchintgrp {
 645                 fsl,pins = <
 646                         /* STMPE811 interrupt */
 647                         MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
 648                 >;
 649         };
 650
 651         pinctrl_uart1_dce: uart1dcegrp {
 652                 fsl,pins = <
 653                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 654                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 655                 >;
 656         };
 657
 658         /* DTE mode */
 659         pinctrl_uart1_dte: uart1dtegrp {
 660                 fsl,pins = <
 661                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 662                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 663                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 664                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 665                 >;
 666         };
 667
 668         /* Additional DTR, DSR, DCD */
 669         pinctrl_uart1_ctrl: uart1ctrlgrp {
 670                 fsl,pins = <
 671                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 672                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 673                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 674                 >;
 675         };
 676
 677         pinctrl_uart2_dte: uart2dtegrp {
 678                 fsl,pins = <
 679                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 680                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 681                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 682                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 683                 >;
 684         };
 685
 686         pinctrl_uart3_dte: uart3dtegrp {
 687                 fsl,pins = <
 688                         MX6QDL_PAD_SD4_CLK__UART3_TX_DATA       0x1b0b1
 689                         MX6QDL_PAD_SD4_CMD__UART3_RX_DATA       0x1b0b1
 690                 >;
 691         };
 692
 693         pinctrl_usbc_det: usbcdetgrp {
 694                 fsl,pins = <
 695                         /* USBC_DET */
 696                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 697                         /* USBC_DET_EN */
 698                         MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26     0x0f058
 699                         /* USBC_DET_OVERWRITE */
 700                         MX6QDL_PAD_RGMII_RXC__GPIO6_IO30        0x0f058
 701                 >;
 702         };
 703
 704         pinctrl_usbc_id_1: usbc_id-1 {
 705                 fsl,pins = <
 706                         /* USBC_ID */
 707                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x1b0b0
 708                 >;
 709         };
 710
 711         pinctrl_usdhc1: usdhc1grp {
 712                 fsl,pins = <
 713                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17071
 714                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10071
 715                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17071
 716                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17071
 717                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17071
 718                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17071
 719                 >;
 720         };
 721
 722         pinctrl_usdhc3: usdhc3grp {
 723                 fsl,pins = <
 724                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 725                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 726                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 727                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 728                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 729                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 730                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 731                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 732                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 733                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 734                         /* eMMC reset */
 735                         MX6QDL_PAD_SD3_RST__SD3_RESET   0x17059
 736                 >;
 737         };
 738
 739         pinctrl_weim_cs0: weimcs0grp {
 740                 fsl,pins = <
 741                         /* nEXT_CS0 */
 742                         MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
 743                 >;
 744         };
 745
 746         pinctrl_weim_cs1: weimcs1grp {
 747                 fsl,pins = <
 748                         /* nEXT_CS1 */
 749                         MX6QDL_PAD_EIM_CS1__EIM_CS1_B   0xb0b1
 750                 >;
 751         };
 752
 753         pinctrl_weim_cs2: weimcs2grp {
 754                 fsl,pins = <
 755                         /* nEXT_CS2 */
 756                         MX6QDL_PAD_SD2_DAT1__EIM_CS2_B  0xb0b1
 757                 >;
 758         };
 759
 760         pinctrl_weim_sram: weimsramgrp {
 761                 fsl,pins = <
 762                         MX6QDL_PAD_EIM_OE__EIM_OE_B             0xb0b1
 763                         MX6QDL_PAD_EIM_RW__EIM_RW               0xb0b1
 764                         /* Data */
 765                         MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00     0x1b0b0
 766                         MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01       0x1b0b0
 767                         MX6QDL_PAD_CSI0_DAT4__EIM_DATA02        0x1b0b0
 768                         MX6QDL_PAD_CSI0_DAT5__EIM_DATA03        0x1b0b0
 769                         MX6QDL_PAD_CSI0_DAT6__EIM_DATA04        0x1b0b0
 770                         MX6QDL_PAD_CSI0_DAT7__EIM_DATA05        0x1b0b0
 771                         MX6QDL_PAD_CSI0_DAT8__EIM_DATA06        0x1b0b0
 772                         MX6QDL_PAD_CSI0_DAT9__EIM_DATA07        0x1b0b0
 773                         MX6QDL_PAD_CSI0_DAT12__EIM_DATA08       0x1b0b0
 774                         MX6QDL_PAD_CSI0_DAT13__EIM_DATA09       0x1b0b0
 775                         MX6QDL_PAD_CSI0_DAT14__EIM_DATA10       0x1b0b0
 776                         MX6QDL_PAD_CSI0_DAT15__EIM_DATA11       0x1b0b0
 777                         MX6QDL_PAD_CSI0_DAT16__EIM_DATA12       0x1b0b0
 778                         MX6QDL_PAD_CSI0_DAT17__EIM_DATA13       0x1b0b0
 779                         MX6QDL_PAD_CSI0_DAT18__EIM_DATA14       0x1b0b0
 780                         MX6QDL_PAD_CSI0_DAT19__EIM_DATA15       0x1b0b0
 781                         /* Address */
 782                         MX6QDL_PAD_EIM_DA15__EIM_AD15           0xb0b1
 783                         MX6QDL_PAD_EIM_DA14__EIM_AD14           0xb0b1
 784                         MX6QDL_PAD_EIM_DA13__EIM_AD13           0xb0b1
 785                         MX6QDL_PAD_EIM_DA12__EIM_AD12           0xb0b1
 786                         MX6QDL_PAD_EIM_DA11__EIM_AD11           0xb0b1
 787                         MX6QDL_PAD_EIM_DA10__EIM_AD10           0xb0b1
 788                         MX6QDL_PAD_EIM_DA9__EIM_AD09            0xb0b1
 789                         MX6QDL_PAD_EIM_DA8__EIM_AD08            0xb0b1
 790                         MX6QDL_PAD_EIM_DA7__EIM_AD07            0xb0b1
 791                         MX6QDL_PAD_EIM_DA6__EIM_AD06            0xb0b1
 792                         MX6QDL_PAD_EIM_DA5__EIM_AD05            0xb0b1
 793                         MX6QDL_PAD_EIM_DA4__EIM_AD04            0xb0b1
 794                         MX6QDL_PAD_EIM_DA3__EIM_AD03            0xb0b1
 795                         MX6QDL_PAD_EIM_DA2__EIM_AD02            0xb0b1
 796                         MX6QDL_PAD_EIM_DA1__EIM_AD01            0xb0b1
 797                         MX6QDL_PAD_EIM_DA0__EIM_AD00            0xb0b1
 798                 >;
 799         };
 800
 801         pinctrl_weim_rdnwr: weimrdnwr {
 802                 fsl,pins = <
 803                         MX6QDL_PAD_SD2_CLK__GPIO1_IO10          0x0040
 804                         MX6QDL_PAD_RGMII_TD3__GPIO6_IO23        0x130b0
 805                 >;
 806         };
 807
 808         pinctrl_weim_npwe: weimnpwe {
 809                 fsl,pins = <
 810                         MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x0040
 811                         MX6QDL_PAD_RGMII_TD2__GPIO6_IO22        0x130b0
 812                 >;
 813         };
 814
 815         /* ADDRESS[16:18] [25] used as GPIO */
 816         pinctrl_weim_gpio_1: weimgpio-1 {
 817                 fsl,pins = <
 818                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 819                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 820                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 821                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 822                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x1b0b0
 823                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b0
 824                         MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 825                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 826                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x1b0b0
 827                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 828                 >;
 829         };
 830
 831         /* ADDRESS[19:24] used as GPIO */
 832         pinctrl_weim_gpio_2: weimgpio-2 {
 833                 fsl,pins = <
 834                         MX6QDL_PAD_KEY_ROW2__GPIO4_IO11         0x1b0b0
 835                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 836                         MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x1b0b0
 837                         MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16      0x1b0b0
 838                         MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15      0x1b0b0
 839                         MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14      0x1b0b0
 840                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
 841                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x1b0b0
 842                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x1b0b0
 843                 >;
 844         };
 845
 846         /* DATA[16:31] used as GPIO */
 847         pinctrl_weim_gpio_3: weimgpio-3 {
 848                 fsl,pins = <
 849                         MX6QDL_PAD_EIM_LBA__GPIO2_IO27          0x1b0b0
 850                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0x1b0b0
 851                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x1b0b0
 852                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x1b0b0
 853                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x1b0b0
 854                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x1b0b0
 855                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x1b0b0
 856                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x1b0b0
 857                         MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x1b0b0
 858                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 859                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x1b0b0
 860                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x1b0b0
 861                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0
 862                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x1b0b0
 863                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 864                 >;
 865         };
 866
 867         /* DQM[0:3] used as GPIO */
 868         pinctrl_weim_gpio_4: weimgpio-4 {
 869                 fsl,pins = <
 870                         MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0x1b0b0
 871                         MX6QDL_PAD_EIM_EB1__GPIO2_IO29          0x1b0b0
 872                         MX6QDL_PAD_SD2_DAT2__GPIO1_IO13         0x1b0b0
 873                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x1b0b0
 874                 >;
 875         };
 876
 877         /* RDY used as GPIO */
 878         pinctrl_weim_gpio_5: weimgpio-5 {
 879                 fsl,pins = <
 880                         MX6QDL_PAD_EIM_WAIT__GPIO5_IO00         0x1b0b0
 881                 >;
 882         };
 883
 884         /* ADDRESS[16] DATA[30] used as GPIO */
 885         pinctrl_weim_gpio_6: weimgpio-6 {
 886                 fsl,pins = <
 887                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 888                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0
 889                 >;
 890         };
 891 };