1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2014-2020 Toradex
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
8 #include <dt-bindings/gpio/gpio.h>
11 model = "Toradex Colibri iMX6DL/S Module";
12 compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
14 backlight: backlight {
15 compatible = "pwm-backlight";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_bl_on>;
18 pwms = <&pwm3 0 5000000>;
19 enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
23 reg_module_3v3: regulator-module-3v3 {
24 compatible = "regulator-fixed";
25 regulator-name = "+V3.3";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
31 reg_module_3v3_audio: regulator-module-3v3-audio {
32 compatible = "regulator-fixed";
33 regulator-name = "+V3.3_AUDIO";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
39 reg_usb_host_vbus: regulator-usb-host-vbus {
40 compatible = "regulator-fixed";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
43 regulator-name = "usb_host_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */
51 compatible = "fsl,imx-audio-sgtl5000";
52 model = "imx6dl-colibri-sgtl5000";
53 ssi-controller = <&ssi1>;
54 audio-codec = <&codec>;
56 "Headphone Jack", "HP_OUT",
57 "LINE_IN", "Line In Jack",
59 "Mic Jack", "Mic Bias";
64 /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */
65 sound_spdif: sound-spdif {
66 compatible = "fsl,imx-audio-spdif";
68 spdif-controller = <&spdif>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_audmux &pinctrl_mic_gnd>;
81 /* Optional on SODIMM 55/63 */
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_flexcan1>;
88 /* Optional on SODIMM 178/188 */
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_flexcan2>;
97 cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_ecspi4>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_enet>;
107 phy-handle = <ðphy>;
111 #address-cells = <1>;
114 ethphy: ethernet-phy@0 {
116 micrel,led-mode = <0>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_hdmi_ddc>;
128 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
129 * touch screen controller
132 clock-frequency = <100000>;
133 pinctrl-names = "default", "gpio";
134 pinctrl-0 = <&pinctrl_i2c2>;
135 pinctrl-0 = <&pinctrl_i2c2_gpio>;
136 scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
137 sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
141 compatible = "fsl,pfuze100";
146 regulator-min-microvolt = <300000>;
147 regulator-max-microvolt = <1875000>;
150 regulator-ramp-delay = <6250>;
154 regulator-min-microvolt = <300000>;
155 regulator-max-microvolt = <1875000>;
158 regulator-ramp-delay = <6250>;
162 regulator-min-microvolt = <400000>;
163 regulator-max-microvolt = <1975000>;
169 regulator-min-microvolt = <5000000>;
170 regulator-max-microvolt = <5150000>;
176 regulator-min-microvolt = <1000000>;
177 regulator-max-microvolt = <3000000>;
190 regulator-min-microvolt = <800000>;
191 regulator-max-microvolt = <1550000>;
197 * +V3.3_1.8_SD1 coming off VGEN3 and supplying
198 * the i.MX 6 NVCC_SD1.
201 regulator-min-microvolt = <1800000>;
202 regulator-max-microvolt = <3300000>;
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <1800000>;
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <3300000>;
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <3300000>;
231 compatible = "fsl,sgtl5000";
233 clocks = <&clks IMX6QDL_CLK_CKO>;
234 VDDA-supply = <®_module_3v3_audio>;
235 VDDIO-supply = <®_module_3v3>;
236 VDDD-supply = <&vgen4_reg>;
237 lrclk-strength = <3>;
240 /* STMPE811 touch screen controller */
242 compatible = "st,stmpe811";
243 pinctrl-names = "default";
244 pinctrl-0 = <&pinctrl_touch_int>;
246 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
247 interrupt-parent = <&gpio6>;
248 interrupt-controller;
252 /* 3.25 MHz ADC clock speed */
256 /* internal ADC reference */
258 /* ADC converstion time: 80 clocks */
259 st,sample-time = <4>;
262 compatible = "st,stmpe-ts";
263 /* 8 sample average control */
265 /* 7 length fractional part in z */
268 * 50 mA typical 80 mA max touchscreen drivers
269 * current limit value
272 /* 1 ms panel driver settling time */
274 /* 5 ms touch detect interrupt delay */
275 st,touch-det-delay = <5>;
279 compatible = "st,stmpe-adc";
280 /* forbid to use ADC channels 3-0 (touch) */
281 st,norequest-mask = <0x0F>;
287 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
290 clock-frequency = <100000>;
291 pinctrl-names = "default", "gpio";
292 pinctrl-0 = <&pinctrl_i2c3>;
293 pinctrl-1 = <&pinctrl_i2c3_gpio>;
294 scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
295 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_pwm1>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_pwm2>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_pwm3>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_pwm4>;
328 /* Optional S/PDIF out on SODIMM 137 */
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_spdif>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_uart2_dte>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_uart3_dte>;
366 disable-over-current;
367 dr_mode = "peripheral";
373 pinctrl-names = "default";
374 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
375 cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */
377 vqmmc-supply = <®_module_3v3>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_usdhc3>;
387 vqmmc-supply = <®_module_3v3>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_weim_sram &pinctrl_weim_cs0
397 &pinctrl_weim_cs1 &pinctrl_weim_cs2
398 &pinctrl_weim_rdnwr &pinctrl_weim_npwe>;
399 #address-cells = <2>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_usbh_oc_1>;
408 pinctrl_audmux: audmuxgrp {
410 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
411 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
412 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
413 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
414 /* SGTL5000 sys_mclk */
415 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0
419 pinctrl_cam_mclk: cammclkgrp {
421 /* Parallel Camera CAM sys_mclk */
422 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
426 pinctrl_ecspi4: ecspi4grp {
428 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
429 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
430 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
432 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1
436 pinctrl_enet: enetgrp {
438 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
439 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
440 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
441 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
442 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
443 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
444 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
445 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
446 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
447 MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
451 pinctrl_flexcan1: flexcan1grp {
453 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
454 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
458 pinctrl_flexcan2: flexcan2grp {
460 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
461 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
465 pinctrl_gpio_bl_on: gpioblon {
467 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0
471 pinctrl_gpio_keys: gpiokeys {
473 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0
477 pinctrl_hdmi_ddc: hdmiddcgrp {
479 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
480 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
484 pinctrl_i2c2: i2c2grp {
486 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
487 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
491 pinctrl_i2c2_gpio: i2c2grp {
493 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
494 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
498 pinctrl_i2c3: i2c3grp {
500 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
501 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
505 pinctrl_i2c3_gpio: i2c3gpiogrp {
507 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
508 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
512 pinctrl_ipu1_csi0: ipu1csi0grp { /* Parallel Camera */
514 MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
515 MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
516 MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
517 MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
518 MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
519 MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
520 MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
521 MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
522 MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
523 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
524 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
525 /* Disable PWM pins on camera interface */
526 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40
527 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
531 pinctrl_ipu1_lcdif: ipu1lcdifgrp {
533 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
534 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
535 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
536 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
537 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
538 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
539 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
540 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
541 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
542 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
543 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
544 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
545 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
546 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
547 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
548 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
549 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
550 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
551 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
552 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
553 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
554 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
558 pinctrl_mic_gnd: gpiomicgnd {
560 /* Controls Mic GND, PU or '1' pull Mic GND to GND */
561 MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0
565 pinctrl_mmc_cd: gpiommccd {
567 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1
571 pinctrl_pwm1: pwm1grp {
573 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
577 pinctrl_pwm2: pwm2grp {
579 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
580 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040
584 pinctrl_pwm3: pwm3grp {
586 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
587 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040
591 pinctrl_pwm4: pwm4grp {
593 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
597 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
600 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058
604 pinctrl_usbh_oc_1: usbhoc1grp {
607 MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0
611 pinctrl_spdif: spdifgrp {
613 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
617 pinctrl_touch_int: gpiotouchintgrp {
619 /* STMPE811 interrupt */
620 MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x1b0b0
624 pinctrl_uart1_dce: uart1dcegrp {
626 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
627 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
632 pinctrl_uart1_dte: uart1dtegrp {
634 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
635 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
636 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
637 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
641 /* Additional DTR, DSR, DCD */
642 pinctrl_uart1_ctrl: uart1ctrlgrp {
644 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
645 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
646 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
650 pinctrl_uart2_dte: uart2dtegrp {
652 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
653 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
654 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
655 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
659 pinctrl_uart3_dte: uart3dtegrp {
661 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
662 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
666 pinctrl_usbc_det: usbcdetgrp {
669 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
671 MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058
672 /* USBC_DET_OVERWRITE */
673 MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058
677 pinctrl_usbc_id_1: usbc_id-1 {
680 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
684 pinctrl_usdhc1: usdhc1grp {
686 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
687 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
688 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
689 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
690 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
691 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
695 pinctrl_usdhc3: usdhc3grp {
697 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
698 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
699 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
700 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
701 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
702 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
703 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
704 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
705 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
706 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
708 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
712 pinctrl_weim_cs0: weimcs0grp {
715 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
719 pinctrl_weim_cs1: weimcs1grp {
722 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
726 pinctrl_weim_cs2: weimcs2grp {
729 MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1
733 pinctrl_weim_sram: weimsramgrp {
735 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
736 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
738 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
739 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
740 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
741 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
742 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
743 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
744 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
745 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
746 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
747 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
748 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
749 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
750 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
751 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
752 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
753 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
755 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
756 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
757 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
758 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
759 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
760 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
761 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
762 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
763 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
764 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
765 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
766 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
767 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
768 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
769 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
770 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
774 pinctrl_weim_rdnwr: weimrdnwr {
776 MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040
777 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0
781 pinctrl_weim_npwe: weimnpwe {
783 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040
784 MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0
788 /* ADDRESS[16:18] [25] used as GPIO */
789 pinctrl_weim_gpio_1: weimgpio-1 {
791 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
792 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
793 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
794 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
795 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
796 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
797 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
798 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
799 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
800 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
804 /* ADDRESS[19:24] used as GPIO */
805 pinctrl_weim_gpio_2: weimgpio-2 {
807 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
808 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
809 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
810 MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0
811 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0
812 MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
813 MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0
814 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0
815 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
819 /* DATA[16:31] used as GPIO */
820 pinctrl_weim_gpio_3: weimgpio-3 {
822 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0
823 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
824 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0
825 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0
826 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0
827 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
828 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0
829 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0
830 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
831 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
832 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
833 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
834 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
835 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
836 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
840 /* DQM[0:3] used as GPIO */
841 pinctrl_weim_gpio_4: weimgpio-4 {
843 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0
844 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0
845 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
846 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
850 /* RDY used as GPIO */
851 pinctrl_weim_gpio_5: weimgpio-5 {
853 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0
857 /* ADDRESS[16] DATA[30] used as GPIO */
858 pinctrl_weim_gpio_6: weimgpio-6 {
860 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
861 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0