arch/arm/boot/dts/imx6qdl-apalis.dtsi

   1 /*
   2  * Copyright 2014-2017 Toradex AG
   3  * Copyright 2012 Freescale Semiconductor, Inc.
   4  * Copyright 2011 Linaro Ltd.
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License
  13  *     version 2 as published by the Free Software Foundation.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45
  46 / {
  47         model = "Toradex Apalis iMX6Q/D Module";
  48         compatible = "toradex,apalis_imx6q", "fsl,imx6q";
  49
  50         /* Will be filled by the bootloader */
  51         memory@10000000 {
  52                 device_type = "memory";
  53                 reg = <0x10000000 0>;
  54         };
  55
  56         backlight: backlight {
  57                 compatible = "pwm-backlight";
  58                 pinctrl-names = "default";
  59                 pinctrl-0 = <&pinctrl_gpio_bl_on>;
  60                 pwms = <&pwm4 0 5000000>;
  61                 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
  62                 status = "disabled";
  63         };
  64
  65         reg_module_3v3: regulator-module-3v3 {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "+V3.3";
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-max-microvolt = <3300000>;
  70                 regulator-always-on;
  71         };
  72
  73         reg_module_3v3_audio: regulator-module-3v3-audio {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "+V3.3_AUDIO";
  76                 regulator-min-microvolt = <3300000>;
  77                 regulator-max-microvolt = <3300000>;
  78                 regulator-always-on;
  79         };
  80
  81         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  82                 compatible = "regulator-fixed";
  83                 pinctrl-names = "default";
  84                 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>;
  85                 regulator-name = "usb_otg_vbus";
  86                 regulator-min-microvolt = <5000000>;
  87                 regulator-max-microvolt = <5000000>;
  88                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
  89                 enable-active-high;
  90                 status = "disabled";
  91         };
  92
  93         /* on module USB hub */
  94         reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub {
  95                 compatible = "regulator-fixed";
  96                 pinctrl-names = "default";
  97                 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>;
  98                 regulator-name = "usb_host_vbus_hub";
  99                 regulator-min-microvolt = <5000000>;
 100                 regulator-max-microvolt = <5000000>;
 101                 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 102                 startup-delay-us = <2000>;
 103                 enable-active-high;
 104                 status = "okay";
 105         };
 106
 107         reg_usb_host_vbus: regulator-usb-host-vbus {
 108                 compatible = "regulator-fixed";
 109                 pinctrl-names = "default";
 110                 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
 111                 regulator-name = "usb_host_vbus";
 112                 regulator-min-microvolt = <5000000>;
 113                 regulator-max-microvolt = <5000000>;
 114                 gpio =  <&gpio1 0 GPIO_ACTIVE_HIGH>;
 115                 enable-active-high;
 116                 vin-supply = <&reg_usb_host_vbus_hub>;
 117                 status = "disabled";
 118         };
 119
 120         sound {
 121                 compatible = "fsl,imx-audio-sgtl5000";
 122                 model = "imx6q-apalis-sgtl5000";
 123                 ssi-controller = <&ssi1>;
 124                 audio-codec = <&codec>;
 125                 audio-routing =
 126                         "LINE_IN", "Line In Jack",
 127                         "MIC_IN", "Mic Jack",
 128                         "Mic Jack", "Mic Bias",
 129                         "Headphone Jack", "HP_OUT";
 130                 mux-int-port = <1>;
 131                 mux-ext-port = <4>;
 132         };
 133
 134         sound_spdif: sound-spdif {
 135                 compatible = "fsl,imx-audio-spdif";
 136                 model = "imx-spdif";
 137                 spdif-controller = <&spdif>;
 138                 spdif-in;
 139                 spdif-out;
 140                 status = "disabled";
 141         };
 142 };
 143
 144 &audmux {
 145         pinctrl-names = "default";
 146         pinctrl-0 = <&pinctrl_audmux>;
 147         status = "okay";
 148 };
 149
 150 &can1 {
 151         pinctrl-names = "default", "sleep";
 152         pinctrl-0 = <&pinctrl_flexcan1_default>;
 153         pinctrl-1 = <&pinctrl_flexcan1_sleep>;
 154         status = "disabled";
 155 };
 156
 157 &can2 {
 158         pinctrl-names = "default", "sleep";
 159         pinctrl-0 = <&pinctrl_flexcan2_default>;
 160         pinctrl-1 = <&pinctrl_flexcan2_sleep>;
 161         status = "disabled";
 162 };
 163
 164 /* Apalis SPI1 */
 165 &ecspi1 {
 166         cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
 167         pinctrl-names = "default";
 168         pinctrl-0 = <&pinctrl_ecspi1>;
 169         status = "disabled";
 170 };
 171
 172 /* Apalis SPI2 */
 173 &ecspi2 {
 174         cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_ecspi2>;
 177         status = "disabled";
 178 };
 179
 180 &fec {
 181         pinctrl-names = "default";
 182         pinctrl-0 = <&pinctrl_enet>;
 183         phy-mode = "rgmii";
 184         phy-handle = <&ethphy>;
 185         phy-reset-duration = <10>;
 186         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 187         status = "okay";
 188
 189         mdio {
 190                 #address-cells = <1>;
 191                 #size-cells = <0>;
 192
 193                 ethphy: ethernet-phy@7 {
 194                         interrupt-parent = <&gpio1>;
 195                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
 196                         reg = <7>;
 197                 };
 198         };
 199 };
 200
 201 &hdmi {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>;
 204         status = "disabled";
 205 };
 206
 207 /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
 208 &i2c1 {
 209         clock-frequency = <100000>;
 210         pinctrl-names = "default", "gpio";
 211         pinctrl-0 = <&pinctrl_i2c1>;
 212         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 213         scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 214         sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 215         status = "disabled";
 216 };
 217
 218 /*
 219  * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 220  * touch screen controller
 221  */
 222 &i2c2 {
 223         clock-frequency = <100000>;
 224         pinctrl-names = "default", "gpio";
 225         pinctrl-0 = <&pinctrl_i2c2>;
 226         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 227         scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 228         sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 229         status = "okay";
 230
 231         pmic: pfuze100@8 {
 232                 compatible = "fsl,pfuze100";
 233                 reg = <0x08>;
 234
 235                 regulators {
 236                         sw1a_reg: sw1ab {
 237                                 regulator-min-microvolt = <300000>;
 238                                 regulator-max-microvolt = <1875000>;
 239                                 regulator-boot-on;
 240                                 regulator-always-on;
 241                                 regulator-ramp-delay = <6250>;
 242                         };
 243
 244                         sw1c_reg: sw1c {
 245                                 regulator-min-microvolt = <300000>;
 246                                 regulator-max-microvolt = <1875000>;
 247                                 regulator-boot-on;
 248                                 regulator-always-on;
 249                                 regulator-ramp-delay = <6250>;
 250                         };
 251
 252                         sw3a_reg: sw3a {
 253                                 regulator-min-microvolt = <400000>;
 254                                 regulator-max-microvolt = <1975000>;
 255                                 regulator-boot-on;
 256                                 regulator-always-on;
 257                         };
 258
 259                         swbst_reg: swbst {
 260                                 regulator-min-microvolt = <5000000>;
 261                                 regulator-max-microvolt = <5150000>;
 262                                 regulator-boot-on;
 263                                 regulator-always-on;
 264                         };
 265
 266                         snvs_reg: vsnvs {
 267                                 regulator-min-microvolt = <1000000>;
 268                                 regulator-max-microvolt = <3000000>;
 269                                 regulator-boot-on;
 270                                 regulator-always-on;
 271                         };
 272
 273                         vref_reg: vrefddr {
 274                                 regulator-boot-on;
 275                                 regulator-always-on;
 276                         };
 277
 278                         vgen1_reg: vgen1 {
 279                                 regulator-min-microvolt = <800000>;
 280                                 regulator-max-microvolt = <1550000>;
 281                                 regulator-boot-on;
 282                                 regulator-always-on;
 283                         };
 284
 285                         vgen2_reg: vgen2 {
 286                                 regulator-min-microvolt = <800000>;
 287                                 regulator-max-microvolt = <1550000>;
 288                                 regulator-boot-on;
 289                                 regulator-always-on;
 290                         };
 291
 292                         vgen3_reg: vgen3 {
 293                                 regulator-min-microvolt = <1800000>;
 294                                 regulator-max-microvolt = <3300000>;
 295                                 regulator-boot-on;
 296                                 regulator-always-on;
 297                         };
 298
 299                         vgen4_reg: vgen4 {
 300                                 regulator-min-microvolt = <1800000>;
 301                                 regulator-max-microvolt = <1800000>;
 302                                 regulator-boot-on;
 303                                 regulator-always-on;
 304                         };
 305
 306                         vgen5_reg: vgen5 {
 307                                 regulator-min-microvolt = <1800000>;
 308                                 regulator-max-microvolt = <3300000>;
 309                                 regulator-boot-on;
 310                                 regulator-always-on;
 311                         };
 312
 313                         vgen6_reg: vgen6 {
 314                                 regulator-min-microvolt = <1800000>;
 315                                 regulator-max-microvolt = <3300000>;
 316                                 regulator-boot-on;
 317                                 regulator-always-on;
 318                         };
 319                 };
 320         };
 321
 322         codec: sgtl5000@a {
 323                 compatible = "fsl,sgtl5000";
 324                 reg = <0x0a>;
 325                 clocks = <&clks IMX6QDL_CLK_CKO>;
 326                 VDDA-supply = <&reg_module_3v3_audio>;
 327                 VDDIO-supply = <&reg_module_3v3>;
 328                 VDDD-supply = <&vgen4_reg>;
 329         };
 330
 331         /* STMPE811 touch screen controller */
 332         stmpe811@41 {
 333                 compatible = "st,stmpe811";
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&pinctrl_touch_int>;
 336                 reg = <0x41>;
 337                 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 338                 interrupt-parent = <&gpio4>;
 339                 interrupt-controller;
 340                 id = <0>;
 341                 blocks = <0x5>;
 342                 irq-trigger = <0x1>;
 343                 /* 3.25 MHz ADC clock speed */
 344                 st,adc-freq = <1>;
 345                 /* 12-bit ADC */
 346                 st,mod-12b = <1>;
 347                 /* internal ADC reference */
 348                 st,ref-sel = <0>;
 349                 /* ADC converstion time: 80 clocks */
 350                 st,sample-time = <4>;
 351
 352                 stmpe_touchscreen {
 353                         compatible = "st,stmpe-ts";
 354                         /* 8 sample average control */
 355                         st,ave-ctrl = <3>;
 356                         /* 7 length fractional part in z */
 357                         st,fraction-z = <7>;
 358                         /*
 359                          * 50 mA typical 80 mA max touchscreen drivers
 360                          * current limit value
 361                          */
 362                         st,i-drive = <1>;
 363                         /* 1 ms panel driver settling time */
 364                         st,settling = <3>;
 365                         /* 5 ms touch detect interrupt delay */
 366                         st,touch-det-delay = <5>;
 367                 };
 368
 369                 stmpe_adc {
 370                         compatible = "st,stmpe-adc";
 371                         /* forbid to use ADC channels 3-0 (touch) */
 372                         st,norequest-mask = <0x0F>;
 373                 };
 374         };
 375 };
 376
 377 /*
 378  * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
 379  * board)
 380  */
 381 &i2c3 {
 382         clock-frequency = <100000>;
 383         pinctrl-names = "default", "gpio";
 384         pinctrl-0 = <&pinctrl_i2c3>;
 385         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 386         scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 387         sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 388         status = "disabled";
 389 };
 390
 391 &pwm1 {
 392         pinctrl-names = "default";
 393         pinctrl-0 = <&pinctrl_pwm1>;
 394         status = "disabled";
 395 };
 396
 397 &pwm2 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&pinctrl_pwm2>;
 400         status = "disabled";
 401 };
 402
 403 &pwm3 {
 404         pinctrl-names = "default";
 405         pinctrl-0 = <&pinctrl_pwm3>;
 406         status = "disabled";
 407 };
 408
 409 &pwm4 {
 410         pinctrl-names = "default";
 411         pinctrl-0 = <&pinctrl_pwm4>;
 412         status = "disabled";
 413 };
 414
 415 &spdif {
 416         pinctrl-names = "default";
 417         pinctrl-0 = <&pinctrl_spdif>;
 418         status = "disabled";
 419 };
 420
 421 &ssi1 {
 422         status = "okay";
 423 };
 424
 425 &uart1 {
 426         pinctrl-names = "default";
 427         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
 428         fsl,dte-mode;
 429         uart-has-rtscts;
 430         status = "disabled";
 431 };
 432
 433 &uart2 {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_uart2_dte>;
 436         fsl,dte-mode;
 437         uart-has-rtscts;
 438         status = "disabled";
 439 };
 440
 441 &uart4 {
 442         pinctrl-names = "default";
 443         pinctrl-0 = <&pinctrl_uart4_dte>;
 444         fsl,dte-mode;
 445         status = "disabled";
 446 };
 447
 448 &uart5 {
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&pinctrl_uart5_dte>;
 451         fsl,dte-mode;
 452         status = "disabled";
 453 };
 454
 455 &usbotg {
 456         pinctrl-names = "default";
 457         pinctrl-0 = <&pinctrl_usbotg>;
 458         disable-over-current;
 459         status = "disabled";
 460 };
 461
 462 /* MMC1 */
 463 &usdhc1 {
 464         pinctrl-names = "default";
 465         pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>;
 466         vqmmc-supply = <&reg_module_3v3>;
 467         bus-width = <8>;
 468         disable-wp;
 469         no-1-8-v;
 470         status = "disabled";
 471 };
 472
 473 /* SD1 */
 474 &usdhc2 {
 475         pinctrl-names = "default";
 476         pinctrl-0 = <&pinctrl_usdhc2>;
 477         vqmmc-supply = <&reg_module_3v3>;
 478         bus-width = <4>;
 479         disable-wp;
 480         no-1-8-v;
 481         status = "disabled";
 482 };
 483
 484 /* eMMC */
 485 &usdhc3 {
 486         pinctrl-names = "default";
 487         pinctrl-0 = <&pinctrl_usdhc3>;
 488         vqmmc-supply = <&reg_module_3v3>;
 489         bus-width = <8>;
 490         no-1-8-v;
 491         non-removable;
 492         status = "okay";
 493 };
 494
 495 &weim {
 496         status = "disabled";
 497 };
 498
 499 &iomuxc {
 500         pinctrl_apalis_gpio1: gpio2io04grp {
 501                 fsl,pins = <
 502                         MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
 503                 >;
 504         };
 505
 506         pinctrl_apalis_gpio2: gpio2io05grp {
 507                 fsl,pins = <
 508                         MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
 509                 >;
 510         };
 511
 512         pinctrl_apalis_gpio3: gpio2io06grp {
 513                 fsl,pins = <
 514                         MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
 515                 >;
 516         };
 517
 518         pinctrl_apalis_gpio4: gpio2io07grp {
 519                 fsl,pins = <
 520                         MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
 521                 >;
 522         };
 523
 524         pinctrl_apalis_gpio5: gpio6io10grp {
 525                 fsl,pins = <
 526                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
 527                 >;
 528         };
 529
 530         pinctrl_apalis_gpio6: gpio6io09grp {
 531                 fsl,pins = <
 532                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
 533                 >;
 534         };
 535
 536         pinctrl_apalis_gpio7: gpio1io02grp {
 537                 fsl,pins = <
 538                         MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
 539                 >;
 540         };
 541
 542         pinctrl_apalis_gpio8: gpio1io06grp {
 543                 fsl,pins = <
 544                         MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
 545                 >;
 546         };
 547
 548         pinctrl_audmux: audmuxgrp {
 549                 fsl,pins = <
 550                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC        0x130b0
 551                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD        0x130b0
 552                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS       0x130b0
 553                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD        0x130b0
 554                         /* SGTL5000 sys_mclk */
 555                         MX6QDL_PAD_GPIO_5__CCM_CLKO1            0x130b0
 556                 >;
 557         };
 558
 559         pinctrl_cam_mclk: cammclkgrp {
 560                 fsl,pins = <
 561                         /* CAM sys_mclk */
 562                         MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0
 563                 >;
 564         };
 565
 566         pinctrl_ecspi1: ecspi1grp {
 567                 fsl,pins = <
 568                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
 569                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
 570                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
 571                         /* SPI1 cs */
 572                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1
 573                 >;
 574         };
 575
 576         pinctrl_ecspi2: ecspi2grp {
 577                 fsl,pins = <
 578                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
 579                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 580                         MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 581                         /* SPI2 cs */
 582                         MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
 583                 >;
 584         };
 585
 586         pinctrl_enet: enetgrp {
 587                 fsl,pins = <
 588                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 589                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 590                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 591                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 592                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 593                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 594                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 595                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 596                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 597                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 598                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 599                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 600                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 601                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 602                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 603                         /* Ethernet PHY reset */
 604                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x000b0
 605                         /* Ethernet PHY interrupt */
 606                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x000b1
 607                 >;
 608         };
 609
 610         pinctrl_flexcan1_default: flexcan1defgrp {
 611                 fsl,pins = <
 612                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
 613                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
 614                 >;
 615         };
 616
 617         pinctrl_flexcan1_sleep: flexcan1slpgrp {
 618                 fsl,pins = <
 619                         MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
 620                         MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
 621                 >;
 622         };
 623
 624         pinctrl_flexcan2_default: flexcan2defgrp {
 625                 fsl,pins = <
 626                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
 627                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
 628                 >;
 629         };
 630         pinctrl_flexcan2_sleep: flexcan2slpgrp {
 631                 fsl,pins = <
 632                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
 633                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
 634                 >;
 635         };
 636
 637         pinctrl_gpio_bl_on: gpioblon {
 638                 fsl,pins = <
 639                         MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0
 640                 >;
 641         };
 642
 643         pinctrl_gpio_keys: gpio1io04grp {
 644                 fsl,pins = <
 645                         /* Power button */
 646                         MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
 647                 >;
 648         };
 649
 650         pinctrl_hdmi_cec: hdmicecgrp {
 651                 fsl,pins = <
 652                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
 653                 >;
 654         };
 655
 656         pinctrl_hdmi_ddc: hdmiddcgrp {
 657                 fsl,pins = <
 658                         MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
 659                         MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
 660                 >;
 661         };
 662
 663         pinctrl_i2c1: i2c1grp {
 664                 fsl,pins = <
 665                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 666                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 667                 >;
 668         };
 669
 670         pinctrl_i2c1_gpio: i2c1gpiogrp {
 671                 fsl,pins = <
 672                         MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
 673                         MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
 674                 >;
 675         };
 676
 677         pinctrl_i2c2: i2c2grp {
 678                 fsl,pins = <
 679                         MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 680                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 681                 >;
 682         };
 683
 684         pinctrl_i2c2_gpio: i2c2gpiogrp {
 685                 fsl,pins = <
 686                         MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
 687                         MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
 688                 >;
 689         };
 690
 691         pinctrl_i2c3: i2c3grp {
 692                 fsl,pins = <
 693                         MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 694                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 695                 >;
 696         };
 697
 698         pinctrl_i2c3_gpio: i2c3gpiogrp {
 699                 fsl,pins = <
 700                         MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1
 701                         MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1
 702                 >;
 703         };
 704
 705         pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
 706                 fsl,pins = <
 707                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0xb0b1
 708                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0xb0b1
 709                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0xb0b1
 710                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0xb0b1
 711                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0xb0b1
 712                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0xb0b1
 713                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0xb0b1
 714                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0xb0b1
 715                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1
 716                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0xb0b1
 717                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0xb0b1
 718                 >;
 719         };
 720
 721         pinctrl_ipu1_lcdif: ipu1lcdifgrp {
 722                 fsl,pins = <
 723                         MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK   0x61
 724                         /* DE */
 725                         MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15     0x61
 726                         /* HSync */
 727                         MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02     0x61
 728                         /* VSync */
 729                         MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03     0x61
 730                         MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00   0x61
 731                         MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01   0x61
 732                         MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02   0x61
 733                         MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03   0x61
 734                         MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04   0x61
 735                         MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05   0x61
 736                         MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06   0x61
 737                         MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07   0x61
 738                         MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08   0x61
 739                         MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09   0x61
 740                         MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10   0x61
 741                         MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11   0x61
 742                         MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12   0x61
 743                         MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13   0x61
 744                         MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14   0x61
 745                         MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15   0x61
 746                         MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16   0x61
 747                         MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17   0x61
 748                         MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18   0x61
 749                         MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19   0x61
 750                         MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20   0x61
 751                         MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21   0x61
 752                         MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22   0x61
 753                         MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23   0x61
 754                 >;
 755         };
 756
 757         pinctrl_ipu2_vdac: ipu2vdacgrp {
 758                 fsl,pins = <
 759                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1
 760                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0xd1
 761                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0xd1
 762                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0xd1
 763                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0xf9
 764                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0xf9
 765                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0xf9
 766                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0xf9
 767                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0xf9
 768                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0xf9
 769                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0xf9
 770                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0xf9
 771                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0xf9
 772                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0xf9
 773                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0xf9
 774                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0xf9
 775                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0xf9
 776                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0xf9
 777                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0xf9
 778                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0xf9
 779                 >;
 780         };
 781
 782         pinctrl_mmc_cd: gpiommccdgrp {
 783                 fsl,pins = <
 784                          /* MMC1 CD */
 785                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
 786                 >;
 787         };
 788
 789         pinctrl_pwm1: pwm1grp {
 790                 fsl,pins = <
 791                         MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
 792                 >;
 793         };
 794
 795         pinctrl_pwm2: pwm2grp {
 796                 fsl,pins = <
 797                         MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
 798                 >;
 799         };
 800
 801         pinctrl_pwm3: pwm3grp {
 802                 fsl,pins = <
 803                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 804                 >;
 805         };
 806
 807         pinctrl_pwm4: pwm4grp {
 808                 fsl,pins = <
 809                         MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
 810                 >;
 811         };
 812
 813         pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
 814                 fsl,pins = <
 815                         /* USBH_EN */
 816                         MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
 817                 >;
 818         };
 819
 820         pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
 821                 fsl,pins = <
 822                         /* USBH_HUB_EN */
 823                         MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
 824                 >;
 825         };
 826
 827         pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
 828                 fsl,pins = <
 829                         /* USBO1 power en */
 830                         MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
 831                 >;
 832         };
 833
 834         pinctrl_reset_moci: gpioresetmocigrp {
 835                 fsl,pins = <
 836                         /* RESET_MOCI control */
 837                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
 838                 >;
 839         };
 840
 841         pinctrl_sd_cd: gpiosdcdgrp {
 842                 fsl,pins = <
 843                         /* SD1 CD */
 844                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
 845                 >;
 846         };
 847
 848         pinctrl_spdif: spdifgrp {
 849                 fsl,pins = <
 850                         MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
 851                         MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 852                 >;
 853         };
 854
 855         pinctrl_touch_int: gpiotouchintgrp {
 856                 fsl,pins = <
 857                         /* STMPE811 interrupt */
 858                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
 859                 >;
 860         };
 861
 862         pinctrl_uart1_dce: uart1dcegrp {
 863                 fsl,pins = <
 864                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 865                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 866                 >;
 867         };
 868
 869         /* DTE mode */
 870         pinctrl_uart1_dte: uart1dtegrp {
 871                 fsl,pins = <
 872                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
 873                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
 874                         MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
 875                         MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 876                 >;
 877         };
 878
 879         /* Additional DTR, DSR, DCD */
 880         pinctrl_uart1_ctrl: uart1ctrlgrp {
 881                 fsl,pins = <
 882                         MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
 883                         MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
 884                         MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
 885                 >;
 886         };
 887
 888         pinctrl_uart2_dce: uart2dcegrp {
 889                 fsl,pins = <
 890                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 891                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 892                 >;
 893         };
 894
 895         /* DTE mode */
 896         pinctrl_uart2_dte: uart2dtegrp {
 897                 fsl,pins = <
 898                         MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA      0x1b0b1
 899                         MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA      0x1b0b1
 900                         MX6QDL_PAD_SD4_DAT6__UART2_RTS_B        0x1b0b1
 901                         MX6QDL_PAD_SD4_DAT5__UART2_CTS_B        0x1b0b1
 902                 >;
 903         };
 904
 905         pinctrl_uart4_dce: uart4dcegrp {
 906                 fsl,pins = <
 907                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 908                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 909                 >;
 910         };
 911
 912         /* DTE mode */
 913         pinctrl_uart4_dte: uart4dtegrp {
 914                 fsl,pins = <
 915                         MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1
 916                         MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1
 917                 >;
 918         };
 919
 920         pinctrl_uart5_dce: uart5dcegrp {
 921                 fsl,pins = <
 922                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
 923                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
 924                 >;
 925         };
 926
 927         /* DTE mode */
 928         pinctrl_uart5_dte: uart5dtegrp {
 929                 fsl,pins = <
 930                         MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
 931                         MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
 932                 >;
 933         };
 934
 935         pinctrl_usbotg: usbotggrp {
 936                 fsl,pins = <
 937                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 938                 >;
 939         };
 940
 941         pinctrl_usdhc1_4bit: usdhc1grp_4bit {
 942                 fsl,pins = <
 943                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17071
 944                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10071
 945                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
 946                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
 947                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
 948                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
 949                 >;
 950         };
 951
 952         pinctrl_usdhc1_8bit: usdhc1grp_8bit {
 953                 fsl,pins = <
 954                         MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
 955                         MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
 956                         MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
 957                         MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071
 958                 >;
 959         };
 960
 961         pinctrl_usdhc2: usdhc2grp {
 962                 fsl,pins = <
 963                         MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17071
 964                         MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10071
 965                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071
 966                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071
 967                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071
 968                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071
 969                 >;
 970         };
 971
 972         pinctrl_usdhc3: usdhc3grp {
 973                 fsl,pins = <
 974                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 975                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 976                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 977                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 978                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 979                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 980                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 981                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 982                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 983                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 984                         /* eMMC reset */
 985                         MX6QDL_PAD_SD3_RST__SD3_RESET  0x17059
 986                 >;
 987         };
 988 };