arch/arm/boot/dts/imx6q.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6q-pinfunc.h"
   7 #include "imx6qdl.dtsi"
   8
   9 / {
  10         aliases {
  11                 ipu1 = &ipu2;
  12                 spi4 = &ecspi5;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                         operating-points = <
  25                                 /* kHz    uV */
  26                                 1200000 1275000
  27                                 996000  1250000
  28                                 852000  1250000
  29                                 792000  1175000
  30                                 396000  975000
  31                         >;
  32                         fsl,soc-operating-points = <
  33                                 /* ARM kHz  SOC-PU uV */
  34                                 1200000 1275000
  35                                 996000  1250000
  36                                 852000  1250000
  37                                 792000  1175000
  38                                 396000  1175000
  39                         >;
  40                         clock-latency = <61036>; /* two CLK32 periods */
  41                         #cooling-cells = <2>;
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                         nvmem-cells = <&cpu_speed_grade>;
  53                         nvmem-cell-names = "speed_grade";
  54                 };
  55
  56                 cpu1: cpu@1 {
  57                         compatible = "arm,cortex-a9";
  58                         device_type = "cpu";
  59                         reg = <1>;
  60                         next-level-cache = <&L2>;
  61                         operating-points = <
  62                                 /* kHz    uV */
  63                                 1200000 1275000
  64                                 996000  1250000
  65                                 852000  1250000
  66                                 792000  1175000
  67                                 396000  975000
  68                         >;
  69                         fsl,soc-operating-points = <
  70                                 /* ARM kHz  SOC-PU uV */
  71                                 1200000 1275000
  72                                 996000  1250000
  73                                 852000  1250000
  74                                 792000  1175000
  75                                 396000  1175000
  76                         >;
  77                         clock-latency = <61036>; /* two CLK32 periods */
  78                         #cooling-cells = <2>;
  79                         clocks = <&clks IMX6QDL_CLK_ARM>,
  80                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  81                                  <&clks IMX6QDL_CLK_STEP>,
  82                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  83                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  84                         clock-names = "arm", "pll2_pfd2_396m", "step",
  85                                       "pll1_sw", "pll1_sys";
  86                         arm-supply = <&reg_arm>;
  87                         pu-supply = <&reg_pu>;
  88                         soc-supply = <&reg_soc>;
  89                 };
  90
  91                 cpu2: cpu@2 {
  92                         compatible = "arm,cortex-a9";
  93                         device_type = "cpu";
  94                         reg = <2>;
  95                         next-level-cache = <&L2>;
  96                         operating-points = <
  97                                 /* kHz    uV */
  98                                 1200000 1275000
  99                                 996000  1250000
 100                                 852000  1250000
 101                                 792000  1175000
 102                                 396000  975000
 103                         >;
 104                         fsl,soc-operating-points = <
 105                                 /* ARM kHz  SOC-PU uV */
 106                                 1200000 1275000
 107                                 996000  1250000
 108                                 852000  1250000
 109                                 792000  1175000
 110                                 396000  1175000
 111                         >;
 112                         clock-latency = <61036>; /* two CLK32 periods */
 113                         #cooling-cells = <2>;
 114                         clocks = <&clks IMX6QDL_CLK_ARM>,
 115                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 116                                  <&clks IMX6QDL_CLK_STEP>,
 117                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 118                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 119                         clock-names = "arm", "pll2_pfd2_396m", "step",
 120                                       "pll1_sw", "pll1_sys";
 121                         arm-supply = <&reg_arm>;
 122                         pu-supply = <&reg_pu>;
 123                         soc-supply = <&reg_soc>;
 124                 };
 125
 126                 cpu3: cpu@3 {
 127                         compatible = "arm,cortex-a9";
 128                         device_type = "cpu";
 129                         reg = <3>;
 130                         next-level-cache = <&L2>;
 131                         operating-points = <
 132                                 /* kHz    uV */
 133                                 1200000 1275000
 134                                 996000  1250000
 135                                 852000  1250000
 136                                 792000  1175000
 137                                 396000  975000
 138                         >;
 139                         fsl,soc-operating-points = <
 140                                 /* ARM kHz  SOC-PU uV */
 141                                 1200000 1275000
 142                                 996000  1250000
 143                                 852000  1250000
 144                                 792000  1175000
 145                                 396000  1175000
 146                         >;
 147                         clock-latency = <61036>; /* two CLK32 periods */
 148                         #cooling-cells = <2>;
 149                         clocks = <&clks IMX6QDL_CLK_ARM>,
 150                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 151                                  <&clks IMX6QDL_CLK_STEP>,
 152                                  <&clks IMX6QDL_CLK_PLL1_SW>,
 153                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
 154                         clock-names = "arm", "pll2_pfd2_396m", "step",
 155                                       "pll1_sw", "pll1_sys";
 156                         arm-supply = <&reg_arm>;
 157                         pu-supply = <&reg_pu>;
 158                         soc-supply = <&reg_soc>;
 159                 };
 160         };
 161
 162         soc {
 163                 ocram: sram@900000 {
 164                         compatible = "mmio-sram";
 165                         reg = <0x00900000 0x40000>;
 166                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
 167                 };
 168
 169                 bus@2000000 { /* AIPS1 */
 170                         spba-bus@2000000 {
 171                                 ecspi5: spi@2018000 {
 172                                         #address-cells = <1>;
 173                                         #size-cells = <0>;
 174                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 175                                         reg = <0x02018000 0x4000>;
 176                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 177                                         clocks = <&clks IMX6Q_CLK_ECSPI5>,
 178                                                  <&clks IMX6Q_CLK_ECSPI5>;
 179                                         clock-names = "ipg", "per";
 180                                         dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
 181                                         dma-names = "rx", "tx";
 182                                         status = "disabled";
 183                                 };
 184                         };
 185
 186                         iomuxc: pinctrl@20e0000 {
 187                                 compatible = "fsl,imx6q-iomuxc";
 188                         };
 189                 };
 190
 191                 sata: sata@2200000 {
 192                         compatible = "fsl,imx6q-ahci";
 193                         reg = <0x02200000 0x4000>;
 194                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 195                         clocks = <&clks IMX6QDL_CLK_SATA>,
 196                                  <&clks IMX6QDL_CLK_SATA_REF_100M>,
 197                                  <&clks IMX6QDL_CLK_AHB>;
 198                         clock-names = "sata", "sata_ref", "ahb";
 199                         status = "disabled";
 200                 };
 201
 202                 gpu_vg: gpu@2204000 {
 203                         compatible = "vivante,gc";
 204                         reg = <0x02204000 0x4000>;
 205                         interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 206                         clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 207                                  <&clks IMX6QDL_CLK_GPU2D_CORE>;
 208                         clock-names = "bus", "core";
 209                         power-domains = <&pd_pu>;
 210                         #cooling-cells = <2>;
 211                 };
 212
 213                 ipu2: ipu@2800000 {
 214                         #address-cells = <1>;
 215                         #size-cells = <0>;
 216                         compatible = "fsl,imx6q-ipu";
 217                         reg = <0x02800000 0x400000>;
 218                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&clks IMX6QDL_CLK_IPU2>,
 221                                  <&clks IMX6QDL_CLK_IPU2_DI0>,
 222                                  <&clks IMX6QDL_CLK_IPU2_DI1>;
 223                         clock-names = "bus", "di0", "di1";
 224                         resets = <&src 4>;
 225
 226                         ipu2_csi0: port@0 {
 227                                 reg = <0>;
 228
 229                                 ipu2_csi0_from_mipi_vc2: endpoint {
 230                                         remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 231                                 };
 232                         };
 233
 234                         ipu2_csi1: port@1 {
 235                                 reg = <1>;
 236
 237                                 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 238                                         remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 239                                 };
 240                         };
 241
 242                         ipu2_di0: port@2 {
 243                                 #address-cells = <1>;
 244                                 #size-cells = <0>;
 245                                 reg = <2>;
 246
 247                                 ipu2_di0_disp0: endpoint@0 {
 248                                         reg = <0>;
 249                                 };
 250
 251                                 ipu2_di0_hdmi: endpoint@1 {
 252                                         reg = <1>;
 253                                         remote-endpoint = <&hdmi_mux_2>;
 254                                 };
 255
 256                                 ipu2_di0_mipi: endpoint@2 {
 257                                         reg = <2>;
 258                                         remote-endpoint = <&mipi_mux_2>;
 259                                 };
 260
 261                                 ipu2_di0_lvds0: endpoint@3 {
 262                                         reg = <3>;
 263                                         remote-endpoint = <&lvds0_mux_2>;
 264                                 };
 265
 266                                 ipu2_di0_lvds1: endpoint@4 {
 267                                         reg = <4>;
 268                                         remote-endpoint = <&lvds1_mux_2>;
 269                                 };
 270                         };
 271
 272                         ipu2_di1: port@3 {
 273                                 #address-cells = <1>;
 274                                 #size-cells = <0>;
 275                                 reg = <3>;
 276
 277                                 ipu2_di1_hdmi: endpoint@1 {
 278                                         reg = <1>;
 279                                         remote-endpoint = <&hdmi_mux_3>;
 280                                 };
 281
 282                                 ipu2_di1_mipi: endpoint@2 {
 283                                         reg = <2>;
 284                                         remote-endpoint = <&mipi_mux_3>;
 285                                 };
 286
 287                                 ipu2_di1_lvds0: endpoint@3 {
 288                                         reg = <3>;
 289                                         remote-endpoint = <&lvds0_mux_3>;
 290                                 };
 291
 292                                 ipu2_di1_lvds1: endpoint@4 {
 293                                         reg = <4>;
 294                                         remote-endpoint = <&lvds1_mux_3>;
 295                                 };
 296                         };
 297                 };
 298         };
 299
 300         capture-subsystem {
 301                 compatible = "fsl,imx-capture-subsystem";
 302                 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 303         };
 304
 305         display-subsystem {
 306                 compatible = "fsl,imx-display-subsystem";
 307                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 308         };
 309 };
 310
 311 &gpio1 {
 312         gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 313                       <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 314                       <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 315                       <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 316                       <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 317                       <&iomuxc 22 116 10>;
 318 };
 319
 320 &gpio2 {
 321         gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 322                       <&iomuxc 31  44  1>;
 323 };
 324
 325 &gpio3 {
 326         gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 327 };
 328
 329 &gpio4 {
 330         gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 331 };
 332
 333 &gpio5 {
 334         gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 335                       <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 336 };
 337
 338 &gpio6 {
 339         gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 340                       <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 341                       <&iomuxc 31  86 1>;
 342 };
 343
 344 &gpio7 {
 345         gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 346 };
 347
 348 &gpr {
 349         ipu1_csi0_mux {
 350                 compatible = "video-mux";
 351                 mux-controls = <&mux 0>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354
 355                 port@0 {
 356                         reg = <0>;
 357
 358                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 359                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 360                         };
 361                 };
 362
 363                 port@1 {
 364                         reg = <1>;
 365
 366                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 367                         };
 368                 };
 369
 370                 port@2 {
 371                         reg = <2>;
 372
 373                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 374                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 375                         };
 376                 };
 377         };
 378
 379         ipu2_csi1_mux {
 380                 compatible = "video-mux";
 381                 mux-controls = <&mux 1>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384
 385                 port@0 {
 386                         reg = <0>;
 387
 388                         ipu2_csi1_mux_from_mipi_vc3: endpoint {
 389                                 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 390                         };
 391                 };
 392
 393                 port@1 {
 394                         reg = <1>;
 395
 396                         ipu2_csi1_mux_from_parallel_sensor: endpoint {
 397                         };
 398                 };
 399
 400                 port@2 {
 401                         reg = <2>;
 402
 403                         ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 404                                 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 405                         };
 406                 };
 407         };
 408 };
 409
 410 &hdmi {
 411         compatible = "fsl,imx6q-hdmi";
 412
 413         port@2 {
 414                 reg = <2>;
 415
 416                 hdmi_mux_2: endpoint {
 417                         remote-endpoint = <&ipu2_di0_hdmi>;
 418                 };
 419         };
 420
 421         port@3 {
 422                 reg = <3>;
 423
 424                 hdmi_mux_3: endpoint {
 425                         remote-endpoint = <&ipu2_di1_hdmi>;
 426                 };
 427         };
 428 };
 429
 430 &ipu1_csi1 {
 431         ipu1_csi1_from_mipi_vc1: endpoint {
 432                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 433         };
 434 };
 435
 436 &ldb {
 437         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 438                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 439                  <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 440                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 441         clock-names = "di0_pll", "di1_pll",
 442                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 443                       "di0", "di1";
 444
 445         lvds-channel@0 {
 446                 port@2 {
 447                         reg = <2>;
 448
 449                         lvds0_mux_2: endpoint {
 450                                 remote-endpoint = <&ipu2_di0_lvds0>;
 451                         };
 452                 };
 453
 454                 port@3 {
 455                         reg = <3>;
 456
 457                         lvds0_mux_3: endpoint {
 458                                 remote-endpoint = <&ipu2_di1_lvds0>;
 459                         };
 460                 };
 461         };
 462
 463         lvds-channel@1 {
 464                 port@2 {
 465                         reg = <2>;
 466
 467                         lvds1_mux_2: endpoint {
 468                                 remote-endpoint = <&ipu2_di0_lvds1>;
 469                         };
 470                 };
 471
 472                 port@3 {
 473                         reg = <3>;
 474
 475                         lvds1_mux_3: endpoint {
 476                                 remote-endpoint = <&ipu2_di1_lvds1>;
 477                         };
 478                 };
 479         };
 480 };
 481
 482 &mipi_csi {
 483         port@1 {
 484                 reg = <1>;
 485
 486                 mipi_vc0_to_ipu1_csi0_mux: endpoint {
 487                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 488                 };
 489         };
 490
 491         port@2 {
 492                 reg = <2>;
 493
 494                 mipi_vc1_to_ipu1_csi1: endpoint {
 495                         remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 496                 };
 497         };
 498
 499         port@3 {
 500                 reg = <3>;
 501
 502                 mipi_vc2_to_ipu2_csi0: endpoint {
 503                         remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 504                 };
 505         };
 506
 507         port@4 {
 508                 reg = <4>;
 509
 510                 mipi_vc3_to_ipu2_csi1_mux: endpoint {
 511                         remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 512                 };
 513         };
 514 };
 515
 516 &mipi_dsi {
 517         ports {
 518                 port@2 {
 519                         reg = <2>;
 520
 521                         mipi_mux_2: endpoint {
 522                                 remote-endpoint = <&ipu2_di0_mipi>;
 523                         };
 524                 };
 525
 526                 port@3 {
 527                         reg = <3>;
 528
 529                         mipi_mux_3: endpoint {
 530                                 remote-endpoint = <&ipu2_di1_mipi>;
 531                         };
 532                 };
 533         };
 534 };
 535
 536 &mux {
 537         mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 538                         <0x04 0x00100000>, /* MIPI_IPU2_MUX */
 539                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 540                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 541                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 542                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 543                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 544 };
 545
 546 &vpu {
 547         compatible = "fsl,imx6q-vpu", "cnm,coda960";
 548 };