Merge tag 'iio-fixes-for-5.6a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[linux-2.6-microblaze.git] / arch / arm / boot / dts / imx6q-display5.dtsi
1 /*
2  * Copyright 2017
3  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
4  *
5  * This file is dual-licensed: you can use it either under the terms
6  * of the GPL or the X11 license, at your option. Note that this dual
7  * licensing only applies to this file, and not this project as a
8  * whole.
9  *
10  *  a) This file is licensed under the terms of the GNU General Public
11  *     License version 2.  This program is licensed "as is" without
12  *     any warranty of any kind, whether express or implied.
13  *
14  * Or, alternatively,
15  *
16  *  b) Permission is hereby granted, free of charge, to any person
17  *     obtaining a copy of this software and associated documentation
18  *     files (the "Software"), to deal in the Software without
19  *     restriction, including without limitation the rights to use,
20  *     copy, modify, merge, publish, distribute, sublicense, and/or
21  *     sell copies of the Software, and to permit persons to whom the
22  *     Software is furnished to do so, subject to the following
23  *     conditions:
24  *
25  *     The above copyright notice and this permission notice shall be
26  *     included in all copies or substantial portions of the Software.
27  *
28  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
29  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
30  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
31  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
32  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
33  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
34  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
35  *     OTHER DEALINGS IN THE SOFTWARE.
36  */
37
38 /dts-v1/;
39
40 #include "imx6q.dtsi"
41
42 #include <dt-bindings/gpio/gpio.h>
43 #include <dt-bindings/pwm/pwm.h>
44 #include <dt-bindings/sound/fsl-imx-audmux.h>
45
46 / {
47         model = "Liebherr (LWN) display5 i.MX6 Quad Board";
48         compatible = "lwn,display5", "fsl,imx6q";
49
50         memory@10000000 {
51                 device_type = "memory";
52                 reg = <0x10000000 0x40000000>;
53         };
54
55         backlight_lvds: backlight {
56                 compatible = "pwm-backlight";
57                 pinctrl-names = "default";
58                 pinctrl-0 = <&pinctrl_backlight>;
59                 pwms = <&pwm2 0 5000000 0>;
60                 brightness-levels = <  0   1   2   3   4   5   6   7   8   9
61                                       10  11  12  13  14  15  16  17  18  19
62                                       20  21  22  23  24  25  26  27  28  29
63                                       30  31  32  33  34  35  36  37  38  39
64                                       40  41  42  43  44  45  46  47  48  49
65                                       50  51  52  53  54  55  56  57  58  59
66                                       60  61  62  63  64  65  66  67  68  69
67                                       70  71  72  73  74  75  76  77  78  79
68                                       80  81  82  83  84  85  86  87  88  89
69                                       90  91  92  93  94  95  96  97  98  99
70                                      100 101 102 103 104 105 106 107 108 109
71                                      110 111 112 113 114 115 116 117 118 119
72                                      120 121 122 123 124 125 126 127 128 129
73                                      130 131 132 133 134 135 136 137 138 139
74                                      140 141 142 143 144 145 146 147 148 149
75                                      150 151 152 153 154 155 156 157 158 159
76                                      160 161 162 163 164 165 166 167 168 169
77                                      170 171 172 173 174 175 176 177 178 179
78                                      180 181 182 183 184 185 186 187 188 189
79                                      190 191 192 193 194 195 196 197 198 199
80                                      200 201 202 203 204 205 206 207 208 209
81                                      210 211 212 213 214 215 216 217 218 219
82                                      220 221 222 223 224 225 226 227 228 229
83                                      230 231 232 233 234 235 236 237 238 239
84                                      240 241 242 243 244 245 246 247 248 249
85                                      250 251 252 253 254 255>;
86                 default-brightness-level = <250>;
87                 enable-gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
88         };
89
90         reg_lvds: regulator-lvds {
91                 compatible = "regulator-fixed";
92                 regulator-name = "lvds_ppen";
93                 regulator-min-microvolt = <3300000>;
94                 regulator-max-microvolt = <3300000>;
95                 regulator-boot-on;
96                 regulator-always-on;
97                 pinctrl-names = "default";
98                 pinctrl-0 = <&pinctrl_reg_lvds>;
99                 gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>;
100                 enable-active-high;
101         };
102
103         reg_usbh1_vbus: usb-h1-vbus {
104                 compatible = "regulator-fixed";
105                 gpio = <&gpio3 31 GPIO_ACTIVE_LOW>;
106                 pinctrl-names = "default";
107                 pinctrl-0 = <&pinctrl_usbh1_vbus>;
108                 regulator-name = "usb_h1_vbus";
109                 regulator-min-microvolt = <5000000>;
110                 regulator-max-microvolt = <5000000>;
111                 regulator-enable-ramp-delay = <300000>;
112         };
113
114         sound {
115                 compatible = "simple-audio-card";
116                 label = "tfa9879-mono";
117
118                 simple-audio-card,dai-link {
119                         /* DAC */
120                         format = "i2s";
121                         bitclock-master = <&dailink_master>;
122                         frame-master = <&dailink_master>;
123
124                         dailink_master: cpu {
125                             sound-dai = <&ssi2>;
126                         };
127                         codec {
128                             sound-dai = <&codec>;
129                         };
130                 };
131         };
132
133         panel: panel-lvds0 {
134                 backlight = <&backlight_lvds>;
135                 power-supply = <&reg_lvds>;
136
137                 port {
138                         panel_in_lvds0: endpoint {
139                                 remote-endpoint = <&lvds0_out>;
140                         };
141                 };
142         };
143 };
144
145 &audmux {
146         pinctrl-names = "default";
147         pinctrl-0 = <&pinctrl_audmux>;
148         status = "okay";
149
150         ssi2 {
151                 fsl,audmux-port = <1>;
152                 fsl,port-config = <
153                         (IMX_AUDMUX_V2_PTCR_SYN |
154                          IMX_AUDMUX_V2_PTCR_TFSEL(5) |
155                          IMX_AUDMUX_V2_PTCR_TCSEL(5) |
156                          IMX_AUDMUX_V2_PTCR_TFSDIR |
157                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
158                         IMX_AUDMUX_V2_PDCR_RXDSEL(5)
159                 >;
160         };
161
162         aud6 {
163                 fsl,audmux-port = <5>;
164                 fsl,port-config = <
165                         (IMX_AUDMUX_V2_PTCR_RFSEL(8) |
166                          IMX_AUDMUX_V2_PTCR_RCSEL(8) |
167                          IMX_AUDMUX_V2_PTCR_TFSEL(1) |
168                          IMX_AUDMUX_V2_PTCR_TCSEL(1) |
169                          IMX_AUDMUX_V2_PTCR_RFSDIR |
170                          IMX_AUDMUX_V2_PTCR_RCLKDIR |
171                          IMX_AUDMUX_V2_PTCR_TFSDIR |
172                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
173                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
174                 >;
175         };
176 };
177
178 &ecspi2 {
179         cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
180         pinctrl-names = "default";
181         pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs &pinctrl_ecspi2_flwp>;
182         status = "okay";
183
184         s25fl256s: flash@0 {
185                 #address-cells = <1>;
186                 #size-cells = <1>;
187                 compatible = "jedec,spi-nor";
188                 spi-max-frequency = <40000000>;
189                 reg = <0>;
190
191                 partition@0 {
192                         label = "SPL (spi)";
193                         reg = <0x0 0x20000>;
194                         read-only;
195                 };
196                 partition@1 {
197                         label = "u-boot (spi)";
198                         reg = <0x20000 0x100000>;
199                         read-only;
200                 };
201                 partition@2 {
202                         label = "uboot-env (spi)";
203                         reg = <0x120000 0x10000>;
204                 };
205                 partition@3 {
206                         label = "uboot-envr (spi)";
207                         reg = <0x130000 0x10000>;
208                 };
209                 partition@4 {
210                         label = "linux-recovery (spi)";
211                         reg = <0x140000 0x800000>;
212                 };
213                 partition@5 {
214                         label = "swupdate-fitImg (spi)";
215                         reg = <0x940000 0x400000>;
216                 };
217                 partition@6 {
218                         label = "swupdate-initramfs (spi)";
219                         reg = <0xD40000 0x800000>;
220                 };
221         };
222 };
223
224 &ecspi3 {
225         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
226         pinctrl-names = "default";
227         pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>;
228         status = "okay";
229 };
230
231 &fec {
232         pinctrl-names = "default";
233         pinctrl-0 = <&pinctrl_enet>;
234         phy-handle = <&ethernet_phy0>;
235         phy-mode = "rgmii-id";
236         status = "okay";
237
238         mdio {
239                 #address-cells = <1>;
240                 #size-cells = <0>;
241                 ethernet_phy0: ethernet-phy@0 {
242                         compatible = "marvell,88E1510";
243                         device_type = "ethernet-phy";
244                         /* Set LED0 control: */
245                         /* On - Link, Blink - Activity, Off - No Link */
246                         marvell,reg-init = <3 0x10 0 0x1011>;
247                         max-speed = <100>;
248                         reg = <0>;
249                 };
250         };
251 };
252
253 &i2c1 {
254         clock-frequency = <400000>;
255         pinctrl-names = "default";
256         pinctrl-0 = <&pinctrl_i2c1>;
257         status = "okay";
258
259         codec: tfa9879@6c {
260                 #sound-dai-cells = <0>;
261                 compatible = "nxp,tfa9879";
262                 reg = <0x6C>;
263         };
264 };
265
266 &i2c2 {
267         clock-frequency = <400000>;
268         pinctrl-names = "default";
269         pinctrl-0 = <&pinctrl_i2c2>;
270         status = "okay";
271 };
272
273 &i2c3 {
274         clock-frequency = <400000>;
275         pinctrl-names = "default";
276         pinctrl-0 = <&pinctrl_i2c3>;
277         status = "okay";
278
279         at24@50 {
280                 compatible = "atmel,24c256";
281                 pagesize = <64>;
282                 reg = <0x50>;
283         };
284
285         pfuze100: pmic@8 {
286                 compatible = "fsl,pfuze100";
287                 reg = <0x08>;
288
289                 regulators {
290                         sw1a_reg: sw1ab {
291                                 regulator-min-microvolt = <300000>;
292                                 regulator-max-microvolt = <1875000>;
293                                 regulator-boot-on;
294                                 regulator-always-on;
295                                 regulator-ramp-delay = <6250>;
296                         };
297
298                         sw1c_reg: sw1c {
299                                 regulator-min-microvolt = <300000>;
300                                 regulator-max-microvolt = <1875000>;
301                                 regulator-boot-on;
302                                 regulator-always-on;
303                                 regulator-ramp-delay = <6250>;
304                         };
305
306                         sw2_reg: sw2 {
307                                 regulator-min-microvolt = <800000>;
308                                 regulator-max-microvolt = <3950000>;
309                                 regulator-boot-on;
310                                 regulator-always-on;
311                         };
312
313                         sw3a_reg: sw3a {
314                                 regulator-min-microvolt = <400000>;
315                                 regulator-max-microvolt = <1975000>;
316                                 regulator-boot-on;
317                                 regulator-always-on;
318                         };
319
320                         sw3b_reg: sw3b {
321                                 regulator-min-microvolt = <400000>;
322                                 regulator-max-microvolt = <1975000>;
323                                 regulator-boot-on;
324                                 regulator-always-on;
325                         };
326
327                         sw4_reg: sw4 {
328                                 regulator-min-microvolt = <800000>;
329                                 regulator-max-microvolt = <3300000>;
330                         };
331
332                         swbst_reg: swbst {
333                                 regulator-min-microvolt = <5000000>;
334                                 regulator-max-microvolt = <5150000>;
335                         };
336
337                         snvs_reg: vsnvs {
338                                 regulator-min-microvolt = <1000000>;
339                                 regulator-max-microvolt = <3000000>;
340                                 regulator-boot-on;
341                                 regulator-always-on;
342                         };
343
344                         vref_reg: vrefddr {
345                                 regulator-boot-on;
346                                 regulator-always-on;
347                         };
348
349                         vgen1_reg: vgen1 {
350                                 regulator-min-microvolt = <800000>;
351                                 regulator-max-microvolt = <1550000>;
352                         };
353
354                         vgen2_reg: vgen2 {
355                                 regulator-min-microvolt = <800000>;
356                                 regulator-max-microvolt = <1550000>;
357                         };
358
359                         vgen3_reg: vgen3 {
360                                 regulator-min-microvolt = <1800000>;
361                                 regulator-max-microvolt = <3300000>;
362                         };
363
364                         vgen4_reg: vgen4 {
365                                 regulator-min-microvolt = <1800000>;
366                                 regulator-max-microvolt = <3300000>;
367                                 regulator-always-on;
368                         };
369
370                         vgen5_reg: vgen5 {
371                                 regulator-min-microvolt = <1800000>;
372                                 regulator-max-microvolt = <3300000>;
373                                 regulator-always-on;
374                         };
375
376                         vgen6_reg: vgen6 {
377                                 regulator-min-microvolt = <1800000>;
378                                 regulator-max-microvolt = <3300000>;
379                                 regulator-always-on;
380                         };
381                 };
382         };
383 };
384
385 &ldb {
386         status = "okay";
387
388         lvds0: lvds-channel@0 {
389                 status = "okay";
390
391                 port@4 {
392                         reg = <4>;
393
394                         lvds0_out: endpoint {
395                                 remote-endpoint = <&panel_in_lvds0>;
396                         };
397                 };
398         };
399 };
400
401 &pwm2 {
402         #pwm-cells = <3>;
403         pinctrl-names = "default";
404         pinctrl-0 = <&pinctrl_pwm2>;
405         status = "okay";
406 };
407
408 &ssi2 {
409         status = "okay";
410 };
411
412 &uart4 {
413         pinctrl-names = "default";
414         pinctrl-0 = <&pinctrl_uart4>;
415         uart-has-rtscts;
416         status = "okay";
417 };
418
419 &uart5 {
420         pinctrl-names = "default";
421         pinctrl-0 = <&pinctrl_uart5>;
422         status = "okay";
423 };
424
425 &usbh1 {
426         vbus-supply = <&reg_usbh1_vbus>;
427         pinctrl-0 = <&pinctrl_usbh1>;
428         status = "okay";
429 };
430
431 &usdhc4 {
432         pinctrl-names = "default";
433         pinctrl-0 = <&pinctrl_usdhc4>;
434         bus-width = <8>;
435         non-removable;
436         status = "okay";
437 };
438
439 &iomuxc {
440         pinctrl_audmux: audmuxgrp {
441                 fsl,pins = <
442                         /* I2S OUTPUT AUD6*/
443                         MX6QDL_PAD_DI0_PIN4__AUD6_RXD  0x130b0
444                         MX6QDL_PAD_DI0_PIN2__AUD6_TXD  0x130b0
445                         MX6QDL_PAD_DI0_PIN3__AUD6_TXFS  0x130b0
446                         MX6QDL_PAD_DI0_PIN15__AUD6_TXC  0x130b0
447                 >;
448         };
449
450         pinctrl_backlight: dispgrp {
451                 fsl,pins = <
452                         /* BLEN_OUT */
453                         MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07    0x1b0b0
454                 >;
455         };
456
457         pinctrl_ecspi2: ecspi2grp {
458                 fsl,pins = <
459                         MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO      0x100b1
460                         MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI       0x100b1
461                         MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK       0x100b1
462                 >;
463         };
464
465         pinctrl_ecspi2_cs: ecspi2csgrp {
466                 fsl,pins = <
467                         MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1
468                 >;
469         };
470
471         pinctrl_ecspi2_flwp: ecspi2flwpgrp {
472                 fsl,pins = <
473                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
474                 >;
475         };
476
477         pinctrl_ecspi3: ecspi3grp {
478                 fsl,pins = <
479                         MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
480                         MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
481                         MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
482                 >;
483         };
484
485         pinctrl_ecspi3_cs: ecspi3csgrp {
486                 fsl,pins = <
487                         MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
488                 >;
489         };
490
491         pinctrl_ecspi3_flwp: ecspi3flwpgrp {
492                 fsl,pins = <
493                         MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
494                 >;
495         };
496
497         pinctrl_enet: enetgrp {
498                 fsl,pins = <
499                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
500                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
501                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
502                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
503                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
504                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
505                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
506                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
507                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
508                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
509                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
510                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
511                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
512                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
513                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
514                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
515                         MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
516                         MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x1b0b0
517                 >;
518         };
519
520         pinctrl_i2c1: i2c1grp {
521                 fsl,pins = <
522                         MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
523                         MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
524                 >;
525         };
526
527         pinctrl_i2c2: i2c2grp {
528                 fsl,pins = <
529                         MX6QDL_PAD_EIM_EB2__I2C2_SCL    0x4001b8b1
530                         MX6QDL_PAD_EIM_D16__I2C2_SDA    0x4001b8b1
531                 >;
532         };
533
534         pinctrl_i2c3: i2c3grp {
535                 fsl,pins = <
536                         MX6QDL_PAD_EIM_D17__I2C3_SCL    0x4001b8b1
537                         MX6QDL_PAD_EIM_D18__I2C3_SDA    0x4001b8b1
538                 >;
539         };
540
541         pinctrl_pwm2: pwm2grp {
542                 fsl,pins = <
543                         MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
544                 >;
545         };
546
547         pinctrl_reg_lvds: reqlvdsgrp {
548                 fsl,pins = <
549                         /* LVDS_PPEN_OUT */
550                         MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13      0x1b0b0
551                 >;
552         };
553
554         pinctrl_uart4: uart4grp {
555                 fsl,pins = <
556                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
557                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
558                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
559                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
560                 >;
561         };
562
563         pinctrl_uart5: uart5grp {
564                 fsl,pins = <
565                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x1b0b1
566                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x1b0b1
567                 >;
568         };
569
570         pinctrl_usbh1: usbh1grp {
571                 fsl,pins = <
572                         MX6QDL_PAD_EIM_D30__USB_H1_OC  0x030b0
573                 >;
574         };
575
576         pinctrl_usbh1_vbus: usbh1_vbus_grp {
577                 fsl,pins = <
578                         MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0
579                 >;
580         };
581
582         pinctrl_usdhc4: usdhc4grp {
583                 fsl,pins = <
584                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
585                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
586                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
587                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
588                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
589                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
590                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
591                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
592                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
593                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
594                         MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x17059
595                 >;
596         };
597 };